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mvebu dt64 for 4.16 (part 2)

Browse Source 
The main change here are the series of commits doing the Armada 7K/8K
 CP110 DT de-duplication, they include the de-duplication itself and
 small fixes in the device tree files.
 
 Besides them there are 2 other patches:
  - One adding the crypto support for Armada 37xx SoCs
  - An other adding Ethernet aliases on A7K/A8K base boards
 -----BEGIN PGP SIGNATURE-----
 
 iIEEABECAEEWIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCWk+h0CMcZ3JlZ29yeS5j
 bGVtZW50QGZyZWUtZWxlY3Ryb25zLmNvbQAKCRALBhiOFHI71ZU9AKCNLcEcewii
 UWPVUzEsQ/+UPojO4wCdHqum9OT33XChVrxHGKP89Dnj1ro=
 =HCIC
 -----END PGP SIGNATURE-----

Merge tag 'mvebu-dt64-4.16-2' of git://git.infradead.org/linux-mvebu into next/dt

Pull "mvebu dt64 for 4.16 (part 2)" from Gregory CLEMENT:

The main change here are the series of commits doing the Armada 7K/8K
CP110 DT de-duplication, they include the de-duplication itself and
small fixes in the device tree files.

Besides them there are 2 other patches:
 - One adding the crypto support for Armada 37xx SoCs
 - An other adding Ethernet aliases on A7K/A8K base boards

* tag 'mvebu-dt64-4.16-2' of git://git.infradead.org/linux-mvebu:
  arm64: dts: marvell: add Ethernet aliases
  arm64: dts: marvell: replace cpm by cp0, cps by cp1
  arm64: dts: marvell: de-duplicate CP110 description
  arm64: dts: marvell: use aliases for SPI busses on Armada 7K/8K
  arm64: dts: marvell: use mvebu-icu.h where possible
  arm64: dts: marvell: fix compatible string list for Armada CP110 slave NAND
  arm64: dts: marvell: fix typos in comment describing the NAND controller
  arm64: dts: marvell: use lower case for unit address and reg property
  arm64: dts: marvell: fix watchdog unit address in Armada AP806
  arm64: dts: marvell: armada-37xx: add a crypto node
  ARM64: dts: marvell: armada-cp110: Fix clock resources for various node
  ARM: dts: kirkwood: fix pin-muxing of MPP7 on OpenBlocks A7
This commit is contained in:
Arnd Bergmann 2018-01-05 17:17:25 +01:00
commit 8c11fcc212
14 changed files with 678 additions and 1027 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm/boot/dts/kirkwood-openblocks_a7.dts
View File

@ -53,7 +53,8 @@
};
pinctrl: pin-controller@10000 {
pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>;
pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header
&pmx_gpio_header_gpo>;
pinctrl-names = "default";
pmx_uart0: pmx-uart0 {
@ -85,11 +86,16 @@
* ground.
*/
pmx_gpio_header: pmx-gpio-header {
marvell,pins = "mpp17", "mpp7", "mpp29", "mpp28",
marvell,pins = "mpp17", "mpp29", "mpp28",
"mpp35", "mpp34", "mpp40";
marvell,function = "gpio";
};
pmx_gpio_header_gpo: pxm-gpio-header-gpo {
marvell,pins = "mpp7";
marvell,function = "gpo";
};
pmx_gpio_init: pmx-init {
marvell,pins = "mpp38";
marvell,function = "gpio";

14
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
View File

@ -316,6 +316,20 @@
};
};
crypto: crypto@90000 {
compatible = "inside-secure,safexcel-eip97";
reg = <0x90000 0x20000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
clocks = <&nb_periph_clk 15>;
};
sdhci1: sdhci@d0000 {
compatible = "marvell,armada-3700-sdhci",
"marvell,sdhci-xenon";

52
arch/arm64/boot/dts/marvell/armada-7040-db.dts
View File

@ -61,7 +61,13 @@
reg = <0x0 0x0 0x0 0x80000000>;
};
cpm_reg_usb3_0_vbus: cpm-usb3-0-vbus {
aliases {
ethernet0 = &cp0_eth0;
ethernet1 = &cp0_eth1;
ethernet2 = &cp0_eth2;
};
cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
compatible = "regulator-fixed";
regulator-name = "usb3h0-vbus";
regulator-min-microvolt = <5000000>;
@ -70,7 +76,7 @@
gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
};
cpm_reg_usb3_1_vbus: cpm-usb3-1-vbus {
cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb3h1-vbus";
regulator-min-microvolt = <5000000>;
@ -79,14 +85,14 @@
gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
};
cpm_usb3_0_phy: cpm-usb3-0-phy {
cp0_usb3_0_phy: cp0-usb3-0-phy {
compatible = "usb-nop-xceiv";
vcc-supply = <&cpm_reg_usb3_0_vbus>;
vcc-supply = <&cp0_reg_usb3_0_vbus>;
};
cpm_usb3_1_phy: cpm-usb3-1-phy {
cp0_usb3_1_phy: cp0-usb3-1-phy {
compatible = "usb-nop-xceiv";
vcc-supply = <&cpm_reg_usb3_1_vbus>;
vcc-supply = <&cp0_reg_usb3_1_vbus>;
};
};
@ -129,11 +135,11 @@
};
&cpm_pcie2 {
&cp0_pcie2 {
status = "okay";
};
&cpm_i2c0 {
&cp0_i2c0 {
status = "okay";
clock-frequency = <100000>;
@ -156,7 +162,7 @@
};
};
&cpm_nand {
&cp0_nand {
/*
* SPI on CPM and NAND have common pins on this board. We can
* use only one at a time. To enable the NAND (whihch will
@ -186,7 +192,7 @@
};
&cpm_spi1 {
&cp0_spi1 {
status = "okay";
spi-flash@0 {
@ -214,17 +220,17 @@
};
};
&cpm_sata0 {
&cp0_sata0 {
status = "okay";
};
&cpm_usb3_0 {
usb-phy = <&cpm_usb3_0_phy>;
&cp0_usb3_0 {
usb-phy = <&cp0_usb3_0_phy>;
status = "okay";
};
&cpm_usb3_1 {
usb-phy = <&cpm_usb3_1_phy>;
&cp0_usb3_1 {
usb-phy = <&cp0_usb3_1_phy>;
status = "okay";
};
@ -235,14 +241,14 @@
non-removable;
};
&cpm_sdhci0 {
&cp0_sdhci0 {
status = "okay";
bus-width = <4>;
no-1-8-v;
cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>;
};
&cpm_mdio {
&cp0_mdio {
status = "okay";
phy0: ethernet-phy@0 {
@ -253,28 +259,28 @@
};
};
&cpm_ethernet {
&cp0_ethernet {
status = "okay";
};
&cpm_eth0 {
&cp0_eth0 {
status = "okay";
/* Network PHY */
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
phys = <&cpm_comphy2 0>;
phys = <&cp0_comphy2 0>;
};
&cpm_eth1 {
&cp0_eth1 {
status = "okay";
/* Network PHY */
phy = <&phy0>;
phy-mode = "sgmii";
/* Generic PHY, providing serdes lanes */
phys = <&cpm_comphy0 1>;
phys = <&cp0_comphy0 1>;
};
&cpm_eth2 {
&cp0_eth2 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";

37
arch/arm64/boot/dts/marvell/armada-70x0.dtsi
View File

@ -44,25 +44,46 @@
* Device Tree file for the Armada 70x0 SoC
*/
#include "armada-cp110-master.dtsi"
/ {
aliases {
gpio1 = &cpm_gpio1;
gpio2 = &cpm_gpio2;
gpio1 = &cp0_gpio1;
gpio2 = &cp0_gpio2;
spi1 = &cp0_spi0;
spi2 = &cp0_spi1;
};
};
&cpm_gpio1 {
/*
* Instantiate the CP110
*/
#define CP110_NAME cp0
#define CP110_BASE f2000000
#define CP110_PCIE_IO_BASE 0xf9000000
#define CP110_PCIE_MEM_BASE 0xf6000000
#define CP110_PCIE0_BASE f2600000
#define CP110_PCIE1_BASE f2620000
#define CP110_PCIE2_BASE f2640000
#include "armada-cp110.dtsi"
#undef CP110_NAME
#undef CP110_BASE
#undef CP110_PCIE_IO_BASE
#undef CP110_PCIE_MEM_BASE
#undef CP110_PCIE0_BASE
#undef CP110_PCIE1_BASE
#undef CP110_PCIE2_BASE
&cp0_gpio1 {
status = "okay";
};
&cpm_gpio2 {
&cp0_gpio2 {
status = "okay";
};
&cpm_syscon0 {
cpm_pinctrl: pinctrl {
&cp0_syscon0 {
cp0_pinctrl: pinctrl {
compatible = "marvell,armada-7k-pinctrl";
nand_pins: nand-pins {

2
arch/arm64/boot/dts/marvell/armada-8020.dtsi
View File

@ -60,6 +60,6 @@
* oscillator so this one is let enabled.
*/
&cpm_rtc {
&cp0_rtc {
status = "disabled";
};

87
arch/arm64/boot/dts/marvell/armada-8040-db.dts
View File

@ -61,46 +61,53 @@
reg = <0x0 0x0 0x0 0x80000000>;
};
cpm_reg_usb3_0_vbus: cpm-usb3-0-vbus {
aliases {
ethernet0 = &cp0_eth0;
ethernet1 = &cp0_eth2;
ethernet2 = &cp1_eth0;
ethernet3 = &cp1_eth1;
};
cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
compatible = "regulator-fixed";
regulator-name = "cpm-usb3h0-vbus";
regulator-name = "cp0-usb3h0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
};
cpm_reg_usb3_1_vbus: cpm-usb3-1-vbus {
cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
compatible = "regulator-fixed";
regulator-name = "cpm-usb3h1-vbus";
regulator-name = "cp0-usb3h1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
};
cpm_usb3_0_phy: cpm-usb3-0-phy {
cp0_usb3_0_phy: cp0-usb3-0-phy {
compatible = "usb-nop-xceiv";
vcc-supply = <&cpm_reg_usb3_0_vbus>;
vcc-supply = <&cp0_reg_usb3_0_vbus>;
};
cpm_usb3_1_phy: cpm-usb3-1-phy {
cp0_usb3_1_phy: cp0-usb3-1-phy {
compatible = "usb-nop-xceiv";
vcc-supply = <&cpm_reg_usb3_1_vbus>;
vcc-supply = <&cp0_reg_usb3_1_vbus>;
};
cps_reg_usb3_0_vbus: cps-usb3-0-vbus {
cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {
compatible = "regulator-fixed";
regulator-name = "cps-usb3h0-vbus";
regulator-name = "cp1-usb3h0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
};
cps_usb3_0_phy: cps-usb3-0-phy {
cp1_usb3_0_phy: cp1-usb3-0-phy {
compatible = "usb-nop-xceiv";
vcc-supply = <&cps_reg_usb3_0_vbus>;
vcc-supply = <&cp1_reg_usb3_0_vbus>;
};
};
@ -144,16 +151,16 @@
};
/* CON6 on CP0 expansion */
&cpm_pcie0 {
&cp0_pcie0 {
status = "okay";
};
/* CON5 on CP0 expansion */
&cpm_pcie2 {
&cp0_pcie2 {
status = "okay";
};
&cpm_i2c0 {
&cp0_i2c0 {
status = "okay";
clock-frequency = <100000>;
@ -178,23 +185,23 @@
};
/* CON4 on CP0 expansion */
&cpm_sata0 {
&cp0_sata0 {
status = "okay";
};
/* CON9 on CP0 expansion */
&cpm_usb3_0 {
usb-phy = <&cpm_usb3_0_phy>;
&cp0_usb3_0 {
usb-phy = <&cp0_usb3_0_phy>;
status = "okay";
};
/* CON10 on CP0 expansion */
&cpm_usb3_1 {
usb-phy = <&cpm_usb3_1_phy>;
&cp0_usb3_1 {
usb-phy = <&cp0_usb3_1_phy>;
status = "okay";
};
&cpm_mdio {
&cp0_mdio {
status = "okay";
phy1: ethernet-phy@1 {
@ -202,42 +209,42 @@
};
};
&cpm_ethernet {
&cp0_ethernet {
status = "okay";
};
&cpm_eth0 {
&cp0_eth0 {
status = "okay";
phy-mode = "10gbase-kr";
};
&cpm_eth2 {
&cp0_eth2 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
/* CON6 on CP1 expansion */
&cps_pcie0 {
&cp1_pcie0 {
status = "okay";
};
/* CON7 on CP1 expansion */
&cps_pcie1 {
&cp1_pcie1 {
status = "okay";
};
/* CON5 on CP1 expansion */
&cps_pcie2 {
&cp1_pcie2 {
status = "okay";
};
&cps_i2c0 {
&cp1_i2c0 {
status = "okay";
clock-frequency = <100000>;
};
&cps_spi1 {
&cp1_spi1 {
status = "okay";
spi-flash@0 {
@ -272,14 +279,14 @@
* Proper NAND usage will require DPR-76 to be in position 1-2, which disables
* MDIO signal of CP1.
*/
&cps_nand {
&cp1_nand {
num-cs = <1>;
pinctrl-0 = <&nand_pins>, <&nand_rb>;
pinctrl-names = "default";
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
marvell,nand-enable-arbiter;
marvell,system-controller = <&cps_syscon0>;
marvell,system-controller = <&cp1_syscon0>;
nand-on-flash-bbt;
partition@0 {
@ -297,22 +304,22 @@
};
/* CON4 on CP1 expansion */
&cps_sata0 {
&cp1_sata0 {
status = "okay";
};
/* CON9 on CP1 expansion */
&cps_usb3_0 {
usb-phy = <&cps_usb3_0_phy>;
&cp1_usb3_0 {
usb-phy = <&cp1_usb3_0_phy>;
status = "okay";
};
/* CON10 on CP1 expansion */
&cps_usb3_1 {
&cp1_usb3_1 {
status = "okay";
};
&cps_mdio {
&cp1_mdio {
status = "okay";
phy0: ethernet-phy@0 {
@ -320,16 +327,16 @@
};
};
&cps_ethernet {
&cp1_ethernet {
status = "okay";
};
&cps_eth0 {
&cp1_eth0 {
status = "okay";
phy-mode = "10gbase-kr";
};
&cps_eth1 {
&cp1_eth1 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
@ -341,7 +348,7 @@
non-removable;
};
&cpm_sdhci0 {
&cp0_sdhci0 {
status = "okay";
bus-width = <8>;
non-removable;

82
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
View File

@ -62,6 +62,12 @@
reg = <0x0 0x0 0x0 0x80000000>;
};
aliases {
ethernet0 = &cp0_eth0;
ethernet1 = &cp1_eth0;
ethernet2 = &cp1_eth1;
};
/* Regulator labels correspond with schematics */
v_3_3: regulator-3-3v {
compatible = "regulator-fixed";
@ -84,9 +90,9 @@
v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&cpm_gpio2 15 GPIO_ACTIVE_HIGH>;
gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&cpm_xhci_vbus_pins>;
pinctrl-0 = <&cp0_xhci_vbus_pins>;
regulator-name = "v_5v0_usb3_hst_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@ -120,17 +126,17 @@
vqmmc-supply = <&v_vddo_h>;
};
&cpm_i2c0 {
&cp0_i2c0 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&cpm_i2c0_pins>;
pinctrl-0 = <&cp0_i2c0_pins>;
status = "okay";
};
&cpm_i2c1 {
&cp0_i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&cpm_i2c1_pins>;
pinctrl-0 = <&cp0_i2c1_pins>;
status = "okay";
i2c-switch@70 {
@ -157,9 +163,9 @@
};
};
&cpm_mdio {
&cp0_mdio {
pinctrl-names = "default";
pinctrl-0 = <&cpm_ge_mdio_pins>;
pinctrl-0 = <&cp0_ge_mdio_pins>;
status = "okay";
ge_phy: ethernet-phy@0 {
@ -167,44 +173,44 @@
};
};
&cpm_pcie0 {
&cp0_pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&cpm_pcie_pins>;
pinctrl-0 = <&cp0_pcie_pins>;
num-lanes = <4>;
num-viewport = <8>;
reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>;
reset-gpio = <&cp0_gpio1 20 GPIO_ACTIVE_LOW>;
status = "okay";
};
&cpm_pinctrl {
cpm_ge_mdio_pins: ge-mdio-pins {
&cp0_pinctrl {
cp0_ge_mdio_pins: ge-mdio-pins {
marvell,pins = "mpp32", "mpp34";
marvell,function = "ge";
};
cpm_i2c1_pins: i2c1-pins {
cp0_i2c1_pins: i2c1-pins {
marvell,pins = "mpp35", "mpp36";
marvell,function = "i2c1";
};
cpm_i2c0_pins: i2c0-pins {
cp0_i2c0_pins: i2c0-pins {
marvell,pins = "mpp37", "mpp38";
marvell,function = "i2c0";
};
cpm_xhci_vbus_pins: xhci0-vbus-pins {
cp0_xhci_vbus_pins: xhci0-vbus-pins {
marvell,pins = "mpp47";
marvell,function = "gpio";
};
cpm_pcie_pins: pcie-pins {
cp0_pcie_pins: pcie-pins {
marvell,pins = "mpp52";
marvell,function = "gpio";
};
cpm_sdhci_pins: sdhci-pins {
cp0_sdhci_pins: sdhci-pins {
marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
"mpp60", "mpp61";
marvell,function = "sdio";
};
};
&cpm_xmdio {
&cp0_xmdio {
status = "okay";
phy0: ethernet-phy@0 {
@ -218,83 +224,83 @@
};
};
&cpm_ethernet {
&cp0_ethernet {
status = "okay";
};
&cpm_eth0 {
&cp0_eth0 {
status = "okay";
/* Network PHY */
phy = <&phy0>;
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
phys = <&cpm_comphy4 0>;
phys = <&cp0_comphy4 0>;
};
&cpm_sata0 {
&cp0_sata0 {
/* CPM Lane 0 - U29 */
status = "okay";
};
&cpm_sdhci0 {
&cp0_sdhci0 {
/* U6 */
broken-cd;
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&cpm_sdhci_pins>;
pinctrl-0 = <&cp0_sdhci_pins>;
status = "okay";
vqmmc-supply = <&v_3_3>;
};
&cpm_usb3_0 {
&cp0_usb3_0 {
/* J38? - USB2.0 only */
status = "okay";
};
&cpm_usb3_1 {
&cp0_usb3_1 {
/* J38? - USB2.0 only */
status = "okay";
};
&cps_ethernet {
&cp1_ethernet {
status = "okay";
};
&cps_eth0 {
&cp1_eth0 {
status = "okay";
/* Network PHY */
phy = <&phy8>;
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
phys = <&cps_comphy4 0>;
phys = <&cp1_comphy4 0>;
};
&cps_eth1 {
&cp1_eth1 {
/* CPS Lane 0 - J5 (Gigabit RJ45) */
status = "okay";
/* Network PHY */
phy = <&ge_phy>;
phy-mode = "sgmii";
/* Generic PHY, providing serdes lanes */
phys = <&cps_comphy0 1>;
phys = <&cp1_comphy0 1>;
};
&cps_pinctrl {
cps_spi1_pins: spi1-pins {
&cp1_pinctrl {
cp1_spi1_pins: spi1-pins {
marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
marvell,function = "spi1";
};
};
&cps_sata0 {
&cp1_sata0 {
/* CPS Lane 1 - U32 */
/* CPS Lane 3 - U31 */
status = "okay";
};
&cps_spi1 {
&cp1_spi1 {
pinctrl-names = "default";
pinctrl-0 = <&cps_spi1_pins>;
pinctrl-0 = <&cp1_spi1_pins>;
status = "okay";
spi-flash@0 {
@ -304,7 +310,7 @@
};
};
&cps_usb3_0 {
&cp1_usb3_0 {
/* CPS Lane 2 - CON7 */
usb-phy = <&usb3h0_phy>;
status = "okay";

2
arch/arm64/boot/dts/marvell/armada-8040.dtsi
View File

@ -59,6 +59,6 @@
* disable it. However, the RTC clock in CP slave is connected to the
* oscillator so this one is let enabled.
*/
&cpm_rtc {
&cp0_rtc {
status = "disabled";
};

80
arch/arm64/boot/dts/marvell/armada-80x0.dtsi
View File

@ -44,34 +44,77 @@
* Device Tree file for the Armada 80x0 SoC family
*/
#include "armada-cp110-master.dtsi"
#include "armada-cp110-slave.dtsi"
/ {
aliases {
gpio1 = &cps_gpio1;
gpio2 = &cpm_gpio2;
gpio1 = &cp1_gpio1;
gpio2 = &cp0_gpio2;
spi1 = &cp0_spi0;
spi2 = &cp0_spi1;
spi3 = &cp1_spi0;
spi4 = &cp1_spi1;
};
};
/*
* Instantiate the master CP110
*/
#define CP110_NAME cp0
#define CP110_BASE f2000000
#define CP110_PCIE_IO_BASE 0xf9000000
#define CP110_PCIE_MEM_BASE 0xf6000000
#define CP110_PCIE0_BASE f2600000
#define CP110_PCIE1_BASE f2620000
#define CP110_PCIE2_BASE f2640000
#include "armada-cp110.dtsi"
#undef CP110_NAME
#undef CP110_BASE
#undef CP110_PCIE_IO_BASE
#undef CP110_PCIE_MEM_BASE
#undef CP110_PCIE0_BASE
#undef CP110_PCIE1_BASE
#undef CP110_PCIE2_BASE
/*
* Instantiate the slave CP110
*/
#define CP110_NAME cp1
#define CP110_BASE f4000000
#define CP110_PCIE_IO_BASE 0xfd000000
#define CP110_PCIE_MEM_BASE 0xfa000000
#define CP110_PCIE0_BASE f4600000
#define CP110_PCIE1_BASE f4620000
#define CP110_PCIE2_BASE f4640000
#include "armada-cp110.dtsi"
#undef CP110_NAME
#undef CP110_BASE
#undef CP110_PCIE_IO_BASE
#undef CP110_PCIE_MEM_BASE
#undef CP110_PCIE0_BASE
#undef CP110_PCIE1_BASE
#undef CP110_PCIE2_BASE
/* The 80x0 has two CP blocks, but uses only one block from each. */
&cps_gpio1 {
&cp1_gpio1 {
status = "okay";
};
&cpm_gpio2 {
&cp0_gpio2 {
status = "okay";
};
&cpm_syscon0 {
cpm_pinctrl: pinctrl {
compatible = "marvell,armada-8k-cpm-pinctrl";
&cp0_syscon0 {
cp0_pinctrl: pinctrl {
compatible = "marvell,armada-8k-cp0-pinctrl";
};
};
&cps_syscon0 {
cps_pinctrl: pinctrl {
compatible = "marvell,armada-8k-cps-pinctrl";
&cp1_syscon0 {
cp1_pinctrl: pinctrl {
compatible = "marvell,armada-8k-cp1-pinctrl";
nand_pins: nand-pins {
marvell,pins =
@ -91,3 +134,14 @@
};
};
};
&cp1_crypto {
/*
* The cryptographic engine found on the cp110
* master is enabled by default at the SoC
* level. Because it is not possible as of now
* to enable two cryptographic engines in
* parallel, disable this one by default.
*/
status = "disabled";
};

8
arch/arm64/boot/dts/marvell/armada-ap806.dtsi
View File

@ -58,6 +58,7 @@
serial0 = &uart0;
serial1 = &uart1;
gpio0 = &ap_gpio;
spi0 = &spi0;
};
psci {
@ -203,7 +204,6 @@
reg = <0x510600 0x50>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ap_clk 3>;
status = "disabled";
@ -241,7 +241,7 @@
};
watchdog: watchdog@600000 {
watchdog: watchdog@610000 {
compatible = "arm,sbsa-gwdt";
reg = <0x610000 0x1000>, <0x600000 0x1000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
@ -286,9 +286,9 @@
};
};
ap_thermal: thermal@6f808C {
ap_thermal: thermal@6f808c {
compatible = "marvell,armada-ap806-thermal";
reg = <0x6f808C 0x4>,
reg = <0x6f808c 0x4>,
<0x6f8084 0x8>;
};
};

10
arch/arm64/boot/dts/marvell/armada-common.dtsi Normal file
View File

@ -0,0 +1,10 @@
// SPDX-License-Identifier: (GPL-2.0+ OR X11)
/*
* Copyright (C) 2016 Marvell Technology Group Ltd.
*/
/* Common definitions used by Armada 7K/8K DTs */
#define PASTER(x, y) x ## y
#define EVALUATOR(x, y) PASTER(x, y)
#define CP110_LABEL(name) EVALUATOR(CP110_NAME, EVALUATOR(_, name))
#define ADDRESSIFY(addr) EVALUATOR(0x, addr)

449
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
View File

@ -1,449 +0,0 @@
/*
* Copyright (C) 2016 Marvell Technology Group Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Device Tree file for Marvell Armada CP110 Master.
*/
#define ICU_GRP_NSR 0x0
/ {
cp110-master {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
interrupt-parent = <&cpm_icu>;
ranges;
config-space@f2000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x0 0x0 0xf2000000 0x2000000>;
cpm_ethernet: ethernet@0 {
compatible = "marvell,armada-7k-pp22";
reg = <0x0 0x100000>, <0x129000 0xb000>;
clocks = <&cpm_clk 1 3>, <&cpm_clk 1 9>, <&cpm_clk 1 5>;
clock-names = "pp_clk", "gop_clk", "mg_clk";
marvell,system-controller = <&cpm_syscon0>;
status = "disabled";
dma-coherent;
cpm_eth0: eth0 {
interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared", "link";
port-id = <0>;
gop-port-id = <0>;
status = "disabled";
};
cpm_eth1: eth1 {
interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared", "link";
port-id = <1>;
gop-port-id = <2>;
status = "disabled";
};
cpm_eth2: eth2 {
interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared", "link";
port-id = <2>;
gop-port-id = <3>;
status = "disabled";
};
};
cpm_comphy: phy@120000 {
compatible = "marvell,comphy-cp110";
reg = <0x120000 0x6000>;
marvell,system-controller = <&cpm_syscon0>;
#address-cells = <1>;
#size-cells = <0>;
cpm_comphy0: phy@0 {
reg = <0>;
#phy-cells = <1>;
};
cpm_comphy1: phy@1 {
reg = <1>;
#phy-cells = <1>;
};
cpm_comphy2: phy@2 {
reg = <2>;
#phy-cells = <1>;
};
cpm_comphy3: phy@3 {
reg = <3>;
#phy-cells = <1>;
};
cpm_comphy4: phy@4 {
reg = <4>;
#phy-cells = <1>;
};
cpm_comphy5: phy@5 {
reg = <5>;
#phy-cells = <1>;
};
};
cpm_mdio: mdio@12a200 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
reg = <0x12a200 0x10>;
clocks = <&cpm_clk 1 9>, <&cpm_clk 1 5>;
status = "disabled";
};
cpm_xmdio: mdio@12a600 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,xmdio";
reg = <0x12a600 0x10>;
status = "disabled";
};
cpm_icu: interrupt-controller@1e0000 {
compatible = "marvell,cp110-icu";
reg = <0x1e0000 0x10>;
#interrupt-cells = <3>;
interrupt-controller;
msi-parent = <&gicp>;
};
cpm_rtc: rtc@284000 {
compatible = "marvell,armada-8k-rtc";
reg = <0x284000 0x20>, <0x284080 0x24>;
reg-names = "rtc", "rtc-soc";
interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
};
cpm_thermal: thermal@400078 {
compatible = "marvell,armada-cp110-thermal";
reg = <0x400078 0x4>,
<0x400070 0x8>;
};
cpm_syscon0: system-controller@440000 {
compatible = "syscon", "simple-mfd";
reg = <0x440000 0x2000>;
cpm_clk: clock {
compatible = "marvell,cp110-clock";
#clock-cells = <2>;
};
cpm_gpio1: gpio@100 {
compatible = "marvell,armada-8k-gpio";
offset = <0x100>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&cpm_pinctrl 0 0 32>;
interrupt-controller;
interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
cpm_gpio2: gpio@140 {
compatible = "marvell,armada-8k-gpio";
offset = <0x140>;
ngpios = <31>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&cpm_pinctrl 0 32 31>;
interrupt-controller;
interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
cpm_usb3_0: usb3@500000 {
compatible = "marvell,armada-8k-xhci",
"generic-xhci";
reg = <0x500000 0x4000>;
dma-coherent;
interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_clk 1 22>;
status = "disabled";
};
cpm_usb3_1: usb3@510000 {
compatible = "marvell,armada-8k-xhci",
"generic-xhci";
reg = <0x510000 0x4000>;
dma-coherent;
interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_clk 1 23>;
status = "disabled";
};
cpm_sata0: sata@540000 {
compatible = "marvell,armada-8k-ahci",
"generic-ahci";
reg = <0x540000 0x30000>;
interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_clk 1 15>;
status = "disabled";
};
cpm_xor0: xor@6a0000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x6a0000 0x1000>,
<0x6b0000 0x1000>;
dma-coherent;
msi-parent = <&gic_v2m0>;
clocks = <&cpm_clk 1 8>;
};
cpm_xor1: xor@6c0000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x6c0000 0x1000>,
<0x6d0000 0x1000>;
dma-coherent;
msi-parent = <&gic_v2m0>;
clocks = <&cpm_clk 1 7>;
};
cpm_spi0: spi@700600 {
compatible = "marvell,armada-380-spi";
reg = <0x700600 0x50>;
#address-cells = <0x1>;
#size-cells = <0x0>;
cell-index = <1>;
clocks = <&cpm_clk 1 21>;
status = "disabled";
};
cpm_spi1: spi@700680 {
compatible = "marvell,armada-380-spi";
reg = <0x700680 0x50>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <2>;
clocks = <&cpm_clk 1 21>;
status = "disabled";
};
cpm_i2c0: i2c@701000 {
compatible = "marvell,mv78230-i2c";
reg = <0x701000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_clk 1 21>;
status = "disabled";
};
cpm_i2c1: i2c@701100 {
compatible = "marvell,mv78230-i2c";
reg = <0x701100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_clk 1 21>;
status = "disabled";
};
cpm_nand: nand@720000 {
/*
* Due to the limiation of the pin available
* this controller is only usable on the CPM
* for A7K and on the CPS for A8K.
*/
compatible = "marvell,armada-8k-nand",
"marvell,armada370-nand";
reg = <0x720000 0x54>;
#address-cells = <1>;
#size-cells = <1>;
interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_clk 1 2>;
marvell,system-controller = <&cpm_syscon0>;
status = "disabled";
};
cpm_trng: trng@760000 {
compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
reg = <0x760000 0x7d>;
interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_clk 1 25>;
status = "okay";
};
cpm_sdhci0: sdhci@780000 {
compatible = "marvell,armada-cp110-sdhci";
reg = <0x780000 0x300>;
interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core";
clocks = <&cpm_clk 1 4>;
dma-coherent;
status = "disabled";
};
cpm_crypto: crypto@800000 {
compatible = "inside-secure,safexcel-eip197";
reg = <0x800000 0x200000>;
interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
clocks = <&cpm_clk 1 26>;
dma-coherent;
};
};
cpm_pcie0: pcie@f2600000 {
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
reg = <0 0xf2600000 0 0x10000>,
<0 0xf6f00000 0 0x80000>;
reg-names = "ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
dma-coherent;
msi-parent = <&gic_v2m0>;
bus-range = <0 0xff>;
ranges =
/* downstream I/O */
<0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000
/* non-prefetchable memory */
0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &cpm_icu ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cpm_clk 1 13>;
status = "disabled";
};
cpm_pcie1: pcie@f2620000 {
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
reg = <0 0xf2620000 0 0x10000>,
<0 0xf7f00000 0 0x80000>;
reg-names = "ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
dma-coherent;
msi-parent = <&gic_v2m0>;
bus-range = <0 0xff>;
ranges =
/* downstream I/O */
<0x81000000 0 0xf9010000 0 0xf9010000 0 0x10000
/* non-prefetchable memory */
0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &cpm_icu ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cpm_clk 1 11>;
status = "disabled";
};
cpm_pcie2: pcie@f2640000 {
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
reg = <0 0xf2640000 0 0x10000>,
<0 0xf8f00000 0 0x80000>;
reg-names = "ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
dma-coherent;
msi-parent = <&gic_v2m0>;
bus-range = <0 0xff>;
ranges =
/* downstream I/O */
<0x81000000 0 0xf9020000 0 0xf9020000 0 0x10000
/* non-prefetchable memory */
0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &cpm_icu ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cpm_clk 1 12>;
status = "disabled";
};
};
};

448
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
View File

@ -1,448 +0,0 @@
/*
* Copyright (C) 2016 Marvell Technology Group Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Device Tree file for Marvell Armada CP110 Slave.
*/
#define ICU_GRP_NSR 0x0
/ {
cp110-slave {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
interrupt-parent = <&cps_icu>;
ranges;
config-space@f4000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x0 0x0 0xf4000000 0x2000000>;
cps_ethernet: ethernet@0 {
compatible = "marvell,armada-7k-pp22";
reg = <0x0 0x100000>, <0x129000 0xb000>;
clocks = <&cps_clk 1 3>, <&cps_clk 1 9>, <&cps_clk 1 5>;
clock-names = "pp_clk", "gop_clk", "mg_clk";
marvell,system-controller = <&cps_syscon0>;
status = "disabled";
dma-coherent;
cps_eth0: eth0 {
interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared", "link";
port-id = <0>;
gop-port-id = <0>;
status = "disabled";
};
cps_eth1: eth1 {
interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared", "link";
port-id = <1>;
gop-port-id = <2>;
status = "disabled";
};
cps_eth2: eth2 {
interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared", "link";
port-id = <2>;
gop-port-id = <3>;
status = "disabled";
};
};
cps_comphy: phy@120000 {
compatible = "marvell,comphy-cp110";
reg = <0x120000 0x6000>;
marvell,system-controller = <&cps_syscon0>;
#address-cells = <1>;
#size-cells = <0>;
cps_comphy0: phy@0 {
reg = <0>;
#phy-cells = <1>;
};
cps_comphy1: phy@1 {
reg = <1>;
#phy-cells = <1>;
};
cps_comphy2: phy@2 {
reg = <2>;
#phy-cells = <1>;
};
cps_comphy3: phy@3 {
reg = <3>;
#phy-cells = <1>;
};
cps_comphy4: phy@4 {
reg = <4>;
#phy-cells = <1>;
};
cps_comphy5: phy@5 {
reg = <5>;
#phy-cells = <1>;
};
};
cps_mdio: mdio@12a200 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
reg = <0x12a200 0x10>;
clocks = <&cps_clk 1 9>, <&cps_clk 1 5>;
status = "disabled";
};
cps_xmdio: mdio@12a600 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,xmdio";
reg = <0x12a600 0x10>;
status = "disabled";
};
cps_icu: interrupt-controller@1e0000 {
compatible = "marvell,cp110-icu";
reg = <0x1e0000 0x10>;
#interrupt-cells = <3>;
interrupt-controller;
msi-parent = <&gicp>;
};
cps_rtc: rtc@284000 {
compatible = "marvell,armada-8k-rtc";
reg = <0x284000 0x20>, <0x284080 0x24>;
reg-names = "rtc", "rtc-soc";
interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
};
cps_thermal: thermal@400078 {
compatible = "marvell,armada-cp110-thermal";
reg = <0x400078 0x4>,
<0x400070 0x8>;
};
cps_syscon0: system-controller@440000 {
compatible = "syscon", "simple-mfd";
reg = <0x440000 0x2000>;
cps_clk: clock {
compatible = "marvell,cp110-clock";
#clock-cells = <2>;
};
cps_gpio1: gpio@100 {
compatible = "marvell,armada-8k-gpio";
offset = <0x100>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&cps_pinctrl 0 0 32>;
interrupt-controller;
interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
cps_gpio2: gpio@140 {
compatible = "marvell,armada-8k-gpio";
offset = <0x140>;
ngpios = <31>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&cps_pinctrl 0 32 31>;
interrupt-controller;
interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
cps_usb3_0: usb3@500000 {
compatible = "marvell,armada-8k-xhci",
"generic-xhci";
reg = <0x500000 0x4000>;
dma-coherent;
interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_clk 1 22>;
status = "disabled";
};
cps_usb3_1: usb3@510000 {
compatible = "marvell,armada-8k-xhci",
"generic-xhci";
reg = <0x510000 0x4000>;
dma-coherent;
interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_clk 1 23>;
status = "disabled";
};
cps_sata0: sata@540000 {
compatible = "marvell,armada-8k-ahci",
"generic-ahci";
reg = <0x540000 0x30000>;
interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_clk 1 15>;
status = "disabled";
};
cps_xor0: xor@6a0000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x6a0000 0x1000>,
<0x6b0000 0x1000>;
dma-coherent;
msi-parent = <&gic_v2m0>;
clocks = <&cps_clk 1 8>;
};
cps_xor1: xor@6c0000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x6c0000 0x1000>,
<0x6d0000 0x1000>;
dma-coherent;
msi-parent = <&gic_v2m0>;
clocks = <&cps_clk 1 7>;
};
cps_spi0: spi@700600 {
compatible = "marvell,armada-380-spi";
reg = <0x700600 0x50>;
#address-cells = <0x1>;
#size-cells = <0x0>;
cell-index = <3>;
clocks = <&cps_clk 1 21>;
status = "disabled";
};
cps_spi1: spi@700680 {
compatible = "marvell,armada-380-spi";
reg = <0x700680 0x50>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <4>;
clocks = <&cps_clk 1 21>;
status = "disabled";
};
cps_i2c0: i2c@701000 {
compatible = "marvell,mv78230-i2c";
reg = <0x701000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_clk 1 21>;
status = "disabled";
};
cps_i2c1: i2c@701100 {
compatible = "marvell,mv78230-i2c";
reg = <0x701100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_clk 1 21>;
status = "disabled";
};
cps_nand: nand@720000 {
/*
* Due to the limiation of the pin available
* this controller is only usable on the CPM
* for A7K and on the CPS for A8K.
*/
compatible = "marvell,armada370-nand",
"marvell,armada-8k-nand";
reg = <0x720000 0x54>;
#address-cells = <1>;
#size-cells = <1>;
interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_clk 1 2>;
marvell,system-controller = <&cpm_syscon0>;
status = "disabled";
};
cps_trng: trng@760000 {
compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
reg = <0x760000 0x7d>;
interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_clk 1 25>;
status = "okay";
};
cps_crypto: crypto@800000 {
compatible = "inside-secure,safexcel-eip197";
reg = <0x800000 0x200000>;
interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
clocks = <&cps_clk 1 26>;
dma-coherent;
/*
* The cryptographic engine found on the cp110
* master is enabled by default at the SoC
* level. Because it is not possible as of now
* to enable two cryptographic engines in
* parallel, disable this one by default.
*/
status = "disabled";
};
};
cps_pcie0: pcie@f4600000 {
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
reg = <0 0xf4600000 0 0x10000>,
<0 0xfaf00000 0 0x80000>;
reg-names = "ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
dma-coherent;
msi-parent = <&gic_v2m0>;
bus-range = <0 0xff>;
ranges =
/* downstream I/O */
<0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000
/* non-prefetchable memory */
0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cps_clk 1 13>;
status = "disabled";
};
cps_pcie1: pcie@f4620000 {
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
reg = <0 0xf4620000 0 0x10000>,
<0 0xfbf00000 0 0x80000>;
reg-names = "ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
dma-coherent;
msi-parent = <&gic_v2m0>;
bus-range = <0 0xff>;
ranges =
/* downstream I/O */
<0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000
/* non-prefetchable memory */
0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cps_clk 1 11>;
status = "disabled";
};
cps_pcie2: pcie@f4640000 {
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
reg = <0 0xf4640000 0 0x10000>,
<0 0xfcf00000 0 0x80000>;
reg-names = "ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
dma-coherent;
msi-parent = <&gic_v2m0>;
bus-range = <0 0xff>;
ranges =
/* downstream I/O */
<0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000
/* non-prefetchable memory */
0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cps_clk 1 12>;
status = "disabled";
};
};
};

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arch/arm64/boot/dts/marvell/armada-cp110.dtsi Normal file
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// SPDX-License-Identifier: (GPL-2.0+ OR X11)
/*
* Copyright (C) 2016 Marvell Technology Group Ltd.
*/
/*
* Device Tree file for Marvell Armada CP110.
*/
#include <dt-bindings/interrupt-controller/mvebu-icu.h>
#include "armada-common.dtsi"
#define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * 0x10000))
#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface * 0x1000000))
#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0xf00000)
/ {
/*
* The contents of the node are defined below, in order to
* save one indentation level
*/
CP110_NAME: CP110_NAME { };
};
&CP110_NAME {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
interrupt-parent = <&CP110_LABEL(icu)>;
ranges;
config-space@CP110_BASE {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>;
CP110_LABEL(ethernet): ethernet@0 {
compatible = "marvell,armada-7k-pp22";
reg = <0x0 0x100000>, <0x129000 0xb000>;
clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>,
<&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 18>;
clock-names = "pp_clk", "gop_clk",
"mg_clk", "axi_clk";
marvell,system-controller = <&CP110_LABEL(syscon0)>;
status = "disabled";
dma-coherent;
CP110_LABEL(eth0): eth0 {
interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared", "link";
port-id = <0>;
gop-port-id = <0>;
status = "disabled";
};
CP110_LABEL(eth1): eth1 {
interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared", "link";
port-id = <1>;
gop-port-id = <2>;
status = "disabled";
};
CP110_LABEL(eth2): eth2 {
interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared", "link";
port-id = <2>;
gop-port-id = <3>;
status = "disabled";
};
};
CP110_LABEL(comphy): phy@120000 {
compatible = "marvell,comphy-cp110";
reg = <0x120000 0x6000>;
marvell,system-controller = <&CP110_LABEL(syscon0)>;
#address-cells = <1>;
#size-cells = <0>;
CP110_LABEL(comphy0): phy@0 {
reg = <0>;
#phy-cells = <1>;
};
CP110_LABEL(comphy1): phy@1 {
reg = <1>;
#phy-cells = <1>;
};
CP110_LABEL(comphy2): phy@2 {
reg = <2>;
#phy-cells = <1>;
};
CP110_LABEL(comphy3): phy@3 {
reg = <3>;
#phy-cells = <1>;
};
CP110_LABEL(comphy4): phy@4 {
reg = <4>;
#phy-cells = <1>;
};
CP110_LABEL(comphy5): phy@5 {
reg = <5>;
#phy-cells = <1>;
};
};
CP110_LABEL(mdio): mdio@12a200 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
reg = <0x12a200 0x10>;
clocks = <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(clk) 1 5>,
<&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
status = "disabled";
};
CP110_LABEL(xmdio): mdio@12a600 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,xmdio";
reg = <0x12a600 0x10>;
status = "disabled";
};
CP110_LABEL(icu): interrupt-controller@1e0000 {
compatible = "marvell,cp110-icu";
reg = <0x1e0000 0x10>;
#interrupt-cells = <3>;
interrupt-controller;
msi-parent = <&gicp>;
};
CP110_LABEL(rtc): rtc@284000 {
compatible = "marvell,armada-8k-rtc";
reg = <0x284000 0x20>, <0x284080 0x24>;
reg-names = "rtc", "rtc-soc";
interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
};
CP110_LABEL(thermal): thermal@400078 {
compatible = "marvell,armada-cp110-thermal";
reg = <0x400078 0x4>,
<0x400070 0x8>;
};
CP110_LABEL(syscon0): system-controller@440000 {
compatible = "syscon", "simple-mfd";
reg = <0x440000 0x2000>;
CP110_LABEL(clk): clock {
compatible = "marvell,cp110-clock";
#clock-cells = <2>;
};
CP110_LABEL(gpio1): gpio@100 {
compatible = "marvell,armada-8k-gpio";
offset = <0x100>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
interrupt-controller;
interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
CP110_LABEL(gpio2): gpio@140 {
compatible = "marvell,armada-8k-gpio";
offset = <0x140>;
ngpios = <31>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>;
interrupt-controller;
interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
CP110_LABEL(usb3_0): usb3@500000 {
compatible = "marvell,armada-8k-xhci",
"generic-xhci";
reg = <0x500000 0x4000>;
dma-coherent;
interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&CP110_LABEL(clk) 1 22>;
status = "disabled";
};
CP110_LABEL(usb3_1): usb3@510000 {
compatible = "marvell,armada-8k-xhci",
"generic-xhci";
reg = <0x510000 0x4000>;
dma-coherent;
interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&CP110_LABEL(clk) 1 23>;
status = "disabled";
};
CP110_LABEL(sata0): sata@540000 {
compatible = "marvell,armada-8k-ahci",
"generic-ahci";
reg = <0x540000 0x30000>;
interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&CP110_LABEL(clk) 1 15>;
status = "disabled";
};
CP110_LABEL(xor0): xor@6a0000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
dma-coherent;
msi-parent = <&gic_v2m0>;
clocks = <&CP110_LABEL(clk) 1 8>;
};
CP110_LABEL(xor1): xor@6c0000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
dma-coherent;
msi-parent = <&gic_v2m0>;
clocks = <&CP110_LABEL(clk) 1 7>;
};
CP110_LABEL(spi0): spi@700600 {
compatible = "marvell,armada-380-spi";
reg = <0x700600 0x50>;
#address-cells = <0x1>;
#size-cells = <0x0>;
clocks = <&CP110_LABEL(clk) 1 21>;
status = "disabled";
};
CP110_LABEL(spi1): spi@700680 {
compatible = "marvell,armada-380-spi";
reg = <0x700680 0x50>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&CP110_LABEL(clk) 1 21>;
status = "disabled";
};
CP110_LABEL(i2c0): i2c@701000 {
compatible = "marvell,mv78230-i2c";
reg = <0x701000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&CP110_LABEL(clk) 1 21>;
status = "disabled";
};
CP110_LABEL(i2c1): i2c@701100 {
compatible = "marvell,mv78230-i2c";
reg = <0x701100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&CP110_LABEL(clk) 1 21>;
status = "disabled";
};
CP110_LABEL(nand): nand@720000 {
/*
* Due to the limitation of the pins available
* this controller is only usable on the CPM
* for A7K and on the CPS for A8K.
*/
compatible = "marvell,armada-8k-nand",
"marvell,armada370-nand";
reg = <0x720000 0x54>;
#address-cells = <1>;
#size-cells = <1>;
interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&CP110_LABEL(clk) 1 2>;
marvell,system-controller = <&CP110_LABEL(syscon0)>;
status = "disabled";
};
CP110_LABEL(trng): trng@760000 {
compatible = "marvell,armada-8k-rng",
"inside-secure,safexcel-eip76";
reg = <0x760000 0x7d>;
interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&CP110_LABEL(clk) 1 25>;
status = "okay";
};
CP110_LABEL(sdhci0): sdhci@780000 {
compatible = "marvell,armada-cp110-sdhci";
reg = <0x780000 0x300>;
interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "axi";
clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>;
dma-coherent;
status = "disabled";
};
CP110_LABEL(crypto): crypto@800000 {
compatible = "inside-secure,safexcel-eip197";
reg = <0x800000 0x200000>;
interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
clocks = <&CP110_LABEL(clk) 1 26>;
dma-coherent;
};
};
CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE {
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>,
<0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>;
reg-names = "ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
dma-coherent;
msi-parent = <&gic_v2m0>;
bus-range = <0 0xff>;
ranges =
/* downstream I/O */
<0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BASE(0) 0 0x10000
/* non-prefetchable memory */
0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&CP110_LABEL(clk) 1 13>;
status = "disabled";
};
CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE {
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>,
<0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>;
reg-names = "ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
dma-coherent;
msi-parent = <&gic_v2m0>;
bus-range = <0 0xff>;
ranges =
/* downstream I/O */
<0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BASE(1) 0 0x10000
/* non-prefetchable memory */
0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&CP110_LABEL(clk) 1 11>;
status = "disabled";
};
CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE {
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>,
<0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>;
reg-names = "ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
dma-coherent;
msi-parent = <&gic_v2m0>;
bus-range = <0 0xff>;
ranges =
/* downstream I/O */
<0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BASE(2) 0 0x10000
/* non-prefetchable memory */
0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&CP110_LABEL(clk) 1 12>;
status = "disabled";
};
};