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usb: dwc3: Soft reset phy on probe for host

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When there's phy initialization, we need to initiate a soft-reset
sequence. That's done through USBCMD.HCRST in the xHCI driver and its
initialization, However, the dwc3 driver may modify core configs before
the soft-reset. This may result in some connection instability. So,
ensure the phy is ready before the controller updates the GCTL.PRTCAPDIR
or other settings by issuing phy soft-reset.

Note that some host-mode configurations may not expose device registers
to initiate the controller soft-reset (via DCTL.CoreSftRst). So we reset
through GUSB3PIPECTL and GUSB2PHYCFG instead.

Cc: stable@vger.kernel.org
Fixes: e835c0a4e2 ("usb: dwc3: don't reset device side if dwc3 was configured as host-only")
Reported-by: Kenta Sato <tosainu.maple@gmail.com>
Closes: https://lore.kernel.org/linux-usb/ZPUciRLUcjDywMVS@debian.me/
Signed-off-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Tested-by: Kenta Sato <tosainu.maple@gmail.com>
Link: https://lore.kernel.org/r/70aea513215d273669152696cc02b20ddcdb6f1a.1694564261.git.Thinh.Nguyen@synopsys.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Thinh Nguyen 2023-09-13 00:52:15 +00:00 committed by Greg Kroah-Hartman
parent f74a7afc22
commit 8bea147dfd
1 changed files with 38 additions and 1 deletions
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39
drivers/usb/dwc3/core.c
View File

@ -279,9 +279,46 @@ int dwc3_core_soft_reset(struct dwc3 *dwc)
* XHCI driver will reset the host block. If dwc3 was configured for
* host-only mode or current role is host, then we can return early.
*/
if (dwc->dr_mode == USB_DR_MODE_HOST || dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
return 0;
/*
* If the dr_mode is host and the dwc->current_dr_role is not the
* corresponding DWC3_GCTL_PRTCAP_HOST, then the dwc3_core_init_mode
* isn't executed yet. Ensure the phy is ready before the controller
* updates the GCTL.PRTCAPDIR or other settings by soft-resetting
* the phy.
*
* Note: GUSB3PIPECTL[n] and GUSB2PHYCFG[n] are port settings where n
* is port index. If this is a multiport host, then we need to reset
* all active ports.
*/
if (dwc->dr_mode == USB_DR_MODE_HOST) {
u32 usb3_port;
u32 usb2_port;
usb3_port = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
usb3_port |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), usb3_port);
usb2_port = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
usb2_port |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), usb2_port);
/* Small delay for phy reset assertion */
usleep_range(1000, 2000);
usb3_port &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), usb3_port);
usb2_port &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), usb2_port);
/* Wait for clock synchronization */
msleep(50);
return 0;
}
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
reg |= DWC3_DCTL_CSFTRST;
reg &= ~DWC3_DCTL_RUN_STOP;