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sh: Overhaul spinlocks and rwlocks for SH-4A SMP.
This rips out some of the old spinlock and rwlock behaviour that the SH-2 parts were using and reworks them for LL/SC semantics on the SH-4A. This is primarily only useful for SH-X3 multi-cores, but can also be used for building CONFIG_SMP=y testing kernels on SH-4A UP. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
parent
b05d1865b4
commit
8a467a529f
@ -2,6 +2,7 @@
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* include/asm-sh/spinlock.h
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*
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* Copyright (C) 2002, 2003 Paul Mundt
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* Copyright (C) 2006, 2007 Akio Idehara
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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@ -10,17 +11,22 @@
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#ifndef __ASM_SH_SPINLOCK_H
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#define __ASM_SH_SPINLOCK_H
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#include <asm/atomic.h>
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#include <asm/spinlock_types.h>
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/*
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* The only locking implemented here uses SH-4A opcodes. For others,
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* split this out as per atomic-*.h.
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*/
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#ifndef CONFIG_CPU_SH4A
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#error "Need movli.l/movco.l for spinlocks"
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#endif
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/*
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* Your basic SMP spinlocks, allowing only a single CPU anywhere
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*/
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#define __raw_spin_is_locked(x) ((x)->lock != 0)
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#define __raw_spin_is_locked(x) ((x)->lock <= 0)
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#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
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#define __raw_spin_unlock_wait(x) \
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do { cpu_relax(); } while (__raw_spin_is_locked(x))
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do { cpu_relax(); } while ((x)->lock)
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/*
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* Simple spin lock operations. There are two variants, one clears IRQ's
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@ -30,12 +36,19 @@
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*/
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static inline void __raw_spin_lock(raw_spinlock_t *lock)
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{
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unsigned long tmp;
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unsigned long oldval;
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__asm__ __volatile__ (
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"1:\n\t"
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"tas.b @%0\n\t"
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"bf/s 1b\n\t"
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"nop\n\t"
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: "=r" (lock->lock)
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"1: \n\t"
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"movli.l @%2, %0 ! __raw_spin_lock \n\t"
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"mov %0, %1 \n\t"
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"mov #0, %0 \n\t"
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"movco.l %0, @%2 \n\t"
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"bf 1b \n\t"
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"cmp/pl %1 \n\t"
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"bf 1b \n\t"
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: "=&z" (tmp), "=&r" (oldval)
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: "r" (&lock->lock)
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: "t", "memory"
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);
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@ -43,12 +56,36 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
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static inline void __raw_spin_unlock(raw_spinlock_t *lock)
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{
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//assert_spin_locked(lock);
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unsigned long tmp;
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lock->lock = 0;
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__asm__ __volatile__ (
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"mov #1, %0 ! __raw_spin_unlock \n\t"
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"mov.l %0, @%1 \n\t"
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: "=&z" (tmp)
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: "r" (&lock->lock)
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: "t", "memory"
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);
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}
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#define __raw_spin_trylock(x) (!test_and_set_bit(0, &(x)->lock))
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static inline int __raw_spin_trylock(raw_spinlock_t *lock)
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{
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unsigned long tmp, oldval;
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__asm__ __volatile__ (
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"1: \n\t"
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"movli.l @%2, %0 ! __raw_spin_trylock \n\t"
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"mov %0, %1 \n\t"
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"mov #0, %0 \n\t"
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"movco.l %0, @%2 \n\t"
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"bf 1b \n\t"
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"synco \n\t"
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: "=&z" (tmp), "=&r" (oldval)
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: "r" (&lock->lock)
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: "t", "memory"
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);
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return oldval;
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}
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/*
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* Read-write spinlocks, allowing multiple readers but only one writer.
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@ -59,58 +96,124 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock)
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* read-locks.
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*/
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/**
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* read_can_lock - would read_trylock() succeed?
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* @lock: the rwlock in question.
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*/
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#define __raw_read_can_lock(x) ((x)->lock > 0)
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/**
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* write_can_lock - would write_trylock() succeed?
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* @lock: the rwlock in question.
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*/
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#define __raw_write_can_lock(x) ((x)->lock == RW_LOCK_BIAS)
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static inline void __raw_read_lock(raw_rwlock_t *rw)
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{
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__raw_spin_lock(&rw->lock);
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unsigned long tmp;
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atomic_inc(&rw->counter);
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__raw_spin_unlock(&rw->lock);
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__asm__ __volatile__ (
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"1: \n\t"
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"movli.l @%1, %0 ! __raw_read_lock \n\t"
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"cmp/pl %0 \n\t"
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"bf 1b \n\t"
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"add #-1, %0 \n\t"
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"movco.l %0, @%1 \n\t"
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"bf 1b \n\t"
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: "=&z" (tmp)
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: "r" (&rw->lock)
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: "t", "memory"
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);
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}
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static inline void __raw_read_unlock(raw_rwlock_t *rw)
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{
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__raw_spin_lock(&rw->lock);
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unsigned long tmp;
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atomic_dec(&rw->counter);
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__raw_spin_unlock(&rw->lock);
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__asm__ __volatile__ (
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"1: \n\t"
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"movli.l @%1, %0 ! __raw_read_unlock \n\t"
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"add #1, %0 \n\t"
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"movco.l %0, @%1 \n\t"
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"bf 1b \n\t"
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: "=&z" (tmp)
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: "r" (&rw->lock)
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: "t", "memory"
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);
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}
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static inline void __raw_write_lock(raw_rwlock_t *rw)
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{
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__raw_spin_lock(&rw->lock);
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atomic_set(&rw->counter, -1);
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unsigned long tmp;
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__asm__ __volatile__ (
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"1: \n\t"
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"movli.l @%1, %0 ! __raw_write_lock \n\t"
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"cmp/hs %2, %0 \n\t"
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"bf 1b \n\t"
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"sub %2, %0 \n\t"
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"movco.l %0, @%1 \n\t"
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"bf 1b \n\t"
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: "=&z" (tmp)
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: "r" (&rw->lock), "r" (RW_LOCK_BIAS)
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: "t", "memory"
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);
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}
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static inline void __raw_write_unlock(raw_rwlock_t *rw)
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{
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atomic_set(&rw->counter, 0);
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__raw_spin_unlock(&rw->lock);
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__asm__ __volatile__ (
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"mov.l %1, @%0 ! __raw_write_unlock \n\t"
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:
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: "r" (&rw->lock), "r" (RW_LOCK_BIAS)
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: "t", "memory"
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);
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}
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static inline int __raw_write_can_lock(raw_rwlock_t *rw)
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static inline int __raw_read_trylock(raw_rwlock_t *rw)
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{
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return (atomic_read(&rw->counter) == RW_LOCK_BIAS);
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}
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unsigned long tmp, oldval;
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static inline int __raw_read_trylock(raw_rwlock_t *lock)
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{
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atomic_t *count = (atomic_t*)lock;
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if (atomic_dec_return(count) >= 0)
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return 1;
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atomic_inc(count);
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return 0;
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__asm__ __volatile__ (
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"1: \n\t"
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"movli.l @%2, %0 ! __raw_read_trylock \n\t"
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"mov %0, %1 \n\t"
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"cmp/pl %0 \n\t"
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"bf 2f \n\t"
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"add #-1, %0 \n\t"
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"movco.l %0, @%2 \n\t"
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"bf 1b \n\t"
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"2: \n\t"
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"synco \n\t"
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: "=&z" (tmp), "=&r" (oldval)
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: "r" (&rw->lock)
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: "t", "memory"
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);
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return (oldval > 0);
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}
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static inline int __raw_write_trylock(raw_rwlock_t *rw)
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{
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if (atomic_sub_and_test(RW_LOCK_BIAS, &rw->counter))
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return 1;
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atomic_add(RW_LOCK_BIAS, &rw->counter);
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unsigned long tmp, oldval;
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return 0;
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__asm__ __volatile__ (
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"1: \n\t"
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"movli.l @%2, %0 ! __raw_write_trylock \n\t"
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"mov %0, %1 \n\t"
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"cmp/hs %3, %0 \n\t"
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"bf 2f \n\t"
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"sub %3, %0 \n\t"
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"2: \n\t"
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"movco.l %0, @%2 \n\t"
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"bf 1b \n\t"
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"synco \n\t"
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: "=&z" (tmp), "=&r" (oldval)
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: "r" (&rw->lock), "r" (RW_LOCK_BIAS)
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: "t", "memory"
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);
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return (oldval > (RW_LOCK_BIAS - 1));
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}
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#define _raw_spin_relax(lock) cpu_relax()
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@ -6,19 +6,16 @@
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#endif
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typedef struct {
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volatile unsigned long lock;
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volatile unsigned int lock;
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} raw_spinlock_t;
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#define __RAW_SPIN_LOCK_UNLOCKED { 1 }
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#include <asm/atomic.h>
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#define __RAW_SPIN_LOCK_UNLOCKED { 1 }
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typedef struct {
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raw_spinlock_t lock;
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atomic_t counter;
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volatile unsigned int lock;
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} raw_rwlock_t;
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#define RW_LOCK_BIAS 0x01000000
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#define __RAW_RW_LOCK_UNLOCKED { { 0 }, { RW_LOCK_BIAS } }
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#define __RAW_RW_LOCK_UNLOCKED { RW_LOCK_BIAS }
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#endif
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