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KVM: SVM: Enable Virtual VMLOAD VMSAVE feature
Enable the Virtual VMLOAD VMSAVE feature. This is done by setting bit 1 at position B8h in the vmcb. The processor must have nested paging enabled, be in 64-bit mode and have support for the Virtual VMLOAD VMSAVE feature for the bit to be set in the vmcb. Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
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@ -120,6 +120,7 @@ struct __attribute__ ((__packed__)) vmcb_control_area {
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#define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
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#define LBR_CTL_ENABLE_MASK BIT_ULL(0)
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#define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
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#define SVM_INTERRUPT_SHADOW_MASK 1
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@ -277,6 +277,10 @@ static int avic;
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module_param(avic, int, S_IRUGO);
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#endif
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/* enable/disable Virtual VMLOAD VMSAVE */
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static int vls = true;
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module_param(vls, int, 0444);
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/* AVIC VM ID bit masks and lock */
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static DECLARE_BITMAP(avic_vm_id_bitmap, AVIC_VM_ID_NR);
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static DEFINE_SPINLOCK(avic_vm_id_lock);
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@ -1093,6 +1097,16 @@ static __init int svm_hardware_setup(void)
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}
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}
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if (vls) {
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if (!npt_enabled ||
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!boot_cpu_has(X86_FEATURE_VIRTUAL_VMLOAD_VMSAVE) ||
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!IS_ENABLED(CONFIG_X86_64)) {
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vls = false;
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} else {
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pr_info("Virtual VMLOAD VMSAVE supported\n");
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}
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}
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return 0;
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err:
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@ -1280,6 +1294,16 @@ static void init_vmcb(struct vcpu_svm *svm)
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if (avic)
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avic_init_vmcb(svm);
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/*
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* If hardware supports Virtual VMLOAD VMSAVE then enable it
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* in VMCB and clear intercepts to avoid #VMEXIT.
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*/
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if (vls) {
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clr_intercept(svm, INTERCEPT_VMLOAD);
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clr_intercept(svm, INTERCEPT_VMSAVE);
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svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
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}
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mark_all_dirty(svm->vmcb);
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enable_gif(svm);
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