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ata: pata_pxa: dmaengine conversion
The PXA architecture was offered a slave dmaengine support. As a consequence the direct DMA registers are progressively replaced by dmaengine support. This makes the pata_pxa change, which brings this driver to almost a generic ATA 40-wires driver relying on dmaengine for transfers. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Tejun Heo <tj@kernel.org>
This commit is contained in:
Robert Jarzmik
Tejun Heo
parent
ecfb459851
commit
88622d80af
@ -24,79 +24,36 @@
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#include <linux/ata.h>
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#include <linux/libata.h>
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#include <linux/platform_device.h>
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#include <linux/dmaengine.h>
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#include <linux/dma/pxa-dma.h>
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#include <linux/gpio.h>
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#include <linux/slab.h>
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#include <linux/completion.h>
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#include <scsi/scsi_host.h>
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#include <mach/pxa2xx-regs.h>
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#include <linux/platform_data/ata-pxa.h>
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#include <mach/dma.h>
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#define DRV_NAME "pata_pxa"
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#define DRV_VERSION "0.1"
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struct pata_pxa_data {
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uint32_t dma_channel;
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struct pxa_dma_desc *dma_desc;
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dma_addr_t dma_desc_addr;
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uint32_t dma_desc_id;
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/* DMA IO physical address */
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uint32_t dma_io_addr;
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/* PXA DREQ<0:2> pin selector */
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uint32_t dma_dreq;
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/* DMA DCSR register value */
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uint32_t dma_dcsr;
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struct dma_chan *dma_chan;
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dma_cookie_t dma_cookie;
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struct completion dma_done;
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};
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/*
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* Setup the DMA descriptors. The size is transfer capped at 4k per descriptor,
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* if the transfer is longer, it is split into multiple chained descriptors.
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* DMA interrupt handler.
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*/
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static void pxa_load_dmac(struct scatterlist *sg, struct ata_queued_cmd *qc)
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static void pxa_ata_dma_irq(void *d)
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{
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struct pata_pxa_data *pd = qc->ap->private_data;
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struct pata_pxa_data *pd = d;
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enum dma_status status;
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uint32_t cpu_len, seg_len;
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dma_addr_t cpu_addr;
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cpu_addr = sg_dma_address(sg);
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cpu_len = sg_dma_len(sg);
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do {
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seg_len = (cpu_len > 0x1000) ? 0x1000 : cpu_len;
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pd->dma_desc[pd->dma_desc_id].ddadr = pd->dma_desc_addr +
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((pd->dma_desc_id + 1) * sizeof(struct pxa_dma_desc));
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pd->dma_desc[pd->dma_desc_id].dcmd = DCMD_BURST32 |
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DCMD_WIDTH2 | (DCMD_LENGTH & seg_len);
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if (qc->tf.flags & ATA_TFLAG_WRITE) {
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pd->dma_desc[pd->dma_desc_id].dsadr = cpu_addr;
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pd->dma_desc[pd->dma_desc_id].dtadr = pd->dma_io_addr;
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pd->dma_desc[pd->dma_desc_id].dcmd |= DCMD_INCSRCADDR |
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DCMD_FLOWTRG;
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} else {
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pd->dma_desc[pd->dma_desc_id].dsadr = pd->dma_io_addr;
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pd->dma_desc[pd->dma_desc_id].dtadr = cpu_addr;
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pd->dma_desc[pd->dma_desc_id].dcmd |= DCMD_INCTRGADDR |
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DCMD_FLOWSRC;
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}
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cpu_len -= seg_len;
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cpu_addr += seg_len;
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pd->dma_desc_id++;
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} while (cpu_len);
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/* Should not happen */
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if (seg_len & 0x1f)
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DALGN |= (1 << pd->dma_dreq);
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status = dmaengine_tx_status(pd->dma_chan, pd->dma_cookie, NULL);
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if (status == DMA_ERROR || status == DMA_COMPLETE)
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complete(&pd->dma_done);
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}
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/*
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@ -105,28 +62,22 @@ static void pxa_load_dmac(struct scatterlist *sg, struct ata_queued_cmd *qc)
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static void pxa_qc_prep(struct ata_queued_cmd *qc)
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{
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struct pata_pxa_data *pd = qc->ap->private_data;
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int si = 0;
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struct scatterlist *sg;
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struct dma_async_tx_descriptor *tx;
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enum dma_transfer_direction dir;
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if (!(qc->flags & ATA_QCFLAG_DMAMAP))
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return;
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pd->dma_desc_id = 0;
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DCSR(pd->dma_channel) = 0;
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DALGN &= ~(1 << pd->dma_dreq);
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for_each_sg(qc->sg, sg, qc->n_elem, si)
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pxa_load_dmac(sg, qc);
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pd->dma_desc[pd->dma_desc_id - 1].ddadr = DDADR_STOP;
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/* Fire IRQ only at the end of last block */
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pd->dma_desc[pd->dma_desc_id - 1].dcmd |= DCMD_ENDIRQEN;
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DDADR(pd->dma_channel) = pd->dma_desc_addr;
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DRCMR(pd->dma_dreq) = DRCMR_MAPVLD | pd->dma_channel;
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dir = (qc->dma_dir == DMA_TO_DEVICE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM);
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tx = dmaengine_prep_slave_sg(pd->dma_chan, qc->sg, qc->n_elem, dir,
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DMA_PREP_INTERRUPT);
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if (!tx) {
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ata_dev_err(qc->dev, "prep_slave_sg() failed\n");
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return;
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}
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tx->callback = pxa_ata_dma_irq;
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tx->callback_param = pd;
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pd->dma_cookie = dmaengine_submit(tx);
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}
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/*
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@ -145,7 +96,7 @@ static void pxa_bmdma_start(struct ata_queued_cmd *qc)
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{
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struct pata_pxa_data *pd = qc->ap->private_data;
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init_completion(&pd->dma_done);
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DCSR(pd->dma_channel) = DCSR_RUN;
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dma_async_issue_pending(pd->dma_chan);
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}
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/*
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@ -154,12 +105,14 @@ static void pxa_bmdma_start(struct ata_queued_cmd *qc)
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static void pxa_bmdma_stop(struct ata_queued_cmd *qc)
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{
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struct pata_pxa_data *pd = qc->ap->private_data;
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enum dma_status status;
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if ((DCSR(pd->dma_channel) & DCSR_RUN) &&
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wait_for_completion_timeout(&pd->dma_done, HZ))
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dev_err(qc->ap->dev, "Timeout waiting for DMA completion!");
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status = dmaengine_tx_status(pd->dma_chan, pd->dma_cookie, NULL);
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if (status != DMA_ERROR && status != DMA_COMPLETE &&
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wait_for_completion_timeout(&pd->dma_done, HZ))
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ata_dev_err(qc->dev, "Timeout waiting for DMA completion!");
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DCSR(pd->dma_channel) = 0;
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dmaengine_terminate_all(pd->dma_chan);
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}
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/*
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@ -170,8 +123,11 @@ static unsigned char pxa_bmdma_status(struct ata_port *ap)
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{
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struct pata_pxa_data *pd = ap->private_data;
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unsigned char ret = ATA_DMA_INTR;
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struct dma_tx_state state;
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enum dma_status status;
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if (pd->dma_dcsr & DCSR_BUSERR)
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status = dmaengine_tx_status(pd->dma_chan, pd->dma_cookie, &state);
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if (status != DMA_COMPLETE)
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ret |= ATA_DMA_ERR;
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return ret;
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@ -213,21 +169,6 @@ static struct ata_port_operations pxa_ata_port_ops = {
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.qc_prep = pxa_qc_prep,
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};
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/*
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* DMA interrupt handler.
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*/
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static void pxa_ata_dma_irq(int dma, void *port)
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{
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struct ata_port *ap = port;
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struct pata_pxa_data *pd = ap->private_data;
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pd->dma_dcsr = DCSR(dma);
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DCSR(dma) = pd->dma_dcsr;
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if (pd->dma_dcsr & DCSR_STOPSTATE)
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complete(&pd->dma_done);
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}
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static int pxa_ata_probe(struct platform_device *pdev)
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{
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struct ata_host *host;
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@ -238,6 +179,9 @@ static int pxa_ata_probe(struct platform_device *pdev)
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struct resource *dma_res;
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struct resource *irq_res;
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struct pata_pxa_pdata *pdata = dev_get_platdata(&pdev->dev);
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struct dma_slave_config config;
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dma_cap_mask_t mask;
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struct pxad_param param;
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int ret = 0;
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/*
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@ -333,29 +277,32 @@ static int pxa_ata_probe(struct platform_device *pdev)
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return -ENOMEM;
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ap->private_data = data;
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data->dma_dreq = pdata->dma_dreq;
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data->dma_io_addr = dma_res->start;
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/*
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* Allocate space for the DMA descriptors
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*/
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data->dma_desc = dmam_alloc_coherent(&pdev->dev, PAGE_SIZE,
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&data->dma_desc_addr, GFP_KERNEL);
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if (!data->dma_desc)
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return -EINVAL;
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dma_cap_zero(mask);
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dma_cap_set(DMA_SLAVE, mask);
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param.prio = PXAD_PRIO_LOWEST;
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param.drcmr = pdata->dma_dreq;
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memset(&config, 0, sizeof(config));
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config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
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config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
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config.src_addr = dma_res->start;
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config.dst_addr = dma_res->start;
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config.src_maxburst = 32;
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config.dst_maxburst = 32;
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/*
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* Request the DMA channel
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*/
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data->dma_channel = pxa_request_dma(DRV_NAME, DMA_PRIO_LOW,
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pxa_ata_dma_irq, ap);
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if (data->dma_channel < 0)
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data->dma_chan =
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dma_request_slave_channel_compat(mask, pxad_filter_fn,
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¶m, &pdev->dev, "data");
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if (!data->dma_chan)
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return -EBUSY;
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/*
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* Stop and clear the DMA channel
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*/
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DCSR(data->dma_channel) = 0;
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ret = dmaengine_slave_config(data->dma_chan, &config);
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if (ret < 0) {
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dev_err(&pdev->dev, "dma configuration failed: %d\n", ret);
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return ret;
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}
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/*
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* Activate the ATA host
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@ -363,7 +310,7 @@ static int pxa_ata_probe(struct platform_device *pdev)
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ret = ata_host_activate(host, irq_res->start, ata_sff_interrupt,
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pdata->irq_flags, &pxa_ata_sht);
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if (ret)
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pxa_free_dma(data->dma_channel);
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dma_release_channel(data->dma_chan);
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return ret;
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}
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@ -373,7 +320,7 @@ static int pxa_ata_remove(struct platform_device *pdev)
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struct ata_host *host = platform_get_drvdata(pdev);
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struct pata_pxa_data *data = host->ports[0]->private_data;
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pxa_free_dma(data->dma_channel);
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dma_release_channel(data->dma_chan);
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ata_host_detach(host);
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