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phy: rockchip-inno-usb2: correct 480MHz output clock stable time
We found that the system crashed due to 480MHz output clock of USB2 PHY was unstable after clock had been enabled by gpu module. Theoretically, 1 millisecond is a critical value for 480MHz output clock stable time, so we try to change the delay time to 1.2 millisecond to avoid this issue. And the commit ed907fb1d7c3 ("phy: rockchip-inno-usb2: correct clk_ops callback") used prepare callbacks instead of enable callbacks to support gate a clk if the operation may sleep. So we can switch from delay to sleep functions. Also fix a spelling error from "waitting" to "waiting". Signed-off-by: William Wu <wulf@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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@ -266,8 +266,8 @@ static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
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if (ret)
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return ret;
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/* waitting for the clk become stable */
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mdelay(1);
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/* waiting for the clk become stable */
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usleep_range(1200, 1300);
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}
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return 0;
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