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MIPS: Octeon: Fix broken interrupt controller code.
Since 3.6.0-rc1, We are getting many messages like: WARNING: at kernel/irq/irqdomain.c:444 irq_domain_associate_many+0x23c/0x260() Modules linked in: Call Trace: [<ffffffff814cb698>] dump_stack+0x8/0x34 [<ffffffff81133d00>] warn_slowpath_common+0x78/0xa8 [<ffffffff81187e44>] irq_domain_associate_many+0x23c/0x260 [<ffffffff81187f38>] irq_create_mapping+0xd0/0x220 [<ffffffff81188104>] irq_create_of_mapping+0x7c/0x158 [<ffffffff813e5f08>] irq_of_parse_and_map+0x28/0x40 . . . Both the CIU and GPIO interrupt domains were somewhat screwed up. For the CIU domain, we need to call irq_domain_associate() for each of the preassigned irq numbers. For the GPIO domain, we were applying the register bit offset in octeon_irq_gpio_xlat, but it should be done in octeon_irq_gpio_map instead. Also: Reserve all 8 'core' irqs for the 'core' irq_chip so that they don't get used by the other domains. Remove unused OCTEON_IRQ_* symbols. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4190/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
David Daney
Ralf Baechle
parent
d9875690d9
commit
87161ccdc6
@ -61,6 +61,12 @@ static void octeon_irq_set_ciu_mapping(int irq, int line, int bit,
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octeon_irq_ciu_to_irq[line][bit] = irq;
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}
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static void octeon_irq_force_ciu_mapping(struct irq_domain *domain,
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int irq, int line, int bit)
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{
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irq_domain_associate(domain, irq, line << 6 | bit);
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}
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static int octeon_coreid_for_cpu(int cpu)
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{
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#ifdef CONFIG_SMP
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@ -183,19 +189,9 @@ static void __init octeon_irq_init_core(void)
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mutex_init(&cd->core_irq_mutex);
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irq = OCTEON_IRQ_SW0 + i;
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switch (irq) {
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case OCTEON_IRQ_TIMER:
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case OCTEON_IRQ_SW0:
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case OCTEON_IRQ_SW1:
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case OCTEON_IRQ_5:
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case OCTEON_IRQ_PERF:
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irq_set_chip_data(irq, cd);
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irq_set_chip_and_handler(irq, &octeon_irq_chip_core,
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handle_percpu_irq);
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break;
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default:
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break;
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}
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irq_set_chip_data(irq, cd);
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irq_set_chip_and_handler(irq, &octeon_irq_chip_core,
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handle_percpu_irq);
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}
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}
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@ -890,7 +886,6 @@ static int octeon_irq_gpio_xlat(struct irq_domain *d,
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unsigned int type;
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unsigned int pin;
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unsigned int trigger;
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struct octeon_irq_gpio_domain_data *gpiod;
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if (d->of_node != node)
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return -EINVAL;
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@ -925,8 +920,7 @@ static int octeon_irq_gpio_xlat(struct irq_domain *d,
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break;
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}
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*out_type = type;
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gpiod = d->host_data;
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*out_hwirq = gpiod->base_hwirq + pin;
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*out_hwirq = pin;
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return 0;
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}
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@ -996,19 +990,21 @@ static int octeon_irq_ciu_map(struct irq_domain *d,
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static int octeon_irq_gpio_map(struct irq_domain *d,
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unsigned int virq, irq_hw_number_t hw)
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{
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unsigned int line = hw >> 6;
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unsigned int bit = hw & 63;
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struct octeon_irq_gpio_domain_data *gpiod = d->host_data;
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unsigned int line, bit;
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if (!octeon_irq_virq_in_range(virq))
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return -EINVAL;
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hw += gpiod->base_hwirq;
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line = hw >> 6;
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bit = hw & 63;
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if (line > 1 || octeon_irq_ciu_to_irq[line][bit] != 0)
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return -EINVAL;
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octeon_irq_set_ciu_mapping(virq, line, bit,
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octeon_irq_gpio_chip,
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octeon_irq_handle_gpio);
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return 0;
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}
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@ -1149,6 +1145,7 @@ static void __init octeon_irq_init_ciu(void)
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struct irq_chip *chip_wd;
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struct device_node *gpio_node;
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struct device_node *ciu_node;
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struct irq_domain *ciu_domain = NULL;
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octeon_irq_init_ciu_percpu();
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octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu;
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@ -1177,31 +1174,6 @@ static void __init octeon_irq_init_ciu(void)
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/* Mips internal */
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octeon_irq_init_core();
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/* CIU_0 */
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for (i = 0; i < 16; i++)
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octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WORKQ0, 0, i + 0, chip, handle_level_irq);
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octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq);
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octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq);
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for (i = 0; i < 4; i++)
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octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_INT0, 0, i + 36, chip, handle_level_irq);
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for (i = 0; i < 4; i++)
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octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_MSI0, 0, i + 40, chip, handle_level_irq);
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octeon_irq_set_ciu_mapping(OCTEON_IRQ_RML, 0, 46, chip, handle_level_irq);
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for (i = 0; i < 4; i++)
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octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_TIMER0, 0, i + 52, chip, handle_edge_irq);
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octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB0, 0, 56, chip, handle_level_irq);
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octeon_irq_set_ciu_mapping(OCTEON_IRQ_BOOTDMA, 0, 63, chip, handle_level_irq);
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/* CIU_1 */
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for (i = 0; i < 16; i++)
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octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, chip_wd, handle_level_irq);
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octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB1, 1, 17, chip, handle_level_irq);
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gpio_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-gpio");
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if (gpio_node) {
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struct octeon_irq_gpio_domain_data *gpiod;
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@ -1219,10 +1191,35 @@ static void __init octeon_irq_init_ciu(void)
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ciu_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-ciu");
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if (ciu_node) {
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irq_domain_add_tree(ciu_node, &octeon_irq_domain_ciu_ops, NULL);
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ciu_domain = irq_domain_add_tree(ciu_node, &octeon_irq_domain_ciu_ops, NULL);
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of_node_put(ciu_node);
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} else
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pr_warn("Cannot find device node for cavium,octeon-3860-ciu.\n");
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panic("Cannot find device node for cavium,octeon-3860-ciu.");
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/* CIU_0 */
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for (i = 0; i < 16; i++)
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octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_WORKQ0, 0, i + 0);
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octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq);
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octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq);
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for (i = 0; i < 4; i++)
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octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_PCI_INT0, 0, i + 36);
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for (i = 0; i < 4; i++)
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octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_PCI_MSI0, 0, i + 40);
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octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_RML, 0, 46);
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for (i = 0; i < 4; i++)
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octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_TIMER0, 0, i + 52);
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octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB0, 0, 56);
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octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_BOOTDMA, 0, 63);
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/* CIU_1 */
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for (i = 0; i < 16; i++)
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octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, chip_wd, handle_level_irq);
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octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB1, 1, 17);
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/* Enable the CIU lines */
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set_c0_status(STATUSF_IP3 | STATUSF_IP2);
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@ -21,14 +21,10 @@ enum octeon_irq {
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OCTEON_IRQ_TIMER,
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/* sources in CIU_INTX_EN0 */
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OCTEON_IRQ_WORKQ0,
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OCTEON_IRQ_GPIO0 = OCTEON_IRQ_WORKQ0 + 16,
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OCTEON_IRQ_WDOG0 = OCTEON_IRQ_GPIO0 + 16,
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OCTEON_IRQ_WDOG0 = OCTEON_IRQ_WORKQ0 + 16,
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OCTEON_IRQ_WDOG15 = OCTEON_IRQ_WDOG0 + 15,
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OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 16,
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OCTEON_IRQ_MBOX1,
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OCTEON_IRQ_UART0,
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OCTEON_IRQ_UART1,
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OCTEON_IRQ_UART2,
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OCTEON_IRQ_PCI_INT0,
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OCTEON_IRQ_PCI_INT1,
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OCTEON_IRQ_PCI_INT2,
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@ -38,8 +34,6 @@ enum octeon_irq {
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OCTEON_IRQ_PCI_MSI2,
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OCTEON_IRQ_PCI_MSI3,
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OCTEON_IRQ_TWSI,
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OCTEON_IRQ_TWSI2,
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OCTEON_IRQ_RML,
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OCTEON_IRQ_TIMER0,
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OCTEON_IRQ_TIMER1,
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@ -47,8 +41,6 @@ enum octeon_irq {
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OCTEON_IRQ_TIMER3,
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OCTEON_IRQ_USB0,
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OCTEON_IRQ_USB1,
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OCTEON_IRQ_MII0,
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OCTEON_IRQ_MII1,
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OCTEON_IRQ_BOOTDMA,
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#ifndef CONFIG_PCI_MSI
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OCTEON_IRQ_LAST = 127
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