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x86/boot/compressed/64: Check SEV encryption in 64-bit boot-path
Check whether the hypervisor reported the correct C-bit when running as an SEV guest. Using a wrong C-bit position could be used to leak sensitive data from the guest to the hypervisor. The check function is in a separate file: arch/x86/kernel/sev_verify_cbit.S so that it can be re-used in the running kernel image. [ bp: Massage. ] Signed-off-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com> Link: https://lkml.kernel.org/r/20201028164659.27002-4-joro@8bytes.org
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@ -164,6 +164,7 @@ void initialize_identity_maps(void *rmode)
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add_identity_map(cmdline, cmdline + COMMAND_LINE_SIZE);
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/* Load the new page-table. */
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sev_verify_cbit(top_level_pgt);
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write_cr3(top_level_pgt);
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}
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@ -68,6 +68,9 @@ SYM_FUNC_START(get_sev_encryption_bit)
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SYM_FUNC_END(get_sev_encryption_bit)
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.code64
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#include "../../kernel/sev_verify_cbit.S"
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SYM_FUNC_START(set_sev_encryption_mask)
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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push %rbp
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@ -111,4 +114,5 @@ SYM_FUNC_END(set_sev_encryption_mask)
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.balign 8
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SYM_DATA(sme_me_mask, .quad 0)
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SYM_DATA(sev_status, .quad 0)
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SYM_DATA(sev_check_data, .quad 0)
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#endif
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@ -159,4 +159,6 @@ void boot_page_fault(void);
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void boot_stage1_vc(void);
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void boot_stage2_vc(void);
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unsigned long sev_verify_cbit(unsigned long cr3);
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#endif /* BOOT_COMPRESSED_MISC_H */
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89
arch/x86/kernel/sev_verify_cbit.S
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89
arch/x86/kernel/sev_verify_cbit.S
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@ -0,0 +1,89 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* sev_verify_cbit.S - Code for verification of the C-bit position reported
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* by the Hypervisor when running with SEV enabled.
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*
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* Copyright (c) 2020 Joerg Roedel (jroedel@suse.de)
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*
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* sev_verify_cbit() is called before switching to a new long-mode page-table
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* at boot.
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*
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* Verify that the C-bit position is correct by writing a random value to
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* an encrypted memory location while on the current page-table. Then it
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* switches to the new page-table to verify the memory content is still the
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* same. After that it switches back to the current page-table and when the
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* check succeeded it returns. If the check failed the code invalidates the
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* stack pointer and goes into a hlt loop. The stack-pointer is invalidated to
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* make sure no interrupt or exception can get the CPU out of the hlt loop.
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*
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* New page-table pointer is expected in %rdi (first parameter)
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*
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*/
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SYM_FUNC_START(sev_verify_cbit)
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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/* First check if a C-bit was detected */
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movq sme_me_mask(%rip), %rsi
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testq %rsi, %rsi
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jz 3f
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/* sme_me_mask != 0 could mean SME or SEV - Check also for SEV */
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movq sev_status(%rip), %rsi
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testq %rsi, %rsi
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jz 3f
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/* Save CR4 in %rsi */
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movq %cr4, %rsi
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/* Disable Global Pages */
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movq %rsi, %rdx
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andq $(~X86_CR4_PGE), %rdx
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movq %rdx, %cr4
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/*
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* Verified that running under SEV - now get a random value using
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* RDRAND. This instruction is mandatory when running as an SEV guest.
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*
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* Don't bail out of the loop if RDRAND returns errors. It is better to
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* prevent forward progress than to work with a non-random value here.
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*/
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1: rdrand %rdx
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jnc 1b
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/* Store value to memory and keep it in %rdx */
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movq %rdx, sev_check_data(%rip)
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/* Backup current %cr3 value to restore it later */
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movq %cr3, %rcx
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/* Switch to new %cr3 - This might unmap the stack */
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movq %rdi, %cr3
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/*
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* Compare value in %rdx with memory location. If C-bit is incorrect
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* this would read the encrypted data and make the check fail.
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*/
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cmpq %rdx, sev_check_data(%rip)
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/* Restore old %cr3 */
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movq %rcx, %cr3
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/* Restore previous CR4 */
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movq %rsi, %cr4
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/* Check CMPQ result */
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je 3f
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/*
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* The check failed, prevent any forward progress to prevent ROP
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* attacks, invalidate the stack and go into a hlt loop.
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*/
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xorq %rsp, %rsp
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subq $0x1000, %rsp
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2: hlt
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jmp 2b
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3:
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#endif
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/* Return page-table pointer */
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movq %rdi, %rax
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ret
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SYM_FUNC_END(sev_verify_cbit)
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