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drm/i915/bxt: add GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ workaround

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Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ben Widawsky 2015-03-11 10:49:32 +02:00 committed by Daniel Vetter
parent 32608ca255
commit 868434c51e
2 changed files with 4 additions and 1 deletions
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1
drivers/gpu/drm/i915/i915_reg.h
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@ -6104,6 +6104,7 @@ enum skl_disp_power_wells {
#define GEN8_UCGCTL6 0x9430 #define GEN8_UCGCTL6 0x9430
#define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1<<24) #define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1<<24)
#define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14) #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14)
#define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28)
#define GEN6_GFXPAUSE 0xA000 #define GEN6_GFXPAUSE 0xA000
#define GEN6_RPNSWREQ 0xA008 #define GEN6_RPNSWREQ 0xA008

4
drivers/gpu/drm/i915/intel_pm.c
View File

@ -103,10 +103,12 @@ static void bxt_init_clock_gating(struct drm_device *dev)
/* /*
* FIXME: * FIXME:
* GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only. * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
* GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
*/ */
/* WaDisableSDEUnitClockGating:bxt */ /* WaDisableSDEUnitClockGating:bxt */
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
GEN8_SDEUNIT_CLOCK_GATE_DISABLE); GEN8_SDEUNIT_CLOCK_GATE_DISABLE |
GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
} }