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supports eg20t ptp clock
Supports EG20T ptp clock in the driver Changes e-mail address. Adds number. Signed-off-by: Takahiro Shimizu <tshimizu818@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Takahiro Shimizu
David S. Miller
parent
74dd1521d0
commit
863d08ece9
@ -72,4 +72,17 @@ config DP83640_PHY
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In order for this to work, your MAC driver must also
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implement the skb_tx_timetamp() function.
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config PTP_1588_CLOCK_PCH
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tristate "Intel PCH EG20T as PTP clock"
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depends on PTP_1588_CLOCK
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depends on PCH_GBE
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help
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This driver adds support for using the PCH EG20T as a PTP
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clock. This clock is only useful if your PTP programs are
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getting hardware time stamps on the PTP Ethernet packets
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using the SO_TIMESTAMPING API.
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To compile this driver as a module, choose M here: the module
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will be called ptp_pch.
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endmenu
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@ -5,3 +5,4 @@
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ptp-y := ptp_clock.o ptp_chardev.o ptp_sysfs.o
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obj-$(CONFIG_PTP_1588_CLOCK) += ptp.o
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obj-$(CONFIG_PTP_1588_CLOCK_IXP46X) += ptp_ixp46x.o
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obj-$(CONFIG_PTP_1588_CLOCK_PCH) += ptp_pch.o
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730
drivers/ptp/ptp_pch.c
Normal file
730
drivers/ptp/ptp_pch.c
Normal file
@ -0,0 +1,730 @@
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/*
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* PTP 1588 clock using the EG20T PCH
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*
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* Copyright (C) 2010 OMICRON electronics GmbH
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* Copyright (C) 2011-2012 LAPIS SEMICONDUCTOR Co., LTD.
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*
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* This code was derived from the IXP46X driver.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/ptp_clock_kernel.h>
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#define STATION_ADDR_LEN 20
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#define PCI_DEVICE_ID_PCH_1588 0x8819
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#define IO_MEM_BAR 1
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#define DEFAULT_ADDEND 0xA0000000
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#define TICKS_NS_SHIFT 5
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#define N_EXT_TS 2
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enum pch_status {
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PCH_SUCCESS,
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PCH_INVALIDPARAM,
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PCH_NOTIMESTAMP,
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PCH_INTERRUPTMODEINUSE,
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PCH_FAILED,
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PCH_UNSUPPORTED,
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};
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/**
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* struct pch_ts_regs - IEEE 1588 registers
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*/
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struct pch_ts_regs {
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u32 control;
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u32 event;
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u32 addend;
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u32 accum;
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u32 test;
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u32 ts_compare;
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u32 rsystime_lo;
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u32 rsystime_hi;
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u32 systime_lo;
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u32 systime_hi;
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u32 trgt_lo;
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u32 trgt_hi;
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u32 asms_lo;
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u32 asms_hi;
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u32 amms_lo;
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u32 amms_hi;
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u32 ch_control;
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u32 ch_event;
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u32 tx_snap_lo;
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u32 tx_snap_hi;
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u32 rx_snap_lo;
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u32 rx_snap_hi;
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u32 src_uuid_lo;
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u32 src_uuid_hi;
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u32 can_status;
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u32 can_snap_lo;
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u32 can_snap_hi;
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u32 ts_sel;
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u32 ts_st[6];
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u32 reserve1[14];
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u32 stl_max_set_en;
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u32 stl_max_set;
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u32 reserve2[13];
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u32 srst;
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};
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#define PCH_TSC_RESET (1 << 0)
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#define PCH_TSC_TTM_MASK (1 << 1)
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#define PCH_TSC_ASMS_MASK (1 << 2)
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#define PCH_TSC_AMMS_MASK (1 << 3)
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#define PCH_TSC_PPSM_MASK (1 << 4)
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#define PCH_TSE_TTIPEND (1 << 1)
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#define PCH_TSE_SNS (1 << 2)
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#define PCH_TSE_SNM (1 << 3)
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#define PCH_TSE_PPS (1 << 4)
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#define PCH_CC_MM (1 << 0)
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#define PCH_CC_TA (1 << 1)
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#define PCH_CC_MODE_SHIFT 16
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#define PCH_CC_MODE_MASK 0x001F0000
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#define PCH_CC_VERSION (1 << 31)
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#define PCH_CE_TXS (1 << 0)
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#define PCH_CE_RXS (1 << 1)
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#define PCH_CE_OVR (1 << 0)
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#define PCH_CE_VAL (1 << 1)
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#define PCH_ECS_ETH (1 << 0)
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#define PCH_ECS_CAN (1 << 1)
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#define PCH_STATION_BYTES 6
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#define PCH_IEEE1588_ETH (1 << 0)
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#define PCH_IEEE1588_CAN (1 << 1)
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/**
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* struct pch_dev - Driver private data
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*/
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struct pch_dev {
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struct pch_ts_regs *regs;
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struct ptp_clock *ptp_clock;
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struct ptp_clock_info caps;
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int exts0_enabled;
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int exts1_enabled;
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u32 mem_base;
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u32 mem_size;
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u32 irq;
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struct pci_dev *pdev;
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spinlock_t register_lock;
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};
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/**
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* struct pch_params - 1588 module parameter
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*/
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struct pch_params {
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u8 station[STATION_ADDR_LEN];
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};
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/* structure to hold the module parameters */
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static struct pch_params pch_param = {
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"00:00:00:00:00:00"
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};
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/*
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* Register access functions
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*/
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static inline void pch_eth_enable_set(struct pch_dev *chip)
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{
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u32 val;
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/* SET the eth_enable bit */
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val = ioread32(&chip->regs->ts_sel) | (PCH_ECS_ETH);
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iowrite32(val, (&chip->regs->ts_sel));
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}
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static u64 pch_systime_read(struct pch_ts_regs *regs)
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{
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u64 ns;
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u32 lo, hi;
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lo = ioread32(®s->systime_lo);
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hi = ioread32(®s->systime_hi);
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ns = ((u64) hi) << 32;
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ns |= lo;
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ns <<= TICKS_NS_SHIFT;
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return ns;
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}
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static void pch_systime_write(struct pch_ts_regs *regs, u64 ns)
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{
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u32 hi, lo;
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ns >>= TICKS_NS_SHIFT;
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hi = ns >> 32;
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lo = ns & 0xffffffff;
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iowrite32(lo, ®s->systime_lo);
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iowrite32(hi, ®s->systime_hi);
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}
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static inline void pch_block_reset(struct pch_dev *chip)
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{
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u32 val;
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/* Reset Hardware Assist block */
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val = ioread32(&chip->regs->control) | PCH_TSC_RESET;
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iowrite32(val, (&chip->regs->control));
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val = val & ~PCH_TSC_RESET;
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iowrite32(val, (&chip->regs->control));
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}
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u32 pch_ch_control_read(struct pci_dev *pdev)
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{
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struct pch_dev *chip = pci_get_drvdata(pdev);
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u32 val;
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val = ioread32(&chip->regs->ch_control);
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return val;
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}
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EXPORT_SYMBOL(pch_ch_control_read);
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void pch_ch_control_write(struct pci_dev *pdev, u32 val)
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{
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struct pch_dev *chip = pci_get_drvdata(pdev);
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iowrite32(val, (&chip->regs->ch_control));
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}
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EXPORT_SYMBOL(pch_ch_control_write);
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u32 pch_ch_event_read(struct pci_dev *pdev)
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{
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struct pch_dev *chip = pci_get_drvdata(pdev);
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u32 val;
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val = ioread32(&chip->regs->ch_event);
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return val;
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}
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EXPORT_SYMBOL(pch_ch_event_read);
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void pch_ch_event_write(struct pci_dev *pdev, u32 val)
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{
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struct pch_dev *chip = pci_get_drvdata(pdev);
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iowrite32(val, (&chip->regs->ch_event));
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}
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EXPORT_SYMBOL(pch_ch_event_write);
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u32 pch_src_uuid_lo_read(struct pci_dev *pdev)
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{
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struct pch_dev *chip = pci_get_drvdata(pdev);
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u32 val;
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val = ioread32(&chip->regs->src_uuid_lo);
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return val;
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}
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EXPORT_SYMBOL(pch_src_uuid_lo_read);
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u32 pch_src_uuid_hi_read(struct pci_dev *pdev)
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{
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struct pch_dev *chip = pci_get_drvdata(pdev);
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u32 val;
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val = ioread32(&chip->regs->src_uuid_hi);
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return val;
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}
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EXPORT_SYMBOL(pch_src_uuid_hi_read);
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u64 pch_rx_snap_read(struct pci_dev *pdev)
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{
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struct pch_dev *chip = pci_get_drvdata(pdev);
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u64 ns;
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u32 lo, hi;
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lo = ioread32(&chip->regs->rx_snap_lo);
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hi = ioread32(&chip->regs->rx_snap_hi);
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ns = ((u64) hi) << 32;
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ns |= lo;
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return ns;
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}
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EXPORT_SYMBOL(pch_rx_snap_read);
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u64 pch_tx_snap_read(struct pci_dev *pdev)
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{
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struct pch_dev *chip = pci_get_drvdata(pdev);
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u64 ns;
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u32 lo, hi;
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lo = ioread32(&chip->regs->tx_snap_lo);
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hi = ioread32(&chip->regs->tx_snap_hi);
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ns = ((u64) hi) << 32;
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ns |= lo;
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return ns;
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}
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EXPORT_SYMBOL(pch_tx_snap_read);
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/* This function enables all 64 bits in system time registers [high & low].
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This is a work-around for non continuous value in the SystemTime Register*/
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static void pch_set_system_time_count(struct pch_dev *chip)
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{
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iowrite32(0x01, &chip->regs->stl_max_set_en);
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iowrite32(0xFFFFFFFF, &chip->regs->stl_max_set);
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iowrite32(0x00, &chip->regs->stl_max_set_en);
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}
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static void pch_reset(struct pch_dev *chip)
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{
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/* Reset Hardware Assist */
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pch_block_reset(chip);
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/* enable all 32 bits in system time registers */
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pch_set_system_time_count(chip);
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}
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/**
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* pch_set_station_address() - This API sets the station address used by
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* IEEE 1588 hardware when looking at PTP
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* traffic on the ethernet interface
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* @addr: dress which contain the column separated address to be used.
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*/
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static int pch_set_station_address(u8 *addr, struct pci_dev *pdev)
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{
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s32 i;
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struct pch_dev *chip = pci_get_drvdata(pdev);
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/* Verify the parameter */
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if ((chip->regs == 0) || addr == (u8 *)NULL) {
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dev_err(&pdev->dev,
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"invalid params returning PCH_INVALIDPARAM\n");
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return PCH_INVALIDPARAM;
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}
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/* For all station address bytes */
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for (i = 0; i < PCH_STATION_BYTES; i++) {
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u32 val;
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s32 tmp;
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tmp = hex_to_bin(addr[i * 3]);
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if (tmp < 0) {
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dev_err(&pdev->dev,
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"invalid params returning PCH_INVALIDPARAM\n");
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return PCH_INVALIDPARAM;
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}
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val = tmp * 16;
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tmp = hex_to_bin(addr[(i * 3) + 1]);
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if (tmp < 0) {
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dev_err(&pdev->dev,
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"invalid params returning PCH_INVALIDPARAM\n");
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return PCH_INVALIDPARAM;
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}
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val += tmp;
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/* Expects ':' separated addresses */
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if ((i < 5) && (addr[(i * 3) + 2] != ':')) {
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dev_err(&pdev->dev,
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"invalid params returning PCH_INVALIDPARAM\n");
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return PCH_INVALIDPARAM;
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}
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/* Ideally we should set the address only after validating
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entire string */
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dev_dbg(&pdev->dev, "invoking pch_station_set\n");
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iowrite32(val, &chip->regs->ts_st[i]);
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}
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return 0;
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}
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/*
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* Interrupt service routine
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*/
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static irqreturn_t isr(int irq, void *priv)
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{
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struct pch_dev *pch_dev = priv;
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struct pch_ts_regs *regs = pch_dev->regs;
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struct ptp_clock_event event;
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u32 ack = 0, lo, hi, val;
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val = ioread32(®s->event);
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if (val & PCH_TSE_SNS) {
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ack |= PCH_TSE_SNS;
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if (pch_dev->exts0_enabled) {
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hi = ioread32(®s->asms_hi);
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lo = ioread32(®s->asms_lo);
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event.type = PTP_CLOCK_EXTTS;
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event.index = 0;
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event.timestamp = ((u64) hi) << 32;
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event.timestamp |= lo;
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event.timestamp <<= TICKS_NS_SHIFT;
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ptp_clock_event(pch_dev->ptp_clock, &event);
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}
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}
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if (val & PCH_TSE_SNM) {
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ack |= PCH_TSE_SNM;
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if (pch_dev->exts1_enabled) {
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hi = ioread32(®s->amms_hi);
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lo = ioread32(®s->amms_lo);
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event.type = PTP_CLOCK_EXTTS;
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event.index = 1;
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event.timestamp = ((u64) hi) << 32;
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event.timestamp |= lo;
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event.timestamp <<= TICKS_NS_SHIFT;
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ptp_clock_event(pch_dev->ptp_clock, &event);
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}
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}
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if (val & PCH_TSE_TTIPEND)
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ack |= PCH_TSE_TTIPEND; /* this bit seems to be always set */
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if (ack) {
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iowrite32(ack, ®s->event);
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return IRQ_HANDLED;
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} else
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return IRQ_NONE;
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}
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/*
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* PTP clock operations
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*/
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static int ptp_pch_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
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{
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u64 adj;
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u32 diff, addend;
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int neg_adj = 0;
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struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
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struct pch_ts_regs *regs = pch_dev->regs;
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if (ppb < 0) {
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neg_adj = 1;
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ppb = -ppb;
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}
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addend = DEFAULT_ADDEND;
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adj = addend;
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adj *= ppb;
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diff = div_u64(adj, 1000000000ULL);
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addend = neg_adj ? addend - diff : addend + diff;
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iowrite32(addend, ®s->addend);
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return 0;
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}
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static int ptp_pch_adjtime(struct ptp_clock_info *ptp, s64 delta)
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{
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s64 now;
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unsigned long flags;
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struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
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struct pch_ts_regs *regs = pch_dev->regs;
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spin_lock_irqsave(&pch_dev->register_lock, flags);
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now = pch_systime_read(regs);
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now += delta;
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pch_systime_write(regs, now);
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spin_unlock_irqrestore(&pch_dev->register_lock, flags);
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return 0;
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}
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|
||||
static int ptp_pch_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
|
||||
{
|
||||
u64 ns;
|
||||
u32 remainder;
|
||||
unsigned long flags;
|
||||
struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
|
||||
struct pch_ts_regs *regs = pch_dev->regs;
|
||||
|
||||
spin_lock_irqsave(&pch_dev->register_lock, flags);
|
||||
ns = pch_systime_read(regs);
|
||||
spin_unlock_irqrestore(&pch_dev->register_lock, flags);
|
||||
|
||||
ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
|
||||
ts->tv_nsec = remainder;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ptp_pch_settime(struct ptp_clock_info *ptp,
|
||||
const struct timespec *ts)
|
||||
{
|
||||
u64 ns;
|
||||
unsigned long flags;
|
||||
struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
|
||||
struct pch_ts_regs *regs = pch_dev->regs;
|
||||
|
||||
ns = ts->tv_sec * 1000000000ULL;
|
||||
ns += ts->tv_nsec;
|
||||
|
||||
spin_lock_irqsave(&pch_dev->register_lock, flags);
|
||||
pch_systime_write(regs, ns);
|
||||
spin_unlock_irqrestore(&pch_dev->register_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ptp_pch_enable(struct ptp_clock_info *ptp,
|
||||
struct ptp_clock_request *rq, int on)
|
||||
{
|
||||
struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
|
||||
|
||||
switch (rq->type) {
|
||||
case PTP_CLK_REQ_EXTTS:
|
||||
switch (rq->extts.index) {
|
||||
case 0:
|
||||
pch_dev->exts0_enabled = on ? 1 : 0;
|
||||
break;
|
||||
case 1:
|
||||
pch_dev->exts1_enabled = on ? 1 : 0;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
return 0;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
static struct ptp_clock_info ptp_pch_caps = {
|
||||
.owner = THIS_MODULE,
|
||||
.name = "PCH timer",
|
||||
.max_adj = 50000000,
|
||||
.n_ext_ts = N_EXT_TS,
|
||||
.pps = 0,
|
||||
.adjfreq = ptp_pch_adjfreq,
|
||||
.adjtime = ptp_pch_adjtime,
|
||||
.gettime = ptp_pch_gettime,
|
||||
.settime = ptp_pch_settime,
|
||||
.enable = ptp_pch_enable,
|
||||
};
|
||||
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static s32 pch_suspend(struct pci_dev *pdev, pm_message_t state)
|
||||
{
|
||||
pci_disable_device(pdev);
|
||||
pci_enable_wake(pdev, PCI_D3hot, 0);
|
||||
|
||||
if (pci_save_state(pdev) != 0) {
|
||||
dev_err(&pdev->dev, "could not save PCI config state\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
pci_set_power_state(pdev, pci_choose_state(pdev, state));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static s32 pch_resume(struct pci_dev *pdev)
|
||||
{
|
||||
s32 ret;
|
||||
|
||||
pci_set_power_state(pdev, PCI_D0);
|
||||
pci_restore_state(pdev);
|
||||
ret = pci_enable_device(pdev);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "pci_enable_device failed\n");
|
||||
return ret;
|
||||
}
|
||||
pci_enable_wake(pdev, PCI_D3hot, 0);
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
#define pch_suspend NULL
|
||||
#define pch_resume NULL
|
||||
#endif
|
||||
|
||||
static void __devexit pch_remove(struct pci_dev *pdev)
|
||||
{
|
||||
struct pch_dev *chip = pci_get_drvdata(pdev);
|
||||
|
||||
ptp_clock_unregister(chip->ptp_clock);
|
||||
/* free the interrupt */
|
||||
if (pdev->irq != 0)
|
||||
free_irq(pdev->irq, chip);
|
||||
|
||||
/* unmap the virtual IO memory space */
|
||||
if (chip->regs != 0) {
|
||||
iounmap(chip->regs);
|
||||
chip->regs = 0;
|
||||
}
|
||||
/* release the reserved IO memory space */
|
||||
if (chip->mem_base != 0) {
|
||||
release_mem_region(chip->mem_base, chip->mem_size);
|
||||
chip->mem_base = 0;
|
||||
}
|
||||
pci_disable_device(pdev);
|
||||
kfree(chip);
|
||||
dev_info(&pdev->dev, "complete\n");
|
||||
}
|
||||
|
||||
static s32 __devinit
|
||||
pch_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
||||
{
|
||||
s32 ret;
|
||||
unsigned long flags;
|
||||
struct pch_dev *chip;
|
||||
|
||||
chip = kzalloc(sizeof(struct pch_dev), GFP_KERNEL);
|
||||
if (chip == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
/* enable the 1588 pci device */
|
||||
ret = pci_enable_device(pdev);
|
||||
if (ret != 0) {
|
||||
dev_err(&pdev->dev, "could not enable the pci device\n");
|
||||
goto err_pci_en;
|
||||
}
|
||||
|
||||
chip->mem_base = pci_resource_start(pdev, IO_MEM_BAR);
|
||||
if (!chip->mem_base) {
|
||||
dev_err(&pdev->dev, "could not locate IO memory address\n");
|
||||
ret = -ENODEV;
|
||||
goto err_pci_start;
|
||||
}
|
||||
|
||||
/* retrieve the available length of the IO memory space */
|
||||
chip->mem_size = pci_resource_len(pdev, IO_MEM_BAR);
|
||||
|
||||
/* allocate the memory for the device registers */
|
||||
if (!request_mem_region(chip->mem_base, chip->mem_size, "1588_regs")) {
|
||||
dev_err(&pdev->dev,
|
||||
"could not allocate register memory space\n");
|
||||
ret = -EBUSY;
|
||||
goto err_req_mem_region;
|
||||
}
|
||||
|
||||
/* get the virtual address to the 1588 registers */
|
||||
chip->regs = ioremap(chip->mem_base, chip->mem_size);
|
||||
|
||||
if (!chip->regs) {
|
||||
dev_err(&pdev->dev, "Could not get virtual address\n");
|
||||
ret = -ENOMEM;
|
||||
goto err_ioremap;
|
||||
}
|
||||
|
||||
chip->caps = ptp_pch_caps;
|
||||
chip->ptp_clock = ptp_clock_register(&chip->caps);
|
||||
|
||||
if (IS_ERR(chip->ptp_clock))
|
||||
return PTR_ERR(chip->ptp_clock);
|
||||
|
||||
spin_lock_init(&chip->register_lock);
|
||||
|
||||
ret = request_irq(pdev->irq, &isr, IRQF_SHARED, KBUILD_MODNAME, chip);
|
||||
if (ret != 0) {
|
||||
dev_err(&pdev->dev, "failed to get irq %d\n", pdev->irq);
|
||||
goto err_req_irq;
|
||||
}
|
||||
|
||||
/* indicate success */
|
||||
chip->irq = pdev->irq;
|
||||
chip->pdev = pdev;
|
||||
pci_set_drvdata(pdev, chip);
|
||||
|
||||
spin_lock_irqsave(&chip->register_lock, flags);
|
||||
/* reset the ieee1588 h/w */
|
||||
pch_reset(chip);
|
||||
|
||||
iowrite32(DEFAULT_ADDEND, &chip->regs->addend);
|
||||
iowrite32(1, &chip->regs->trgt_lo);
|
||||
iowrite32(0, &chip->regs->trgt_hi);
|
||||
iowrite32(PCH_TSE_TTIPEND, &chip->regs->event);
|
||||
/* Version: IEEE1588 v1 and IEEE1588-2008, Mode: All Evwnt, Locked */
|
||||
iowrite32(0x80020000, &chip->regs->ch_control);
|
||||
|
||||
pch_eth_enable_set(chip);
|
||||
|
||||
if (strcmp(pch_param.station, "00:00:00:00:00:00") != 0) {
|
||||
if (pch_set_station_address(pch_param.station, pdev) != 0) {
|
||||
dev_err(&pdev->dev,
|
||||
"Invalid station address parameter\n"
|
||||
"Module loaded but station address not set correctly\n"
|
||||
);
|
||||
}
|
||||
}
|
||||
spin_unlock_irqrestore(&chip->register_lock, flags);
|
||||
return 0;
|
||||
|
||||
err_req_irq:
|
||||
ptp_clock_unregister(chip->ptp_clock);
|
||||
iounmap(chip->regs);
|
||||
chip->regs = 0;
|
||||
|
||||
err_ioremap:
|
||||
release_mem_region(chip->mem_base, chip->mem_size);
|
||||
|
||||
err_req_mem_region:
|
||||
chip->mem_base = 0;
|
||||
|
||||
err_pci_start:
|
||||
pci_disable_device(pdev);
|
||||
|
||||
err_pci_en:
|
||||
kfree(chip);
|
||||
dev_err(&pdev->dev, "probe failed(ret=0x%x)\n", ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static DEFINE_PCI_DEVICE_TABLE(pch_ieee1588_pcidev_id) = {
|
||||
{
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_PCH_1588
|
||||
},
|
||||
{0}
|
||||
};
|
||||
|
||||
static struct pci_driver pch_pcidev = {
|
||||
.name = KBUILD_MODNAME,
|
||||
.id_table = pch_ieee1588_pcidev_id,
|
||||
.probe = pch_probe,
|
||||
.remove = pch_remove,
|
||||
.suspend = pch_suspend,
|
||||
.resume = pch_resume,
|
||||
};
|
||||
|
||||
static void __exit ptp_pch_exit(void)
|
||||
{
|
||||
pci_unregister_driver(&pch_pcidev);
|
||||
}
|
||||
|
||||
static s32 __init ptp_pch_init(void)
|
||||
{
|
||||
s32 ret;
|
||||
|
||||
/* register the driver with the pci core */
|
||||
ret = pci_register_driver(&pch_pcidev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
module_init(ptp_pch_init);
|
||||
module_exit(ptp_pch_exit);
|
||||
|
||||
module_param_string(station, pch_param.station, sizeof pch_param.station, 0444);
|
||||
MODULE_PARM_DESC(station,
|
||||
"IEEE 1588 station address to use - column separated hex values");
|
||||
|
||||
MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>");
|
||||
MODULE_DESCRIPTION("PTP clock using the EG20T timer");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue
Block a user