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arm64: dts: imx8mp-icore-mx8mp-edim2.2: correct pad settings
BIT3 and BIT0 are reserved bits, should not touch.
Fixes: aec8ad34f7
("arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
parent
242d8ee911
commit
8630354f42
@ -110,28 +110,28 @@
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&iomuxc {
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&iomuxc {
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pinctrl_eqos: eqosgrp {
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pinctrl_eqos: eqosgrp {
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fsl,pins = <
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fsl,pins = <
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MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
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MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
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MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
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MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
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MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
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MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
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MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
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MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
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MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
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MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
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MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
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MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
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MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
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MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
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MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
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MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
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MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
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MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
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MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
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MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
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MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
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MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
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MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
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MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
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MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
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MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
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MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
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MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
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MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x19
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MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x10
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>;
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>;
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};
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};
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pinctrl_uart2: uart2grp {
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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fsl,pins = <
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MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
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MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40
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MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
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MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40
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>;
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>;
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};
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};
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@ -151,7 +151,7 @@
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MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
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MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
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MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
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MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
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MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
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MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
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MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
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MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
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>;
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>;
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};
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};
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@ -163,13 +163,13 @@
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pinctrl_reg_usb1: regusb1grp {
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pinctrl_reg_usb1: regusb1grp {
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fsl,pins = <
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fsl,pins = <
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MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19
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MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x10
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>;
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>;
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};
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};
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pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
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pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
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fsl,pins = <
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fsl,pins = <
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MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
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MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
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>;
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>;
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};
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};
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};
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};
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