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sh: Cleanup IRQ disabling for hardirq handlers.

Browse Source 
The generic hardirq layer already takes care of a lot of the
appropriate locking and disabling for us, no need to duplicate
it in the handlers..

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt 2006-09-27 18:03:34 +09:00
parent ba463937ef
commit 8599cf0592
15 changed files with 38 additions and 156 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

47
arch/sh/boards/bigsur/irq.c
View File

@ -19,6 +19,7 @@
* IRQ functions for a Hitachi Big Sur Evaluation Board.
*
*/
#undef DEBUG
#include <linux/sched.h>
#include <linux/module.h>
@ -41,10 +42,8 @@
#undef BIGSUR_DEBUG
#ifdef BIGSUR_DEBUG
#define DPRINTK(args...) printk(args)
#define DIPRINTK(n, args...) if (BIGSUR_DEBUG>(n)) printk(args)
#else
#define DPRINTK(args...)
#define DIPRINTK(n, args...)
#endif /* BIGSUR_DEBUG */
@ -60,45 +59,39 @@ extern int hd64465_irq_demux(int irq);
/* Level 1 IRQ routines */
static void disable_bigsur_l1irq(unsigned int irq)
{
unsigned long flags;
unsigned char mask;
unsigned int mask_port = ((irq - BIGSUR_IRQ_LOW)/8) ? BIGSUR_IRLMR1 : BIGSUR_IRLMR0;
unsigned char bit = (1 << ((irq - MGATE_IRQ_LOW)%8) );
if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH) {
DPRINTK("Disable L1 IRQ %d\n", irq);
pr_debug("Disable L1 IRQ %d\n", irq);
DIPRINTK(2,"disable_bigsur_l1irq: IMR=0x%08x mask=0x%x\n",
mask_port, bit);
local_irq_save(flags);
/* Disable IRQ - set mask bit */
mask = inb(mask_port) | bit;
outb(mask, mask_port);
local_irq_restore(flags);
return;
}
DPRINTK("disable_bigsur_l1irq: Invalid IRQ %d\n", irq);
pr_debug("disable_bigsur_l1irq: Invalid IRQ %d\n", irq);
}
static void enable_bigsur_l1irq(unsigned int irq)
{
unsigned long flags;
unsigned char mask;
unsigned int mask_port = ((irq - BIGSUR_IRQ_LOW)/8) ? BIGSUR_IRLMR1 : BIGSUR_IRLMR0;
unsigned char bit = (1 << ((irq - MGATE_IRQ_LOW)%8) );
if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH) {
DPRINTK("Enable L1 IRQ %d\n", irq);
pr_debug("Enable L1 IRQ %d\n", irq);
DIPRINTK(2,"enable_bigsur_l1irq: IMR=0x%08x mask=0x%x\n",
mask_port, bit);
local_irq_save(flags);
/* Enable L1 IRQ - clear mask bit */
mask = inb(mask_port) & ~bit;
outb(mask, mask_port);
local_irq_restore(flags);
return;
}
DPRINTK("enable_bigsur_l1irq: Invalid IRQ %d\n", irq);
pr_debug("enable_bigsur_l1irq: Invalid IRQ %d\n", irq);
}
@ -126,51 +119,45 @@ static const u32 imr_offset = BIGSUR_IMR0 - BIGSUR_IMR1;
/* Level 2 IRQ routines */
static void disable_bigsur_l2irq(unsigned int irq)
{
unsigned long flags;
unsigned char mask;
unsigned char bit = 1 << ((irq-BIGSUR_2NDLVL_IRQ_LOW)%8);
unsigned int mask_port = imr_base - REG_NUM(irq)*imr_offset;
if(irq >= BIGSUR_2NDLVL_IRQ_LOW && irq < BIGSUR_2NDLVL_IRQ_HIGH) {
DPRINTK("Disable L2 IRQ %d\n", irq);
if(irq >= BIGSUR_2NDLVL_IRQ_LOW && irq < BIGSUR_2NDLVL_IRQ_HIGH) {
pr_debug("Disable L2 IRQ %d\n", irq);
DIPRINTK(2,"disable_bigsur_l2irq: IMR=0x%08x mask=0x%x\n",
mask_port, bit);
local_irq_save(flags);
/* Disable L2 IRQ - set mask bit */
mask = inb(mask_port) | bit;
outb(mask, mask_port);
local_irq_restore(flags);
return;
}
DPRINTK("disable_bigsur_l2irq: Invalid IRQ %d\n", irq);
pr_debug("disable_bigsur_l2irq: Invalid IRQ %d\n", irq);
}
static void enable_bigsur_l2irq(unsigned int irq)
{
unsigned long flags;
unsigned char mask;
unsigned char bit = 1 << ((irq-BIGSUR_2NDLVL_IRQ_LOW)%8);
unsigned int mask_port = imr_base - REG_NUM(irq)*imr_offset;
if(irq >= BIGSUR_2NDLVL_IRQ_LOW && irq < BIGSUR_2NDLVL_IRQ_HIGH) {
DPRINTK("Enable L2 IRQ %d\n", irq);
if(irq >= BIGSUR_2NDLVL_IRQ_LOW && irq < BIGSUR_2NDLVL_IRQ_HIGH) {
pr_debug("Enable L2 IRQ %d\n", irq);
DIPRINTK(2,"enable_bigsur_l2irq: IMR=0x%08x mask=0x%x\n",
mask_port, bit);
local_irq_save(flags);
/* Enable L2 IRQ - clear mask bit */
mask = inb(mask_port) & ~bit;
outb(mask, mask_port);
local_irq_restore(flags);
return;
}
DPRINTK("enable_bigsur_l2irq: Invalid IRQ %d\n", irq);
pr_debug("enable_bigsur_l2irq: Invalid IRQ %d\n", irq);
}
static void mask_and_ack_bigsur(unsigned int irq)
{
DPRINTK("mask_and_ack_bigsur IRQ %d\n", irq);
pr_debug("mask_and_ack_bigsur IRQ %d\n", irq);
if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH)
disable_bigsur_l1irq(irq);
else
@ -179,7 +166,7 @@ static void mask_and_ack_bigsur(unsigned int irq)
static void end_bigsur_irq(unsigned int irq)
{
DPRINTK("end_bigsur_irq IRQ %d\n", irq);
pr_debug("end_bigsur_irq IRQ %d\n", irq);
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH)
enable_bigsur_l1irq(irq);
@ -193,7 +180,7 @@ static unsigned int startup_bigsur_irq(unsigned int irq)
u8 mask;
u32 reg;
DPRINTK("startup_bigsur_irq IRQ %d\n", irq);
pr_debug("startup_bigsur_irq IRQ %d\n", irq);
if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH) {
/* Enable the L1 IRQ */
@ -218,7 +205,7 @@ static unsigned int startup_bigsur_irq(unsigned int irq)
static void shutdown_bigsur_irq(unsigned int irq)
{
DPRINTK("shutdown_bigsur_irq IRQ %d\n", irq);
pr_debug("shutdown_bigsur_irq IRQ %d\n", irq);
if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH)
disable_bigsur_l1irq(irq);
else
@ -260,7 +247,7 @@ static void make_bigsur_l1isr(unsigned int irq) {
disable_bigsur_l1irq(irq);
return;
}
DPRINTK("make_bigsur_l1isr: bad irq, %d\n", irq);
pr_debug("make_bigsur_l1isr: bad irq, %d\n", irq);
return;
}
@ -277,7 +264,7 @@ static void make_bigsur_l2isr(unsigned int irq) {
disable_bigsur_l2irq(irq);
return;
}
DPRINTK("make_bigsur_l2isr: bad irq, %d\n", irq);
pr_debug("make_bigsur_l2isr: bad irq, %d\n", irq);
return;
}

7
arch/sh/boards/dreamcast/irq.c
View File

@ -10,7 +10,6 @@
*/
#include <linux/irq.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/dreamcast/sysasic.h>
@ -57,29 +56,23 @@
/* Disable the hardware event by masking its bit in its EMR */
static inline void disable_systemasic_irq(unsigned int irq)
{
unsigned long flags;
__u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
__u32 mask;
local_irq_save(flags);
mask = inl(emr);
mask &= ~(1 << EVENT_BIT(irq));
outl(mask, emr);
local_irq_restore(flags);
}
/* Enable the hardware event by setting its bit in its EMR */
static inline void enable_systemasic_irq(unsigned int irq)
{
unsigned long flags;
__u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
__u32 mask;
local_irq_save(flags);
mask = inl(emr);
mask |= (1 << EVENT_BIT(irq));
outl(mask, emr);
local_irq_restore(flags);
}
/* Acknowledge a hardware event by writing its bit back to its ESR */

6
arch/sh/boards/landisk/irq.c
View File

@ -39,30 +39,24 @@ static unsigned int startup_landisk_irq(unsigned int irq)
static void disable_landisk_irq(unsigned int irq)
{
unsigned long flags;
unsigned char val;
unsigned char mask = 0xff ^ (0x01 << (irq - 5));
/* Set the priority in IPR to 0 */
local_irq_save(flags);
val = ctrl_inb(PA_IMASK);
val &= mask;
ctrl_outb(val, PA_IMASK);
local_irq_restore(flags);
}
static void enable_landisk_irq(unsigned int irq)
{
unsigned long flags;
unsigned char val;
unsigned char value = (0x01 << (irq - 5));
/* Set priority in IPR back to original value */
local_irq_save(flags);
val = ctrl_inb(PA_IMASK);
val |= value;
ctrl_outb(val, PA_IMASK);
local_irq_restore(flags);
}
static void ack_landisk_irq(unsigned int irq)

14
arch/sh/boards/mpc1211/setup.c
View File

@ -80,9 +80,6 @@ volatile unsigned long irq_err_count;
static void disable_mpc1211_irq(unsigned int irq)
{
unsigned long flags;
save_and_cli(flags);
if( irq < 8) {
m_irq_mask |= (1 << irq);
outb(m_irq_mask,I8259_M_MR);
@ -90,16 +87,11 @@ static void disable_mpc1211_irq(unsigned int irq)
s_irq_mask |= (1 << (irq - 8));
outb(s_irq_mask,I8259_S_MR);
}
restore_flags(flags);
}
static void enable_mpc1211_irq(unsigned int irq)
{
unsigned long flags;
save_and_cli(flags);
if( irq < 8) {
m_irq_mask &= ~(1 << irq);
outb(m_irq_mask,I8259_M_MR);
@ -107,7 +99,6 @@ static void enable_mpc1211_irq(unsigned int irq)
s_irq_mask &= ~(1 << (irq - 8));
outb(s_irq_mask,I8259_S_MR);
}
restore_flags(flags);
}
static inline int mpc1211_irq_real(unsigned int irq)
@ -131,10 +122,6 @@ static inline int mpc1211_irq_real(unsigned int irq)
static void mask_and_ack_mpc1211(unsigned int irq)
{
unsigned long flags;
save_and_cli(flags);
if(irq < 8) {
if(m_irq_mask & (1<<irq)){
if(!mpc1211_irq_real(irq)){
@ -162,7 +149,6 @@ static void mask_and_ack_mpc1211(unsigned int irq)
outb(0x60+(irq-8),I8259_S_CR); /* EOI */
outb(0x60+2,I8259_M_CR);
}
restore_flags(flags);
}
static void end_mpc1211_irq(unsigned int irq)

6
arch/sh/boards/renesas/hs7751rvoip/irq.c
View File

@ -35,30 +35,24 @@ static unsigned int startup_hs7751rvoip_irq(unsigned int irq)
static void disable_hs7751rvoip_irq(unsigned int irq)
{
unsigned long flags;
unsigned short val;
unsigned short mask = 0xffff ^ (0x0001 << mask_pos[irq]);
/* Set the priority in IPR to 0 */
local_irq_save(flags);
val = ctrl_inw(IRLCNTR3);
val &= mask;
ctrl_outw(val, IRLCNTR3);
local_irq_restore(flags);
}
static void enable_hs7751rvoip_irq(unsigned int irq)
{
unsigned long flags;
unsigned short val;
unsigned short value = (0x0001 << mask_pos[irq]);
/* Set priority in IPR back to original value */
local_irq_save(flags);
val = ctrl_inw(IRLCNTR3);
val |= value;
ctrl_outw(val, IRLCNTR3);
local_irq_restore(flags);
}
static void ack_hs7751rvoip_irq(unsigned int irq)

6
arch/sh/boards/renesas/r7780rp/irq.c
View File

@ -39,30 +39,24 @@ static unsigned int startup_r7780rp_irq(unsigned int irq)
static void disable_r7780rp_irq(unsigned int irq)
{
unsigned long flags;
unsigned short val;
unsigned short mask = 0xffff ^ (0x0001 << mask_pos[irq]);
/* Set the priority in IPR to 0 */
local_irq_save(flags);
val = ctrl_inw(IRLCNTR1);
val &= mask;
ctrl_outw(val, IRLCNTR1);
local_irq_restore(flags);
}
static void enable_r7780rp_irq(unsigned int irq)
{
unsigned long flags;
unsigned short val;
unsigned short value = (0x0001 << mask_pos[irq]);
/* Set priority in IPR back to original value */
local_irq_save(flags);
val = ctrl_inw(IRLCNTR1);
val |= value;
ctrl_outw(val, IRLCNTR1);
local_irq_restore(flags);
}
static void ack_r7780rp_irq(unsigned int irq)

6
arch/sh/boards/renesas/rts7751r2d/irq.c
View File

@ -41,30 +41,24 @@ static unsigned int startup_rts7751r2d_irq(unsigned int irq)
static void disable_rts7751r2d_irq(unsigned int irq)
{
unsigned long flags;
unsigned short val;
unsigned short mask = 0xffff ^ (0x0001 << mask_pos[irq]);
/* Set the priority in IPR to 0 */
local_irq_save(flags);
val = ctrl_inw(IRLCNTR1);
val &= mask;
ctrl_outw(val, IRLCNTR1);
local_irq_restore(flags);
}
static void enable_rts7751r2d_irq(unsigned int irq)
{
unsigned long flags;
unsigned short val;
unsigned short value = (0x0001 << mask_pos[irq]);
/* Set priority in IPR back to original value */
local_irq_save(flags);
val = ctrl_inw(IRLCNTR1);
val |= value;
ctrl_outw(val, IRLCNTR1);
local_irq_restore(flags);
}
int rts7751r2d_irq_demux(int irq)

8
arch/sh/boards/renesas/systemh/irq.c
View File

@ -57,12 +57,9 @@ static void shutdown_systemh_irq(unsigned int irq)
static void disable_systemh_irq(unsigned int irq)
{
if (systemh_irq_mask_register) {
unsigned long flags;
unsigned long val, mask = 0x01 << 1;
/* Clear the "irq"th bit in the mask and set it in the request */
local_irq_save(flags);
val = ctrl_inl((unsigned long)systemh_irq_mask_register);
val &= ~mask;
ctrl_outl(val, (unsigned long)systemh_irq_mask_register);
@ -70,23 +67,18 @@ static void disable_systemh_irq(unsigned int irq)
val = ctrl_inl((unsigned long)systemh_irq_request_register);
val |= mask;
ctrl_outl(val, (unsigned long)systemh_irq_request_register);
local_irq_restore(flags);
}
}
static void enable_systemh_irq(unsigned int irq)
{
if (systemh_irq_mask_register) {
unsigned long flags;
unsigned long val, mask = 0x01 << 1;
/* Set "irq"th bit in the mask register */
local_irq_save(flags);
val = ctrl_inl((unsigned long)systemh_irq_mask_register);
val |= mask;
ctrl_outl(val, (unsigned long)systemh_irq_mask_register);
local_irq_restore(flags);
}
}

39
arch/sh/boards/superh/microdev/irq.c
View File

@ -11,14 +11,12 @@
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/system.h>
#include <asm/io.h>
#include <asm/microdev.h>
#define NUM_EXTERNAL_IRQS 16 /* IRL0 .. IRL15 */
static const struct {
unsigned char fpgaIrq;
unsigned char mapped;
@ -93,53 +91,42 @@ static struct hw_interrupt_type microdev_irq_type = {
static void disable_microdev_irq(unsigned int irq)
{
unsigned int flags;
unsigned int fpgaIrq;
if (irq >= NUM_EXTERNAL_IRQS) return;
if (!fpgaIrqTable[irq].mapped) return;
if (irq >= NUM_EXTERNAL_IRQS)
return;
if (!fpgaIrqTable[irq].mapped)
return;
fpgaIrq = fpgaIrqTable[irq].fpgaIrq;
/* disable interrupts */
local_irq_save(flags);
/* disable interupts on the FPGA INTC register */
/* disable interupts on the FPGA INTC register */
ctrl_outl(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTDSB_REG);
/* restore interrupts */
local_irq_restore(flags);
}
static void enable_microdev_irq(unsigned int irq)
{
unsigned long priorityReg, priorities, pri;
unsigned int flags;
unsigned int fpgaIrq;
if (irq >= NUM_EXTERNAL_IRQS) return;
if (!fpgaIrqTable[irq].mapped) return;
if (unlikely(irq >= NUM_EXTERNAL_IRQS))
return;
if (unlikely(!fpgaIrqTable[irq].mapped))
return;
pri = 15 - irq;
fpgaIrq = fpgaIrqTable[irq].fpgaIrq;
priorityReg = MICRODEV_FPGA_INTPRI_REG(fpgaIrq);
/* disable interrupts */
local_irq_save(flags);
/* set priority for the interrupt */
/* set priority for the interrupt */
priorities = ctrl_inl(priorityReg);
priorities &= ~MICRODEV_FPGA_INTPRI_MASK(fpgaIrq);
priorities |= MICRODEV_FPGA_INTPRI_LEVEL(fpgaIrq, pri);
ctrl_outl(priorities, priorityReg);
/* enable interupts on the FPGA INTC register */
/* enable interupts on the FPGA INTC register */
ctrl_outl(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTENB_REG);
/* restore interrupts */
local_irq_restore(flags);
}
/* This functions sets the desired irq handler to be a MicroDev type */
@ -158,9 +145,7 @@ static void mask_and_ack_microdev(unsigned int irq)
static void end_microdev_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
{
enable_microdev_irq(irq);
}
}
extern void __init init_microdev_irq(void)
@ -171,9 +156,7 @@ extern void __init init_microdev_irq(void)
ctrl_outl(~0ul, MICRODEV_FPGA_INTDSB_REG);
for (i = 0; i < NUM_EXTERNAL_IRQS; i++)
{
make_microdev_irq(i);
}
}
extern void microdev_print_fpga_intc_status(void)

7
arch/sh/cchips/hd6446x/hd64461/setup.c
View File

@ -11,35 +11,28 @@
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/hd64461.h>
static void disable_hd64461_irq(unsigned int irq)
{
unsigned long flags;
unsigned short nimr;
unsigned short mask = 1 << (irq - HD64461_IRQBASE);
local_irq_save(flags);
nimr = inw(HD64461_NIMR);
nimr |= mask;
outw(nimr, HD64461_NIMR);
local_irq_restore(flags);
}
static void enable_hd64461_irq(unsigned int irq)
{
unsigned long flags;
unsigned short nimr;
unsigned short mask = 1 << (irq - HD64461_IRQBASE);
local_irq_save(flags);
nimr = inw(HD64461_NIMR);
nimr &= ~mask;
outw(nimr, HD64461_NIMR);
local_irq_restore(flags);
}
static void mask_and_ack_hd64461(unsigned int irq)

6
arch/sh/cchips/hd6446x/hd64465/setup.c
View File

@ -25,31 +25,25 @@
static void disable_hd64465_irq(unsigned int irq)
{
unsigned long flags;
unsigned short nimr;
unsigned short mask = 1 << (irq - HD64465_IRQ_BASE);
pr_debug("disable_hd64465_irq(%d): mask=%x\n", irq, mask);
local_irq_save(flags);
nimr = inw(HD64465_REG_NIMR);
nimr |= mask;
outw(nimr, HD64465_REG_NIMR);
local_irq_restore(flags);
}
static void enable_hd64465_irq(unsigned int irq)
{
unsigned long flags;
unsigned short nimr;
unsigned short mask = 1 << (irq - HD64465_IRQ_BASE);
pr_debug("enable_hd64465_irq(%d): mask=%x\n", irq, mask);
local_irq_save(flags);
nimr = inw(HD64465_REG_NIMR);
nimr &= ~mask;
outw(nimr, HD64465_REG_NIMR);
local_irq_restore(flags);
}

20
arch/sh/cchips/voyagergx/irq.c
View File

@ -36,32 +36,26 @@
static void disable_voyagergx_irq(unsigned int irq)
{
unsigned long flags, val;
unsigned long mask = 1 << (irq - VOYAGER_IRQ_BASE);
unsigned long val;
unsigned long mask = 1 << (irq - VOYAGER_IRQ_BASE);
pr_debug("disable_voyagergx_irq(%d): mask=%x\n", irq, mask);
local_irq_save(flags);
val = inl(VOYAGER_INT_MASK);
val &= ~mask;
outl(val, VOYAGER_INT_MASK);
local_irq_restore(flags);
}
static void enable_voyagergx_irq(unsigned int irq)
{
unsigned long flags, val;
unsigned long mask = 1 << (irq - VOYAGER_IRQ_BASE);
unsigned long val;
unsigned long mask = 1 << (irq - VOYAGER_IRQ_BASE);
pr_debug("disable_voyagergx_irq(%d): mask=%x\n", irq, mask);
local_irq_save(flags);
val = inl(VOYAGER_INT_MASK);
val |= mask;
outl(val, VOYAGER_INT_MASK);
local_irq_restore(flags);
}
static void mask_and_ack_voyagergx(unsigned int irq)
{
disable_voyagergx_irq(irq);
@ -94,7 +88,8 @@ static struct hw_interrupt_type voyagergx_irq_type = {
.end = end_voyagergx_irq,
};
static irqreturn_t voyagergx_interrupt(int irq, void *dev_id, struct pt_regs *regs)
static irqreturn_t voyagergx_interrupt(int irq, void *dev_id,
struct pt_regs *regs)
{
printk(KERN_INFO
"VoyagerGX: spurious interrupt, status: 0x%x\n",
@ -102,9 +97,6 @@ static irqreturn_t voyagergx_interrupt(int irq, void *dev_id, struct pt_regs *re
return IRQ_HANDLED;
}
/*====================================================*/
static struct {
int (*func)(int, void *);
void *dev;

8
arch/sh/kernel/cpu/irq/ipr.c
View File

@ -57,31 +57,27 @@ static struct hw_interrupt_type ipr_irq_type = {
static void disable_ipr_irq(unsigned int irq)
{
unsigned long val, flags;
unsigned long val;
unsigned int addr = ipr_data[irq].addr;
unsigned short mask = 0xffff ^ (0x0f << ipr_data[irq].shift);
/* Set the priority in IPR to 0 */
local_irq_save(flags);
val = ctrl_inw(addr);
val &= mask;
ctrl_outw(val, addr);
local_irq_restore(flags);
}
static void enable_ipr_irq(unsigned int irq)
{
unsigned long val, flags;
unsigned long val;
unsigned int addr = ipr_data[irq].addr;
int priority = ipr_data[irq].priority;
unsigned short value = (priority << ipr_data[irq].shift);
/* Set priority in IPR back to original value */
local_irq_save(flags);
val = ctrl_inw(addr);
val |= value;
ctrl_outw(val, addr);
local_irq_restore(flags);
}
static void mask_and_ack_ipr(unsigned int irq)

6
arch/sh/kernel/cpu/irq/maskreg.c
View File

@ -52,32 +52,26 @@ static void shutdown_maskreg_irq(unsigned int irq)
static void disable_maskreg_irq(unsigned int irq)
{
unsigned long flags;
unsigned short val, mask = 0x01 << irq;
BUG_ON(!irq_mask_register);
/* Set "irq"th bit */
local_irq_save(flags);
val = ctrl_inw(irq_mask_register);
val |= mask;
ctrl_outw(val, irq_mask_register);
local_irq_restore(flags);
}
static void enable_maskreg_irq(unsigned int irq)
{
unsigned long flags;
unsigned short val, mask = ~(0x01 << irq);
BUG_ON(!irq_mask_register);
/* Clear "irq"th bit */
local_irq_save(flags);
val = ctrl_inw(irq_mask_register);
val &= mask;
ctrl_outw(val, irq_mask_register);
local_irq_restore(flags);
}
static void mask_and_ack_maskreg(unsigned int irq)

8
arch/sh/kernel/cpu/irq/pint.c
View File

@ -48,26 +48,22 @@ static struct hw_interrupt_type pint_irq_type = {
static void disable_pint_irq(unsigned int irq)
{
unsigned long val, flags;
unsigned long val;
local_irq_save(flags);
val = ctrl_inw(INTC_INTER);
val &= ~(1 << (irq - PINT_IRQ_BASE));
ctrl_outw(val, INTC_INTER); /* disable PINTn */
portcr_mask &= ~(3 << (irq - PINT_IRQ_BASE)*2);
local_irq_restore(flags);
}
static void enable_pint_irq(unsigned int irq)
{
unsigned long val, flags;
unsigned long val;
local_irq_save(flags);
val = ctrl_inw(INTC_INTER);
val |= 1 << (irq - PINT_IRQ_BASE);
ctrl_outw(val, INTC_INTER); /* enable PINTn */
portcr_mask |= 3 << (irq - PINT_IRQ_BASE)*2;
local_irq_restore(flags);
}
static void mask_and_ack_pint(unsigned int irq)