Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS updates from Ralf Baechle:
 "This is the MIPS pull request for the next kernel:

   - Zubair's patch series adds CMA support for MIPS.  Doing so it also
     touches ARM64 and x86.
   - remove the last instance of IRQF_DISABLED from arch/mips
   - updates to two of the MIPS defconfig files.
   - cleanup of how cache coherency bits are handled on MIPS and
     implement support for write-combining.
   - platform upgrades for Alchemy
   - move MIPS DTS files to arch/mips/boot/dts/"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (24 commits)
  MIPS: ralink: remove deprecated IRQF_DISABLED
  MIPS: pgtable.h: Implement the pgprot_writecombine function for MIPS
  MIPS: cpu-probe: Set the write-combine CCA value on per core basis
  MIPS: pgtable-bits: Define the CCA bit for WC writes on Ingenic cores
  MIPS: pgtable-bits: Move the CCA bits out of the core's ifdef blocks
  MIPS: DMA: Add cma support
  x86: use generic dma-contiguous.h
  arm64: use generic dma-contiguous.h
  asm-generic: Add dma-contiguous.h
  MIPS: BPF: Add new emit_long_instr macro
  MIPS: ralink: Move device-trees to arch/mips/boot/dts/
  MIPS: Netlogic: Move device-trees to arch/mips/boot/dts/
  MIPS: sead3: Move device-trees to arch/mips/boot/dts/
  MIPS: Lantiq: Move device-trees to arch/mips/boot/dts/
  MIPS: Octeon: Move device-trees to arch/mips/boot/dts/
  MIPS: Add support for building device-tree binaries
  MIPS: Create common infrastructure for building built-in device-trees
  MIPS: SEAD3: Enable DEVTMPFS
  MIPS: SEAD3: Regenerate defconfigs
  MIPS: Alchemy: DB1300: Add touch penirq support
  ...
This commit is contained in:
Linus Torvalds 2014-10-18 14:24:36 -07:00
commit 857b50f5d0
57 changed files with 272 additions and 136 deletions

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@ -9,6 +9,7 @@ generic-y += current.h
generic-y += delay.h
generic-y += div64.h
generic-y += dma.h
generic-y += dma-contiguous.h
generic-y += early_ioremap.h
generic-y += emergency-restart.h
generic-y += errno.h

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@ -1,28 +0,0 @@
/*
* Copyright (c) 2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _ASM_DMA_CONTIGUOUS_H
#define _ASM_DMA_CONTIGUOUS_H
#ifdef __KERNEL__
#ifdef CONFIG_DMA_CMA
#include <linux/types.h>
static inline void
dma_contiguous_early_fixup(phys_addr_t base, unsigned long size) { }
#endif
#endif
#endif

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@ -29,6 +29,7 @@ config MIPS
select GENERIC_ATOMIC64 if !64BIT
select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
select HAVE_DMA_ATTRS
select HAVE_DMA_CONTIGUOUS
select HAVE_DMA_API_DEBUG
select GENERIC_IRQ_PROBE
select GENERIC_IRQ_SHOW
@ -353,6 +354,7 @@ config MIPS_SEAD3
bool "MIPS SEAD3 board"
select BOOT_ELF32
select BOOT_RAW
select BUILTIN_DTB
select CEVT_R4K
select CSRC_R4K
select CSRC_GIC
@ -742,6 +744,7 @@ config CAVIUM_OCTEON_SOC
select ARCH_SPARSEMEM_ENABLE
select SYS_SUPPORTS_SMP
select NR_CPUS_DEFAULT_16
select BUILTIN_DTB
help
This option supports all of the Octeon reference boards from Cavium
Networks. It builds a kernel that dynamically determines the Octeon
@ -2482,6 +2485,9 @@ config USE_OF
select OF_EARLY_FLATTREE
select IRQ_DOMAIN
config BUILTIN_DTB
bool
endmenu
config LOCKDEP_SUPPORT

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@ -333,6 +333,16 @@ endif
CLEAN_FILES += vmlinux.32 vmlinux.64
# device-trees
core-$(CONFIG_BUILTIN_DTB) += arch/mips/boot/dts/
%.dtb %.dtb.S %.dtb.o: | scripts
$(Q)$(MAKE) $(build)=arch/mips/boot/dts arch/mips/boot/dts/$@
PHONY += dtbs
dtbs: scripts
$(Q)$(MAKE) $(build)=arch/mips/boot/dts dtbs
archprepare:
ifdef CONFIG_MIPS32_N32
@echo ' Checking missing-syscalls for N32'
@ -367,6 +377,7 @@ define archhelp
echo ' vmlinuz.srec - SREC zboot image'
echo ' uImage - U-Boot image'
echo ' uImage.gz - U-Boot image (gzip)'
echo ' dtbs - Device-tree blobs for enabled boards'
echo
echo ' These will be default as appropriate for a configured platform.'
endef

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@ -21,6 +21,7 @@
#include <linux/mtd/partitions.h>
#include <linux/platform_device.h>
#include <linux/smsc911x.h>
#include <linux/wm97xx.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1100_mmc.h>
@ -711,6 +712,46 @@ static struct platform_device db1300_lcd_dev = {
/**********************************************************************/
static void db1300_wm97xx_irqen(struct wm97xx *wm, int enable)
{
if (enable)
enable_irq(DB1300_AC97_PEN_INT);
else
disable_irq_nosync(DB1300_AC97_PEN_INT);
}
static struct wm97xx_mach_ops db1300_wm97xx_ops = {
.irq_enable = db1300_wm97xx_irqen,
.irq_gpio = WM97XX_GPIO_3,
};
static int db1300_wm97xx_probe(struct platform_device *pdev)
{
struct wm97xx *wm = platform_get_drvdata(pdev);
/* external pendown indicator */
wm97xx_config_gpio(wm, WM97XX_GPIO_13, WM97XX_GPIO_IN,
WM97XX_GPIO_POL_LOW, WM97XX_GPIO_STICKY,
WM97XX_GPIO_WAKE);
/* internal "virtual" pendown gpio */
wm97xx_config_gpio(wm, WM97XX_GPIO_3, WM97XX_GPIO_OUT,
WM97XX_GPIO_POL_LOW, WM97XX_GPIO_NOTSTICKY,
WM97XX_GPIO_NOWAKE);
wm->pen_irq = DB1300_AC97_PEN_INT;
return wm97xx_register_mach_ops(wm, &db1300_wm97xx_ops);
}
static struct platform_driver db1300_wm97xx_driver = {
.driver.name = "wm97xx-touch",
.driver.owner = THIS_MODULE,
.probe = db1300_wm97xx_probe,
};
/**********************************************************************/
static struct platform_device *db1300_dev[] __initdata = {
&db1300_eth_dev,
&db1300_i2c_dev,
@ -755,6 +796,9 @@ int __init db1300_dev_setup(void)
i2c_register_board_info(0, db1300_i2c_devs,
ARRAY_SIZE(db1300_i2c_devs));
if (platform_driver_register(&db1300_wm97xx_driver))
pr_warn("DB1300: failed to init touch pen irq support!\n");
/* Audio PSC clock is supplied by codecs (PSC1, 2) */
__raw_writel(PSC_SEL_CLK_SERCLK,
(void __iomem *)KSEG1ADDR(AU1300_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
@ -762,9 +806,10 @@ int __init db1300_dev_setup(void)
__raw_writel(PSC_SEL_CLK_SERCLK,
(void __iomem *)KSEG1ADDR(AU1300_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET);
wmb();
/* I2C uses internal 48MHz EXTCLK1 */
/* I2C driver wants 50MHz, get as close as possible */
c = clk_get(NULL, "psc3_intclk");
if (!IS_ERR(c)) {
clk_set_rate(c, 50000000);
clk_prepare_enable(c);
clk_put(c);
}

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@ -34,12 +34,9 @@ static void __init db1550_hw_setup(void)
void __iomem *base;
unsigned long v;
/* complete SPI setup: link psc0_intclk to a 48MHz source,
* and assign GPIO16 to PSC0_SYNC1 (SPI cs# line) as well as PSC1_SYNC
* for AC97 on PB1550.
/* complete pin setup: assign GPIO16 to PSC0_SYNC1 (SPI cs# line)
* as well as PSC1_SYNC for AC97 on PB1550.
*/
v = alchemy_rdsys(AU1000_SYS_CLKSRC);
alchemy_wrsys(v | 0x000001e0, AU1000_SYS_CLKSRC);
v = alchemy_rdsys(AU1000_SYS_PINFUNC);
alchemy_wrsys(v | 1 | SYS_PF_PSC1_S1, AU1000_SYS_PINFUNC);
@ -586,11 +583,13 @@ int __init db1550_dev_setup(void)
c = clk_get(NULL, "psc0_intclk");
if (!IS_ERR(c)) {
clk_set_rate(c, 50000000);
clk_prepare_enable(c);
clk_put(c);
}
c = clk_get(NULL, "psc2_intclk");
if (!IS_ERR(c)) {
clk_set_rate(c, db1550_spi_platdata.mainclk_hz);
clk_prepare_enable(c);
clk_put(c);
}

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@ -11,6 +11,7 @@
#include <linux/pm.h>
#include <asm/bootinfo.h>
#include <asm/idle.h>
#include <asm/reboot.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-db1x00/bcsr.h>
@ -53,6 +54,8 @@ static void db1x_power_off(void)
{
bcsr_write(BCSR_RESETS, 0);
bcsr_write(BCSR_SYSTEM, BCSR_SYSTEM_PWROFF | BCSR_SYSTEM_RESET);
while (1) /* sit and spin */
cpu_wait();
}
static void db1x_reset(char *c)

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@ -5,3 +5,4 @@ zImage
zImage.tmp
calc_vmlinuz_load_addr
uImage
*.dtb

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@ -0,0 +1,20 @@
dtb-$(CONFIG_CAVIUM_OCTEON_SOC) += octeon_3xxx.dtb octeon_68xx.dtb
dtb-$(CONFIG_DT_EASY50712) += easy50712.dtb
dtb-$(CONFIG_DT_XLP_EVP) += xlp_evp.dtb
dtb-$(CONFIG_DT_XLP_SVP) += xlp_svp.dtb
dtb-$(CONFIG_DT_XLP_FVP) += xlp_fvp.dtb
dtb-$(CONFIG_DT_XLP_GVP) += xlp_gvp.dtb
dtb-$(CONFIG_DTB_RT2880_EVAL) += rt2880_eval.dtb
dtb-$(CONFIG_DTB_RT305X_EVAL) += rt3052_eval.dtb
dtb-$(CONFIG_DTB_RT3883_EVAL) += rt3883_eval.dtb
dtb-$(CONFIG_DTB_MT7620A_EVAL) += mt7620a_eval.dtb
dtb-$(CONFIG_MIPS_SEAD3) += sead3.dtb
obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
targets += dtbs
targets += $(dtb-y)
dtbs: $(addprefix $(obj)/, $(dtb-y))
clean-files += *.dtb *.dtb.S

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@ -1,2 +0,0 @@
*.dtb.S
*.dtb

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@ -20,13 +20,3 @@ obj-y += executive/
obj-$(CONFIG_MTD) += flash_setup.o
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_OCTEON_ILM) += oct_ilm.o
DTS_FILES = octeon_3xxx.dts octeon_68xx.dts
DTB_FILES = $(patsubst %.dts, %.dtb, $(DTS_FILES))
obj-y += $(patsubst %.dts, %.dtb.o, $(DTS_FILES))
# Let's keep the .dtb files around in case we want to look at them.
.SECONDARY: $(addprefix $(obj)/, $(DTB_FILES))
clean-files += $(DTB_FILES) $(patsubst %.dtb, %.dtb.S, $(DTB_FILES))

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@ -31,8 +31,8 @@ CONFIG_IP_PNP_BOOTP=y
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_MTD=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y

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@ -32,8 +32,8 @@ CONFIG_IP_PNP_BOOTP=y
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_MTD=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y

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@ -1,6 +1,7 @@
# MIPS headers
generic-y += cputime.h
generic-y += current.h
generic-y += dma-contiguous.h
generic-y += emergency-restart.h
generic-y += hash.h
generic-y += irq_work.h

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@ -231,6 +231,16 @@
#define cpu_has_clo_clz cpu_has_mips_r
#endif
/*
* MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH.
* MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD.
* This indicates the availability of WSBH and in case of 64 bit CPUs also
* DSBH and DSHD.
*/
#ifndef cpu_has_wsbh
#define cpu_has_wsbh cpu_has_mips_r2
#endif
#ifndef cpu_has_dsp
#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
#endif

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@ -79,6 +79,11 @@ struct cpuinfo_mips {
#define NUM_WATCH_REGS 4
u16 watch_reg_masks[NUM_WATCH_REGS];
unsigned int kscratch_mask; /* Usable KScratch mask. */
/*
* Cache Coherency attribute for write-combine memory writes.
* (shifted by _CACHE_SHIFT)
*/
unsigned int writecombine;
} __attribute__((aligned(SMP_CACHE_BYTES)));
extern struct cpuinfo_mips cpu_data[];

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@ -8,6 +8,12 @@
#define __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H
#define cpu_has_tlb 1
#define cpu_has_tlbinv 0
#define cpu_has_segments 0
#define cpu_has_eva 0
#define cpu_has_htw 0
#define cpu_has_rixiex 0
#define cpu_has_maar 0
#define cpu_has_4kex 1
#define cpu_has_3k_cache 0
#define cpu_has_4k_cache 1
@ -28,6 +34,8 @@
#define cpu_has_mdmx 0
#define cpu_has_mips3d 0
#define cpu_has_smartmips 0
#define cpu_has_rixi 0
#define cpu_has_mmips 0
#define cpu_has_vtag_icache 0
#define cpu_has_dc_aliases 0
#define cpu_has_ic_fills_f_dc 1
@ -50,4 +58,8 @@
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32
#define cpu_has_perf_cntr_intr_bit 0
#define cpu_has_vz 0
#define cpu_has_msa 0
#endif /* __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H */

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@ -57,6 +57,7 @@
#define cpu_has_vint 0
#define cpu_has_veic 0
#define cpu_hwrena_impl_bits 0xc0000000
#define cpu_has_wsbh 1
#define cpu_has_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON)

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@ -59,4 +59,6 @@
#define cpu_has_watch 1
#define cpu_has_local_ebase 0
#define cpu_has_wsbh IS_ENABLED(CONFIG_CPU_LOONGSON3)
#endif /* __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H */

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@ -224,40 +224,54 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
#define _CACHE_CACHABLE_NONCOHERENT 0
#define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED
#elif defined(CONFIG_CPU_SB1)
/* No penalty for being coherent on the SB1, so just
use it for "noncoherent" spaces, too. Shouldn't hurt. */
#define _CACHE_UNCACHED (2<<_CACHE_SHIFT)
#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT)
#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
#elif defined(CONFIG_CPU_LOONGSON3)
/* Using COHERENT flag for NONCOHERENT doesn't hurt. */
#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) /* LOONGSON */
#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */
#define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */
#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) /* LOONGSON */
#else
#elif defined(CONFIG_MACH_JZ4740)
#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) /* R4600 only */
#define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT) /* R4600 only */
#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) /* R4[0246]00 */
#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* R4[0246]00 */
#define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT) /* R4[04]00MC only */
#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) /* R4[04]00MC only */
#define _CACHE_CACHABLE_COHERENT (5<<_CACHE_SHIFT) /* MIPS32R2 CMP */
#define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT) /* R4[04]00MC only */
#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) /* R10000 only */
/* Ingenic uses the WA bit to achieve write-combine memory writes */
#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)
#endif
#ifndef _CACHE_CACHABLE_NO_WA
#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT)
#endif
#ifndef _CACHE_CACHABLE_WA
#define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT)
#endif
#ifndef _CACHE_UNCACHED
#define _CACHE_UNCACHED (2<<_CACHE_SHIFT)
#endif
#ifndef _CACHE_CACHABLE_NONCOHERENT
#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)
#endif
#ifndef _CACHE_CACHABLE_CE
#define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT)
#endif
#ifndef _CACHE_CACHABLE_COW
#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT)
#endif
#ifndef _CACHE_CACHABLE_CUW
#define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT)
#endif
#ifndef _CACHE_UNCACHED_ACCELERATED
#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
#endif
#define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (cpu_has_rixi ? 0 : _PAGE_READ))
#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)

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@ -366,6 +366,16 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot)
return __pgprot(prot);
}
static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
{
unsigned long prot = pgprot_val(_prot);
/* cpu_data[0].writecombine is already shifted by _CACHE_SHIFT */
prot = (prot & ~_CACHE_MASK) | cpu_data[0].writecombine;
return __pgprot(prot);
}
/*
* Conversion functions: convert a page and protection to a page entry,
* and a page entry and page directory to the page they refer to.

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@ -13,12 +13,16 @@
#define __SWAB_64_THRU_32__
#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
#if (defined(__mips_isa_rev) && (__mips_isa_rev >= 2)) || \
defined(_MIPS_ARCH_LOONGSON3A)
static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
{
__asm__(
" .set push \n"
" .set arch=mips32r2 \n"
" wsbh %0, %1 \n"
" .set pop \n"
: "=r" (x)
: "r" (x));
@ -29,8 +33,11 @@ static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
{
__asm__(
" .set push \n"
" .set arch=mips32r2 \n"
" wsbh %0, %1 \n"
" rotr %0, %0, 16 \n"
" .set pop \n"
: "=r" (x)
: "r" (x));
@ -46,8 +53,11 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
{
__asm__(
" dsbh %0, %1\n"
" dshd %0, %0"
" .set push \n"
" .set arch=mips64r2 \n"
" dsbh %0, %1 \n"
" dshd %0, %0 \n"
" .set pop \n"
: "=r" (x)
: "r" (x));
@ -55,5 +65,5 @@ static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
}
#define __arch_swab64 __arch_swab64
#endif /* __mips64 */
#endif /* MIPS R2 or newer */
#endif /* MIPS R2 or newer or Loongson 3A */
#endif /* _ASM_SWAB_H */

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@ -27,6 +27,7 @@
#include <asm/msa.h>
#include <asm/watch.h>
#include <asm/elf.h>
#include <asm/pgtable-bits.h>
#include <asm/spram.h>
#include <asm/uaccess.h>
@ -764,6 +765,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
break;
case PRID_REV_LOONGSON3A:
c->cputype = CPU_LOONGSON3;
c->writecombine = _CACHE_UNCACHED_ACCELERATED;
__cpu_name[cpu] = "ICT Loongson-3";
set_elf_platform(cpu, "loongson3a");
break;
@ -798,67 +800,83 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
{
c->writecombine = _CACHE_UNCACHED_ACCELERATED;
switch (c->processor_id & PRID_IMP_MASK) {
case PRID_IMP_4KC:
c->cputype = CPU_4KC;
c->writecombine = _CACHE_UNCACHED;
__cpu_name[cpu] = "MIPS 4Kc";
break;
case PRID_IMP_4KEC:
case PRID_IMP_4KECR2:
c->cputype = CPU_4KEC;
c->writecombine = _CACHE_UNCACHED;
__cpu_name[cpu] = "MIPS 4KEc";
break;
case PRID_IMP_4KSC:
case PRID_IMP_4KSD:
c->cputype = CPU_4KSC;
c->writecombine = _CACHE_UNCACHED;
__cpu_name[cpu] = "MIPS 4KSc";
break;
case PRID_IMP_5KC:
c->cputype = CPU_5KC;
c->writecombine = _CACHE_UNCACHED;
__cpu_name[cpu] = "MIPS 5Kc";
break;
case PRID_IMP_5KE:
c->cputype = CPU_5KE;
c->writecombine = _CACHE_UNCACHED;
__cpu_name[cpu] = "MIPS 5KE";
break;
case PRID_IMP_20KC:
c->cputype = CPU_20KC;
c->writecombine = _CACHE_UNCACHED;
__cpu_name[cpu] = "MIPS 20Kc";
break;
case PRID_IMP_24K:
c->cputype = CPU_24K;
c->writecombine = _CACHE_UNCACHED;
__cpu_name[cpu] = "MIPS 24Kc";
break;
case PRID_IMP_24KE:
c->cputype = CPU_24K;
c->writecombine = _CACHE_UNCACHED;
__cpu_name[cpu] = "MIPS 24KEc";
break;
case PRID_IMP_25KF:
c->cputype = CPU_25KF;
c->writecombine = _CACHE_UNCACHED;
__cpu_name[cpu] = "MIPS 25Kc";
break;
case PRID_IMP_34K:
c->cputype = CPU_34K;
c->writecombine = _CACHE_UNCACHED;
__cpu_name[cpu] = "MIPS 34Kc";
break;
case PRID_IMP_74K:
c->cputype = CPU_74K;
c->writecombine = _CACHE_UNCACHED;
__cpu_name[cpu] = "MIPS 74Kc";
break;
case PRID_IMP_M14KC:
c->cputype = CPU_M14KC;
c->writecombine = _CACHE_UNCACHED;
__cpu_name[cpu] = "MIPS M14Kc";
break;
case PRID_IMP_M14KEC:
c->cputype = CPU_M14KEC;
c->writecombine = _CACHE_UNCACHED;
__cpu_name[cpu] = "MIPS M14KEc";
break;
case PRID_IMP_1004K:
c->cputype = CPU_1004K;
c->writecombine = _CACHE_UNCACHED;
__cpu_name[cpu] = "MIPS 1004Kc";
break;
case PRID_IMP_1074K:
c->cputype = CPU_1074K;
c->writecombine = _CACHE_UNCACHED;
__cpu_name[cpu] = "MIPS 1074Kc";
break;
case PRID_IMP_INTERAPTIV_UP:
@ -932,6 +950,7 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
{
decode_configs(c);
c->writecombine = _CACHE_UNCACHED_ACCELERATED;
switch (c->processor_id & PRID_IMP_MASK) {
case PRID_IMP_SB1:
c->cputype = CPU_SB1;
@ -1063,6 +1082,7 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
switch (c->processor_id & PRID_IMP_MASK) {
case PRID_IMP_JZRISC:
c->cputype = CPU_JZRISC;
c->writecombine = _CACHE_UNCACHED_ACCELERATED;
__cpu_name[cpu] = "Ingenic JZRISC";
break;
default:
@ -1169,6 +1189,7 @@ void cpu_probe(void)
c->processor_id = PRID_IMP_UNKNOWN;
c->fpu_id = FPIR_IMP_NONE;
c->cputype = CPU_UNKNOWN;
c->writecombine = _CACHE_UNCACHED;
c->processor_id = read_c0_prid();
switch (c->processor_id & PRID_COMP_MASK) {

View File

@ -24,6 +24,8 @@
#include <linux/debugfs.h>
#include <linux/kexec.h>
#include <linux/sizes.h>
#include <linux/device.h>
#include <linux/dma-contiguous.h>
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
@ -476,6 +478,7 @@ static void __init bootmem_init(void)
* o bootmem_init()
* o sparse_init()
* o paging_init()
* o dma_continguous_reserve()
*
* At this stage the bootmem allocator is ready to use.
*
@ -609,6 +612,7 @@ static void __init request_crashkernel(struct resource *res)
static void __init arch_mem_init(char **cmdline_p)
{
struct memblock_region *reg;
extern void plat_mem_setup(void);
/* call board setup routine */
@ -675,6 +679,11 @@ static void __init arch_mem_init(char **cmdline_p)
sparse_init();
plat_swiotlb_setup();
paging_init();
dma_contiguous_reserve(PFN_PHYS(max_low_pfn));
/* Tell bootmem about cma reserved memblock section */
for_each_memblock(reserved, reg)
reserve_bootmem(reg->base, reg->size, BOOTMEM_DEFAULT);
}
static void __init resource_init(void)

View File

@ -30,6 +30,7 @@ choice
config DT_EASY50712
bool "Easy50712"
depends on SOC_XWAY
select BUILTIN_DTB
endchoice
config PCI_LANTIQ

View File

@ -6,8 +6,6 @@
obj-y := irq.o clk.o prom.o
obj-y += dts/
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
obj-$(CONFIG_SOC_TYPE_XWAY) += xway/

View File

@ -1 +0,0 @@
obj-$(CONFIG_DT_EASY50712) := easy50712.dtb.o

View File

@ -277,9 +277,12 @@ LEAF(csum_partial)
#endif
/* odd buffer alignment? */
#ifdef CONFIG_CPU_MIPSR2
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_LOONGSON3)
.set push
.set arch=mips32r2
wsbh v1, sum
movn sum, v1, t7
.set pop
#else
beqz t7, 1f /* odd buffer alignment? */
lui v1, 0x00ff
@ -726,9 +729,12 @@ LEAF(csum_partial)
addu sum, v1
#endif
#ifdef CONFIG_CPU_MIPSR2
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_LOONGSON3)
.set push
.set arch=mips32r2
wsbh v1, sum
movn sum, v1, odd
.set pop
#else
beqz odd, 1f /* odd buffer alignment? */
lui v1, 0x00ff

View File

@ -16,6 +16,7 @@
#include <linux/string.h>
#include <linux/gfp.h>
#include <linux/highmem.h>
#include <linux/dma-contiguous.h>
#include <asm/cache.h>
#include <asm/cpu-type.h>
@ -128,23 +129,30 @@ static void *mips_dma_alloc_coherent(struct device *dev, size_t size,
dma_addr_t * dma_handle, gfp_t gfp, struct dma_attrs *attrs)
{
void *ret;
struct page *page = NULL;
unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
if (dma_alloc_from_coherent(dev, size, dma_handle, &ret))
return ret;
gfp = massage_gfp_flags(dev, gfp);
ret = (void *) __get_free_pages(gfp, get_order(size));
if (IS_ENABLED(CONFIG_DMA_CMA) && !(gfp & GFP_ATOMIC))
page = dma_alloc_from_contiguous(dev,
count, get_order(size));
if (!page)
page = alloc_pages(gfp, get_order(size));
if (ret) {
memset(ret, 0, size);
*dma_handle = plat_map_dma_mem(dev, ret, size);
if (!page)
return NULL;
if (!plat_device_is_coherent(dev)) {
dma_cache_wback_inv((unsigned long) ret, size);
if (!hw_coherentio)
ret = UNCAC_ADDR(ret);
}
ret = page_address(page);
memset(ret, 0, size);
*dma_handle = plat_map_dma_mem(dev, ret, size);
if (!plat_device_is_coherent(dev)) {
dma_cache_wback_inv((unsigned long) ret, size);
if (!hw_coherentio)
ret = UNCAC_ADDR(ret);
}
return ret;
@ -164,6 +172,8 @@ static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr,
{
unsigned long addr = (unsigned long) vaddr;
int order = get_order(size);
unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
struct page *page = NULL;
if (dma_release_from_coherent(dev, order, vaddr))
return;
@ -173,7 +183,10 @@ static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr,
if (!plat_device_is_coherent(dev) && !hw_coherentio)
addr = CAC_ADDR(addr);
free_pages(addr, get_order(size));
page = virt_to_page((void *) addr);
if (!dma_release_from_contiguous(dev, page, count))
__free_pages(page, get_order(size));
}
static inline void __dma_sync_virtual(void *addr, size_t size,

View File

@ -19,9 +19,5 @@ obj-y += sead3-i2c-dev.o sead3-i2c.o \
obj-$(CONFIG_EARLY_PRINTK) += sead3-console.o
obj-$(CONFIG_USB_EHCI_HCD) += sead3-ehci.o
obj-$(CONFIG_OF) += sead3.dtb.o
CFLAGS_sead3-setup.o = -I$(src)/../../../scripts/dtc/libfdt
$(obj)/%.dtb: $(obj)/%.dts
$(call if_changed,dtc)

View File

@ -163,6 +163,19 @@ do { \
(ctx)->idx++; \
} while (0)
/*
* Similar to emit_instr but it must be used when we need to emit
* 32-bit or 64-bit instructions
*/
#define emit_long_instr(ctx, func, ...) \
do { \
if ((ctx)->target != NULL) { \
u32 *p = &(ctx)->target[ctx->idx]; \
UASM_i_##func(&p, ##__VA_ARGS__); \
} \
(ctx)->idx++; \
} while (0)
/* Determine if immediate is within the 16-bit signed range */
static inline bool is_range16(s32 imm)
{
@ -218,13 +231,6 @@ static inline void emit_ori(unsigned int dst, unsigned src, u32 imm,
}
}
static inline void emit_daddu(unsigned int dst, unsigned int src1,
unsigned int src2, struct jit_ctx *ctx)
{
emit_instr(ctx, daddu, dst, src1, src2);
}
static inline void emit_daddiu(unsigned int dst, unsigned int src,
int imm, struct jit_ctx *ctx)
{
@ -283,11 +289,7 @@ static inline void emit_xori(ptr dst, ptr src, u32 imm, struct jit_ctx *ctx)
static inline void emit_stack_offset(int offset, struct jit_ctx *ctx)
{
if (config_enabled(CONFIG_64BIT))
emit_instr(ctx, daddiu, r_sp, r_sp, offset);
else
emit_instr(ctx, addiu, r_sp, r_sp, offset);
emit_long_instr(ctx, ADDIU, r_sp, r_sp, offset);
}
static inline void emit_subu(unsigned int dst, unsigned int src1,
@ -365,10 +367,7 @@ static inline void emit_store_stack_reg(ptr reg, ptr base,
unsigned int offset,
struct jit_ctx *ctx)
{
if (config_enabled(CONFIG_64BIT))
emit_instr(ctx, sd, reg, offset, base);
else
emit_instr(ctx, sw, reg, offset, base);
emit_long_instr(ctx, SW, reg, offset, base);
}
static inline void emit_store(ptr reg, ptr base, unsigned int offset,
@ -381,10 +380,7 @@ static inline void emit_load_stack_reg(ptr reg, ptr base,
unsigned int offset,
struct jit_ctx *ctx)
{
if (config_enabled(CONFIG_64BIT))
emit_instr(ctx, ld, reg, offset, base);
else
emit_instr(ctx, lw, reg, offset, base);
emit_long_instr(ctx, LW, reg, offset, base);
}
static inline void emit_load(unsigned int reg, unsigned int base,
@ -458,10 +454,7 @@ static inline void emit_load_ptr(unsigned int dst, unsigned int src,
int imm, struct jit_ctx *ctx)
{
/* src contains the base addr of the 32/64-pointer */
if (config_enabled(CONFIG_64BIT))
emit_instr(ctx, ld, dst, imm, src);
else
emit_instr(ctx, lw, dst, imm, src);
emit_long_instr(ctx, LW, dst, imm, src);
}
/* load a function pointer to register */
@ -483,10 +476,7 @@ static inline void emit_load_func(unsigned int reg, ptr imm,
/* Move to real MIPS register */
static inline void emit_reg_move(ptr dst, ptr src, struct jit_ctx *ctx)
{
if (config_enabled(CONFIG_64BIT))
emit_daddu(dst, src, r_zero, ctx);
else
emit_addu(dst, src, r_zero, ctx);
emit_long_instr(ctx, ADDU, dst, src, r_zero);
}
/* Move to JIT (32-bit) register */
@ -623,10 +613,7 @@ static void save_bpf_jit_regs(struct jit_ctx *ctx, unsigned offset)
if (ctx->flags & SEEN_MEM) {
if (real_off % (RSIZE * 2))
real_off += RSIZE;
if (config_enabled(CONFIG_64BIT))
emit_daddiu(r_M, r_sp, real_off, ctx);
else
emit_addiu(r_M, r_sp, real_off, ctx);
emit_long_instr(ctx, ADDIU, r_M, r_sp, real_off);
}
}
@ -1241,7 +1228,7 @@ jmp_cmp:
emit_half_load(r_A, r_skb, off, ctx);
#ifdef CONFIG_CPU_LITTLE_ENDIAN
/* This needs little endian fixup */
if (cpu_has_mips_r2) {
if (cpu_has_wsbh) {
/* R2 and later have the wsbh instruction */
emit_wsbh(r_A, r_A, ctx);
} else {

View File

@ -4,6 +4,7 @@ if NLM_XLP_BOARD
config DT_XLP_EVP
bool "Built-in device tree for XLP EVP boards"
default y
select BUILTIN_DTB
help
Add an FDT blob for XLP EVP boards into the kernel.
This DTB will be used if the firmware does not pass in a DTB
@ -13,6 +14,7 @@ config DT_XLP_EVP
config DT_XLP_SVP
bool "Built-in device tree for XLP SVP boards"
default y
select BUILTIN_DTB
help
Add an FDT blob for XLP VP boards into the kernel.
This DTB will be used if the firmware does not pass in a DTB
@ -22,6 +24,7 @@ config DT_XLP_SVP
config DT_XLP_FVP
bool "Built-in device tree for XLP FVP boards"
default y
select BUILTIN_DTB
help
Add an FDT blob for XLP FVP board into the kernel.
This DTB will be used if the firmware does not pass in a DTB
@ -31,6 +34,7 @@ config DT_XLP_FVP
config DT_XLP_GVP
bool "Built-in device tree for XLP GVP boards"
default y
select BUILTIN_DTB
help
Add an FDT blob for XLP GVP board into the kernel.
This DTB will be used if the firmware does not pass in a DTB

View File

@ -1,4 +1,3 @@
obj-$(CONFIG_NLM_COMMON) += common/
obj-$(CONFIG_CPU_XLR) += xlr/
obj-$(CONFIG_CPU_XLP) += xlp/
obj-$(CONFIG_CPU_XLP) += dts/

View File

@ -1,4 +0,0 @@
obj-$(CONFIG_DT_XLP_EVP) := xlp_evp.dtb.o
obj-$(CONFIG_DT_XLP_SVP) += xlp_svp.dtb.o
obj-$(CONFIG_DT_XLP_FVP) += xlp_fvp.dtb.o
obj-$(CONFIG_DT_XLP_GVP) += xlp_gvp.dtb.o

View File

@ -42,18 +42,22 @@ choice
config DTB_RT2880_EVAL
bool "RT2880 eval kit"
depends on SOC_RT288X
select BUILTIN_DTB
config DTB_RT305X_EVAL
bool "RT305x eval kit"
depends on SOC_RT305X
select BUILTIN_DTB
config DTB_RT3883_EVAL
bool "RT3883 eval kit"
depends on SOC_RT3883
select BUILTIN_DTB
config DTB_MT7620A_EVAL
bool "MT7620A eval kit"
depends on SOC_MT7620
select BUILTIN_DTB
endchoice

View File

@ -16,5 +16,3 @@ obj-$(CONFIG_SOC_RT3883) += rt3883.o
obj-$(CONFIG_SOC_MT7620) += mt7620.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
obj-y += dts/

View File

@ -1,4 +0,0 @@
obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_eval.dtb.o
obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
obj-$(CONFIG_DTB_RT3883_EVAL) := rt3883_eval.dtb.o
obj-$(CONFIG_DTB_MT7620A_EVAL) := mt7620a_eval.dtb.o

View File

@ -58,7 +58,7 @@ static irqreturn_t rt_timer_irq(int irq, void *_rt)
static int rt_timer_request(struct rt_timer *rt)
{
int err = request_irq(rt->irq, rt_timer_irq, IRQF_DISABLED,
int err = request_irq(rt->irq, rt_timer_irq, 0,
dev_name(rt->dev), rt);
if (err) {
dev_err(rt->dev, "failed to request irq\n");

View File

@ -6,6 +6,7 @@ genhdr-y += unistd_x32.h
generic-y += clkdev.h
generic-y += cputime.h
generic-y += dma-contiguous.h
generic-y += early_ioremap.h
generic-y += mcs_spinlock.h
generic-y += scatterlist.h

View File

@ -1,7 +1,5 @@
#ifndef ASMX86_DMA_CONTIGUOUS_H
#define ASMX86_DMA_CONTIGUOUS_H
#ifdef __KERNEL__
#ifndef _ASM_GENERIC_DMA_CONTIGUOUS_H
#define _ASM_GENERIC_DMA_CONTIGUOUS_H
#include <linux/types.h>
@ -9,4 +7,3 @@ static inline void
dma_contiguous_early_fixup(phys_addr_t base, unsigned long size) { }
#endif
#endif