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powerpc/fsl-pci: Limit ZONE_DMA32 to 2GiB on 64-bit platforms

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FSL PCI cannot directly address the whole lower 4 GiB due to
conflicts with PCICSRBAR and outbound windows.  By the time
max_direct_dma_addr is set to the precise limit, it will be too late to
alter the zone limits, but we should always have at least 2 GiB mapped
(unless RAM is smaller than that).

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Shaohui Xie <Shaohui.Xie@freescale.com>
This commit is contained in:
Scott Wood 2014-08-08 18:40:45 -05:00
parent cf5621032f
commit 84f44cc56c
2 changed files with 21 additions and 0 deletions
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11
arch/powerpc/platforms/85xx/corenet_generic.c
View File

@ -20,6 +20,7 @@
#include <asm/time.h> #include <asm/time.h>
#include <asm/machdep.h> #include <asm/machdep.h>
#include <asm/pci-bridge.h> #include <asm/pci-bridge.h>
#include <asm/pgtable.h>
#include <asm/ppc-pci.h> #include <asm/ppc-pci.h>
#include <mm/mmu_decl.h> #include <mm/mmu_decl.h>
#include <asm/prom.h> #include <asm/prom.h>
@ -67,6 +68,16 @@ void __init corenet_gen_setup_arch(void)
swiotlb_detect_4g(); swiotlb_detect_4g();
#if defined(CONFIG_FSL_PCI) && defined(CONFIG_ZONE_DMA32)
/*
* Inbound windows don't cover the full lower 4 GiB
* due to conflicts with PCICSRBAR and outbound windows,
* so limit the DMA32 zone to 2 GiB, to allow consistent
* allocations to succeed.
*/
limit_zone_pfn(ZONE_DMA32, 1UL << (31 - PAGE_SHIFT));
#endif
pr_info("%s board\n", ppc_md.name); pr_info("%s board\n", ppc_md.name);
mpc85xx_qe_init(); mpc85xx_qe_init();

10
arch/powerpc/platforms/85xx/qemu_e500.c
View File

@ -18,6 +18,7 @@
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/of_fdt.h> #include <linux/of_fdt.h>
#include <asm/machdep.h> #include <asm/machdep.h>
#include <asm/pgtable.h>
#include <asm/time.h> #include <asm/time.h>
#include <asm/udbg.h> #include <asm/udbg.h>
#include <asm/mpic.h> #include <asm/mpic.h>
@ -44,6 +45,15 @@ static void __init qemu_e500_setup_arch(void)
fsl_pci_assign_primary(); fsl_pci_assign_primary();
swiotlb_detect_4g(); swiotlb_detect_4g();
#if defined(CONFIG_FSL_PCI) && defined(CONFIG_ZONE_DMA32)
/*
* Inbound windows don't cover the full lower 4 GiB
* due to conflicts with PCICSRBAR and outbound windows,
* so limit the DMA32 zone to 2 GiB, to allow consistent
* allocations to succeed.
*/
limit_zone_pfn(ZONE_DMA32, 1UL << (31 - PAGE_SHIFT));
#endif
mpc85xx_smp_init(); mpc85xx_smp_init();
} }