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KVM: X86/MMU: Fix shadowing 5-level NPT for 4-level NPT L1 guest
When shadowing 5-level NPT for 4-level NPT L1 guest, the root_sp is allocated with role.level = 5 and the guest pagetable's root gfn. And root_sp->spt[0] is also allocated with the same gfn and the same role except role.level = 4. Luckily that they are different shadow pages, but only root_sp->spt[0] is the real translation of the guest pagetable. Here comes a problem: If the guest switches from gCR4_LA57=0 to gCR4_LA57=1 (or vice verse) and uses the same gfn as the root page for nested NPT before and after switching gCR4_LA57. The host (hCR4_LA57=1) might use the same root_sp for the guest even the guest switches gCR4_LA57. The guest will see unexpected page mapped and L2 may exploit the bug and hurt L1. It is lucky that the problem can't hurt L0. And three special cases need to be handled: The root_sp should be like role.direct=1 sometimes: its contents are not backed by gptes, root_sp->gfns is meaningless. (For a normal high level sp in shadow paging, sp->gfns is often unused and kept zero, but it could be relevant and meaningful if sp->gfns is used because they are backed by concrete gptes.) For such root_sp in the case, root_sp is just a portal to contribute root_sp->spt[0], and root_sp->gfns should not be used and root_sp->spt[0] should not be dropped if gpte[0] of the guest root pagetable is changed. Such root_sp should not be accounted too. So add role.passthrough to distinguish the shadow pages in the hash when gCR4_LA57 is toggled and fix above special cases by using it in kvm_mmu_page_{get|set}_gfn() and sp_has_gptes(). Signed-off-by: Lai Jiangshan <jiangshan.ljs@antgroup.com> Message-Id: <20220420131204.2850-3-jiangshanlai@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -202,6 +202,10 @@ Shadow pages contain the following information:
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Is 1 if the MMU instance cannot use A/D bits. EPT did not have A/D
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bits before Haswell; shadow EPT page tables also cannot use A/D bits
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if the L1 hypervisor does not enable them.
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role.passthrough:
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The page is not backed by a guest page table, but its first entry
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points to one. This is set if NPT uses 5-level page tables (host
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CR4.LA57=1) and is shadowing L1's 4-level NPT (L1 CR4.LA57=1).
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gfn:
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Either the guest page table containing the translations shadowed by this
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page, or the base page frame for linear translations. See role.direct.
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@ -285,7 +285,7 @@ struct kvm_kernel_irq_routing_entry;
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* minimize the size of kvm_memory_slot.arch.gfn_track, i.e. allows allocating
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* 2 bytes per gfn instead of 4 bytes per gfn.
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*
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* Indirect upper-level shadow pages are tracked for write-protection via
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* Upper-level shadow pages having gptes are tracked for write-protection via
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* gfn_track. As above, gfn_track is a 16 bit counter, so KVM must not create
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* more than 2^16-1 upper-level shadow pages at a single gfn, otherwise
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* gfn_track will overflow and explosions will ensure.
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@ -331,7 +331,8 @@ union kvm_mmu_page_role {
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unsigned smap_andnot_wp:1;
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unsigned ad_disabled:1;
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unsigned guest_mode:1;
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unsigned :6;
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unsigned passthrough:1;
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unsigned :5;
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/*
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* This is left at the top of the word so that
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@ -734,6 +734,9 @@ static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
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static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
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{
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if (sp->role.passthrough)
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return sp->gfn;
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if (!sp->role.direct)
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return sp->gfns[index];
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@ -742,6 +745,11 @@ static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
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static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
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{
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if (sp->role.passthrough) {
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WARN_ON_ONCE(gfn != sp->gfn);
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return;
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}
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if (!sp->role.direct) {
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sp->gfns[index] = gfn;
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return;
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@ -1858,6 +1866,9 @@ static bool sp_has_gptes(struct kvm_mmu_page *sp)
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if (sp->role.direct)
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return false;
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if (sp->role.passthrough)
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return false;
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return true;
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}
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@ -2054,6 +2065,8 @@ static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
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quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
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role.quadrant = quadrant;
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}
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if (level <= vcpu->arch.mmu->cpu_role.base.level)
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role.passthrough = 0;
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sp_list = &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)];
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for_each_valid_sp(vcpu->kvm, sp, sp_list) {
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@ -4907,6 +4920,9 @@ void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, unsigned long cr0,
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root_role = cpu_role.base;
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root_role.level = kvm_mmu_get_tdp_level(vcpu);
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if (root_role.level == PT64_ROOT_5LEVEL &&
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cpu_role.base.level == PT64_ROOT_4LEVEL)
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root_role.passthrough = 1;
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shadow_mmu_init_context(vcpu, context, cpu_role, root_role);
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kvm_mmu_new_pgd(vcpu, nested_cr3);
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@ -1007,6 +1007,7 @@ static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
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.level = 0xf,
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.access = 0x7,
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.quadrant = 0x3,
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.passthrough = 0x1,
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};
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/*
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