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x86/cpu, kvm: Add support for CPUID_80000021_EAX
Add support for CPUID leaf 80000021, EAX. The majority of the features will be used in the kernel and thus a separate leaf is appropriate. Include KVM's reverse_cpuid entry because features are used by VM guests, too. [ bp: Massage commit message. ] Signed-off-by: Kim Phillips <kim.phillips@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Acked-by: Sean Christopherson <seanjc@google.com> Link: https://lore.kernel.org/r/20230124163319.2277355-2-kim.phillips@amd.com
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@ -32,6 +32,7 @@ enum cpuid_leafs
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CPUID_8000_0007_EBX,
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CPUID_7_EDX,
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CPUID_8000_001F_EAX,
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CPUID_8000_0021_EAX,
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};
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#define X86_CAP_FMT_NUM "%d:%d"
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@ -94,8 +95,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
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CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 17, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 18, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 19, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 20, feature_bit) || \
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REQUIRED_MASK_CHECK || \
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BUILD_BUG_ON_ZERO(NCAPINTS != 20))
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BUILD_BUG_ON_ZERO(NCAPINTS != 21))
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#define DISABLED_MASK_BIT_SET(feature_bit) \
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( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 0, feature_bit) || \
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@ -118,8 +120,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
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CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 17, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 18, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 19, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 20, feature_bit) || \
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DISABLED_MASK_CHECK || \
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BUILD_BUG_ON_ZERO(NCAPINTS != 20))
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BUILD_BUG_ON_ZERO(NCAPINTS != 21))
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#define cpu_has(c, bit) \
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(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \
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@ -13,7 +13,7 @@
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/*
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* Defines x86 CPU feature bits
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*/
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#define NCAPINTS 20 /* N 32-bit words worth of info */
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#define NCAPINTS 21 /* N 32-bit words worth of info */
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#define NBUGINTS 1 /* N 32-bit bug flags */
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/*
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@ -124,6 +124,7 @@
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#define DISABLED_MASK17 0
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#define DISABLED_MASK18 0
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#define DISABLED_MASK19 0
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#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 20)
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#define DISABLED_MASK20 0
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#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 21)
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#endif /* _ASM_X86_DISABLED_FEATURES_H */
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@ -98,6 +98,7 @@
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#define REQUIRED_MASK17 0
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#define REQUIRED_MASK18 0
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#define REQUIRED_MASK19 0
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#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 20)
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#define REQUIRED_MASK20 0
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#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 21)
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#endif /* _ASM_X86_REQUIRED_FEATURES_H */
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@ -1093,6 +1093,9 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
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if (c->extended_cpuid_level >= 0x8000001f)
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c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f);
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if (c->extended_cpuid_level >= 0x80000021)
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c->x86_capability[CPUID_8000_0021_EAX] = cpuid_eax(0x80000021);
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init_scattered_cpuid_features(c);
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init_speculation_control(c);
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@ -68,6 +68,7 @@ static const struct cpuid_reg reverse_cpuid[] = {
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[CPUID_12_EAX] = {0x00000012, 0, CPUID_EAX},
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[CPUID_8000_001F_EAX] = {0x8000001f, 0, CPUID_EAX},
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[CPUID_7_1_EDX] = { 7, 1, CPUID_EDX},
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[CPUID_8000_0021_EAX] = {0x80000021, 0, CPUID_EAX},
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};
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/*
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