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rtw88: pci: use macros to access PCI DBI/MDIO registers
Add some register and bit macros to access DBI/MDIO register. This should not change the logic. Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
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@ -1060,14 +1060,15 @@ static void rtw_pci_io_unmapping(struct rtw_dev *rtwdev,
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static void rtw_dbi_write8(struct rtw_dev *rtwdev, u16 addr, u8 data)
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{
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u16 write_addr;
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u16 remainder = addr & 0x3;
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u16 remainder = addr & ~(BITS_DBI_WREN | BITS_DBI_ADDR_MASK);
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u8 flag;
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u8 cnt = 20;
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u8 cnt = RTW_PCI_WR_RETRY_CNT;
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write_addr = ((addr & 0x0ffc) | (BIT(0) << (remainder + 12)));
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write_addr = addr & BITS_DBI_ADDR_MASK;
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write_addr |= u16_encode_bits(BIT(remainder), BITS_DBI_WREN);
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rtw_write8(rtwdev, REG_DBI_WDATA_V1 + remainder, data);
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rtw_write16(rtwdev, REG_DBI_FLAG_V1, write_addr);
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rtw_write8(rtwdev, REG_DBI_FLAG_V1 + 2, 0x01);
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rtw_write8(rtwdev, REG_DBI_FLAG_V1 + 2, BIT_DBI_WFLAG >> 16);
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flag = rtw_read8(rtwdev, REG_DBI_FLAG_V1 + 2);
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while (flag && (cnt != 0)) {
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@ -1083,19 +1084,17 @@ static void rtw_mdio_write(struct rtw_dev *rtwdev, u8 addr, u16 data, bool g1)
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{
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u8 page;
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u8 wflag;
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u8 cnt;
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u8 cnt = RTW_PCI_WR_RETRY_CNT;
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rtw_write16(rtwdev, REG_MDIO_V1, data);
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page = addr < 0x20 ? 0 : 1;
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page += g1 ? 0 : 2;
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rtw_write8(rtwdev, REG_PCIE_MIX_CFG, addr & 0x1f);
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page = addr < RTW_PCI_MDIO_PG_SZ ? 0 : 1;
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page += g1 ? RTW_PCI_MDIO_PG_OFFS_G1 : RTW_PCI_MDIO_PG_OFFS_G2;
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rtw_write8(rtwdev, REG_PCIE_MIX_CFG, addr & BITS_MDIO_ADDR_MASK);
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rtw_write8(rtwdev, REG_PCIE_MIX_CFG + 3, page);
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rtw_write32_mask(rtwdev, REG_PCIE_MIX_CFG, BIT_MDIO_WFLAG_V1, 1);
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wflag = rtw_read32_mask(rtwdev, REG_PCIE_MIX_CFG, BIT_MDIO_WFLAG_V1);
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cnt = 20;
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wflag = rtw_read32_mask(rtwdev, REG_PCIE_MIX_CFG, BIT_MDIO_WFLAG_V1);
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while (wflag && (cnt != 0)) {
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udelay(10);
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wflag = rtw_read32_mask(rtwdev, REG_PCIE_MIX_CFG,
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@ -21,9 +21,19 @@
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#define BIT_RX_TAG_EN BIT(15)
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#define REG_DBI_WDATA_V1 0x03E8
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#define REG_DBI_FLAG_V1 0x03F0
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#define BIT_DBI_RFLAG BIT(17)
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#define BIT_DBI_WFLAG BIT(16)
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#define BITS_DBI_WREN GENMASK(15, 12)
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#define BITS_DBI_ADDR_MASK GENMASK(11, 2)
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#define REG_MDIO_V1 0x03F4
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#define REG_PCIE_MIX_CFG 0x03F8
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#define BITS_MDIO_ADDR_MASK GENMASK(4, 0)
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#define BIT_MDIO_WFLAG_V1 BIT(5)
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#define RTW_PCI_MDIO_PG_SZ BIT(5)
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#define RTW_PCI_MDIO_PG_OFFS_G1 0
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#define RTW_PCI_MDIO_PG_OFFS_G2 2
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#define RTW_PCI_WR_RETRY_CNT 20
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#define BIT_PCI_BCNQ_FLAG BIT(4)
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#define RTK_PCI_TXBD_DESA_BCNQ 0x308
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