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scsi: be2iscsi: switch to pci_alloc_irq_vectors
And get automatic MSI-X affinity for free. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Jitendra Bhivare <jitendra.bhivare@broadcom.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Christoph Hellwig
Martin K. Petersen
parent
dbd34a61c3
commit
831488669a
@ -796,12 +796,12 @@ static int beiscsi_init_irqs(struct beiscsi_hba *phba)
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struct pci_dev *pcidev = phba->pcidev;
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struct hwi_controller *phwi_ctrlr;
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struct hwi_context_memory *phwi_context;
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int ret, msix_vec, i, j;
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int ret, i, j;
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phwi_ctrlr = phba->phwi_ctrlr;
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phwi_context = phwi_ctrlr->phwi_ctxt;
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if (phba->msix_enabled) {
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if (pcidev->msix_enabled) {
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for (i = 0; i < phba->num_cpus; i++) {
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phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME,
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GFP_KERNEL);
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@ -812,9 +812,8 @@ static int beiscsi_init_irqs(struct beiscsi_hba *phba)
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sprintf(phba->msi_name[i], "beiscsi_%02x_%02x",
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phba->shost->host_no, i);
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msix_vec = phba->msix_entries[i].vector;
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ret = request_irq(msix_vec, be_isr_msix, 0,
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phba->msi_name[i],
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ret = request_irq(pci_irq_vector(pcidev, i),
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be_isr_msix, 0, phba->msi_name[i],
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&phwi_context->be_eq[i]);
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if (ret) {
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beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
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@ -832,9 +831,8 @@ static int beiscsi_init_irqs(struct beiscsi_hba *phba)
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}
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sprintf(phba->msi_name[i], "beiscsi_mcc_%02x",
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phba->shost->host_no);
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msix_vec = phba->msix_entries[i].vector;
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ret = request_irq(msix_vec, be_isr_mcc, 0, phba->msi_name[i],
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&phwi_context->be_eq[i]);
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ret = request_irq(pci_irq_vector(pcidev, i), be_isr_mcc, 0,
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phba->msi_name[i], &phwi_context->be_eq[i]);
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if (ret) {
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beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT ,
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"BM_%d : beiscsi_init_irqs-"
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@ -856,9 +854,8 @@ static int beiscsi_init_irqs(struct beiscsi_hba *phba)
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return 0;
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free_msix_irqs:
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for (j = i - 1; j >= 0; j--) {
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free_irq(pci_irq_vector(pcidev, i), &phwi_context->be_eq[j]);
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kfree(phba->msi_name[j]);
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msix_vec = phba->msix_entries[j].vector;
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free_irq(msix_vec, &phwi_context->be_eq[j]);
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}
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return ret;
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}
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@ -3000,7 +2997,7 @@ static int beiscsi_create_eqs(struct beiscsi_hba *phba,
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num_eq_pages = PAGES_REQUIRED(phba->params.num_eq_entries * \
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sizeof(struct be_eq_entry));
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if (phba->msix_enabled)
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if (phba->pcidev->msix_enabled)
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eq_for_mcc = 1;
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else
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eq_for_mcc = 0;
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@ -3510,7 +3507,7 @@ static int be_mcc_queues_create(struct beiscsi_hba *phba,
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sizeof(struct be_mcc_compl)))
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goto err;
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/* Ask BE to create MCC compl queue; */
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if (phba->msix_enabled) {
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if (phba->pcidev->msix_enabled) {
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if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq
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[phba->num_cpus].q, false, true, 0))
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goto mcc_cq_free;
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@ -3541,42 +3538,35 @@ err:
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return -ENOMEM;
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}
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/**
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* find_num_cpus()- Get the CPU online count
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* @phba: ptr to priv structure
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*
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* CPU count is used for creating EQ.
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**/
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static void find_num_cpus(struct beiscsi_hba *phba)
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static void be2iscsi_enable_msix(struct beiscsi_hba *phba)
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{
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int num_cpus = 0;
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num_cpus = num_online_cpus();
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int nvec = 1;
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switch (phba->generation) {
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case BE_GEN2:
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case BE_GEN3:
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phba->num_cpus = (num_cpus > BEISCSI_MAX_NUM_CPUS) ?
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BEISCSI_MAX_NUM_CPUS : num_cpus;
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nvec = BEISCSI_MAX_NUM_CPUS + 1;
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break;
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case BE_GEN4:
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/*
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* If eqid_count == 1 fall back to
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* INTX mechanism
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**/
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if (phba->fw_config.eqid_count == 1) {
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enable_msix = 0;
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phba->num_cpus = 1;
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return;
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}
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phba->num_cpus =
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(num_cpus > (phba->fw_config.eqid_count - 1)) ?
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(phba->fw_config.eqid_count - 1) : num_cpus;
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nvec = phba->fw_config.eqid_count;
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break;
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default:
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phba->num_cpus = 1;
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nvec = 2;
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break;
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}
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/* if eqid_count == 1 fall back to INTX */
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if (enable_msix && nvec > 1) {
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const struct irq_affinity desc = { .post_vectors = 1 };
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if (pci_alloc_irq_vectors_affinity(phba->pcidev, 2, nvec,
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PCI_IRQ_MSIX | PCI_IRQ_AFFINITY, &desc) < 0) {
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phba->num_cpus = nvec - 1;
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return;
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}
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}
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phba->num_cpus = 1;
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}
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static void hwi_purge_eq(struct beiscsi_hba *phba)
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@ -3593,7 +3583,7 @@ static void hwi_purge_eq(struct beiscsi_hba *phba)
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phwi_ctrlr = phba->phwi_ctrlr;
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phwi_context = phwi_ctrlr->phwi_ctxt;
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if (phba->msix_enabled)
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if (phba->pcidev->msix_enabled)
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eq_msix = 1;
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else
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eq_msix = 0;
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@ -3671,7 +3661,7 @@ static void hwi_cleanup_port(struct beiscsi_hba *phba)
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}
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be_mcc_queues_destroy(phba);
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if (phba->msix_enabled)
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if (phba->pcidev->msix_enabled)
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eq_for_mcc = 1;
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else
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eq_for_mcc = 0;
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@ -4117,7 +4107,7 @@ static void hwi_enable_intr(struct beiscsi_hba *phba)
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iowrite32(reg, addr);
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}
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if (!phba->msix_enabled) {
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if (!phba->pcidev->msix_enabled) {
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eq = &phwi_context->be_eq[0].q;
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beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
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"BM_%d : eq->id=%d\n", eq->id);
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@ -5240,19 +5230,6 @@ static void beiscsi_eqd_update_work(struct work_struct *work)
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msecs_to_jiffies(BEISCSI_EQD_UPDATE_INTERVAL));
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}
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static void beiscsi_msix_enable(struct beiscsi_hba *phba)
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{
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int i, status;
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for (i = 0; i <= phba->num_cpus; i++)
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phba->msix_entries[i].entry = i;
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status = pci_enable_msix_range(phba->pcidev, phba->msix_entries,
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phba->num_cpus + 1, phba->num_cpus + 1);
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if (status > 0)
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phba->msix_enabled = true;
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}
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static void beiscsi_hw_tpe_check(unsigned long ptr)
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{
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struct beiscsi_hba *phba;
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@ -5320,15 +5297,7 @@ static int beiscsi_enable_port(struct beiscsi_hba *phba)
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if (ret)
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return ret;
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if (enable_msix)
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find_num_cpus(phba);
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else
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phba->num_cpus = 1;
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if (enable_msix) {
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beiscsi_msix_enable(phba);
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if (!phba->msix_enabled)
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phba->num_cpus = 1;
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}
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be2iscsi_enable_msix(phba);
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beiscsi_get_params(phba);
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/* Re-enable UER. If different TPE occurs then it is recoverable. */
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@ -5357,7 +5326,7 @@ static int beiscsi_enable_port(struct beiscsi_hba *phba)
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irq_poll_init(&pbe_eq->iopoll, be_iopoll_budget, be_iopoll);
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}
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i = (phba->msix_enabled) ? i : 0;
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i = (phba->pcidev->msix_enabled) ? i : 0;
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/* Work item for MCC handling */
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pbe_eq = &phwi_context->be_eq[i];
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INIT_WORK(&pbe_eq->mcc_work, beiscsi_mcc_work);
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@ -5395,9 +5364,7 @@ cleanup_port:
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hwi_cleanup_port(phba);
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disable_msix:
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if (phba->msix_enabled)
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pci_disable_msix(phba->pcidev);
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pci_free_irq_vectors(phba->pcidev);
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return ret;
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}
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@ -5414,7 +5381,7 @@ static void beiscsi_disable_port(struct beiscsi_hba *phba, int unload)
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struct hwi_context_memory *phwi_context;
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struct hwi_controller *phwi_ctrlr;
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struct be_eq_obj *pbe_eq;
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unsigned int i, msix_vec;
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unsigned int i;
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if (!test_and_clear_bit(BEISCSI_HBA_ONLINE, &phba->state))
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return;
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@ -5422,16 +5389,16 @@ static void beiscsi_disable_port(struct beiscsi_hba *phba, int unload)
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phwi_ctrlr = phba->phwi_ctrlr;
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phwi_context = phwi_ctrlr->phwi_ctxt;
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hwi_disable_intr(phba);
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if (phba->msix_enabled) {
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if (phba->pcidev->msix_enabled) {
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for (i = 0; i <= phba->num_cpus; i++) {
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msix_vec = phba->msix_entries[i].vector;
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free_irq(msix_vec, &phwi_context->be_eq[i]);
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free_irq(pci_irq_vector(phba->pcidev, i),
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&phwi_context->be_eq[i]);
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kfree(phba->msi_name[i]);
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}
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} else
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if (phba->pcidev->irq)
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free_irq(phba->pcidev->irq, phba);
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pci_disable_msix(phba->pcidev);
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pci_free_irq_vectors(phba->pcidev);
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for (i = 0; i < phba->num_cpus; i++) {
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pbe_eq = &phwi_context->be_eq[i];
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@ -5641,21 +5608,12 @@ static int beiscsi_dev_probe(struct pci_dev *pcidev,
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beiscsi_get_params(phba);
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beiscsi_set_uer_feature(phba);
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if (enable_msix)
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find_num_cpus(phba);
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else
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phba->num_cpus = 1;
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be2iscsi_enable_msix(phba);
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beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
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"BM_%d : num_cpus = %d\n",
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phba->num_cpus);
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if (enable_msix) {
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beiscsi_msix_enable(phba);
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if (!phba->msix_enabled)
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phba->num_cpus = 1;
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}
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phba->shost->max_id = phba->params.cxns_per_ctrl;
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phba->shost->can_queue = phba->params.ios_per_ctrl;
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ret = beiscsi_get_memory(phba);
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@ -5705,7 +5663,7 @@ static int beiscsi_dev_probe(struct pci_dev *pcidev,
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irq_poll_init(&pbe_eq->iopoll, be_iopoll_budget, be_iopoll);
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}
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i = (phba->msix_enabled) ? i : 0;
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i = (phba->pcidev->msix_enabled) ? i : 0;
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/* Work item for MCC handling */
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pbe_eq = &phwi_context->be_eq[i];
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INIT_WORK(&pbe_eq->mcc_work, beiscsi_mcc_work);
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@ -5776,8 +5734,7 @@ free_port:
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phba->ctrl.mbox_mem_alloced.dma);
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beiscsi_unmap_pci_function(phba);
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hba_free:
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if (phba->msix_enabled)
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pci_disable_msix(phba->pcidev);
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pci_disable_msix(phba->pcidev);
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pci_dev_put(phba->pcidev);
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iscsi_host_free(phba->shost);
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pci_set_drvdata(pcidev, NULL);
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@ -317,9 +317,7 @@ struct beiscsi_hba {
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struct pci_dev *pcidev;
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unsigned int num_cpus;
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unsigned int nxt_cqid;
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struct msix_entry msix_entries[MAX_CPUS];
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char *msi_name[MAX_CPUS];
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bool msix_enabled;
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struct be_mem_descriptor *init_mem;
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unsigned short io_sgl_alloc_index;
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