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[ARM] 3587/1: AT91RM9200 hardware headers
Patch from Andrew Victor These headers define the registers and bits for the SPI (Serial Peripheral Interface), SSC (Synchronous Serial), TC (Timer/Counter) and UDP (USB Device) peripherals integrated in the AT91RM9200 processor. (They will probably also be usable for the AT91SAM9 series of SoC processors) Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Andrew Victor
Russell King
parent
7238d7ee82
commit
82c583e3ae
81
include/asm-arm/arch-at91rm9200/at91rm9200_spi.h
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81
include/asm-arm/arch-at91rm9200/at91rm9200_spi.h
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/*
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* include/asm-arm/arch-at91rm9200/at91rm9200_spi.h
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*
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* Copyright (C) 2005 Ivan Kokshaysky
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* Copyright (C) SAN People
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*
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* Serial Peripheral Interface (SPI) registers.
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* Based on AT91RM9200 datasheet revision E.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91RM9200_SPI_H
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#define AT91RM9200_SPI_H
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#define AT91_SPI_CR 0x00 /* Control Register */
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#define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */
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#define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */
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#define AT91_SPI_SWRST (1 << 7) /* SPI Software Reset */
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#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
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#define AT91_SPI_MR 0x04 /* Mode Register */
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#define AT91_SPI_MSTR (1 << 0) /* Master/Slave Mode */
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#define AT91_SPI_PS (1 << 1) /* Peripheral Select */
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#define AT91_SPI_PS_FIXED (0 << 1)
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#define AT91_SPI_PS_VARIABLE (1 << 1)
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#define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */
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#define AT91_SPI_DIV32 (1 << 3) /* Clock Selection */
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#define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */
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#define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */
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#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
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#define AT91_SPI_DLYBCS (0xff << 24) /* Delay Between Chip Selects */
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#define AT91_SPI_RDR 0x08 /* Receive Data Register */
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#define AT91_SPI_RD (0xffff << 0) /* Receive Data */
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#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
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#define AT91_SPI_TDR 0x0c /* Transmit Data Register */
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#define AT91_SPI_TD (0xffff << 0) /* Transmit Data */
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#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
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#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
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#define AT91_SPI_SR 0x10 /* Status Register */
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#define AT91_SPI_RDRF (1 << 0) /* Receive Data Register Full */
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#define AT91_SPI_TDRE (1 << 1) /* Transmit Data Register Full */
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#define AT91_SPI_MODF (1 << 2) /* Mode Fault Error */
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#define AT91_SPI_OVRES (1 << 3) /* Overrun Error Status */
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#define AT91_SPI_ENDRX (1 << 4) /* End of RX buffer */
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#define AT91_SPI_ENDTX (1 << 5) /* End of TX buffer */
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#define AT91_SPI_RXBUFF (1 << 6) /* RX Buffer Full */
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#define AT91_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */
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#define AT91_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */
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#define AT91_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */
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#define AT91_SPI_SPIENS (1 << 16) /* SPI Enable Status */
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#define AT91_SPI_IER 0x14 /* Interrupt Enable Register */
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#define AT91_SPI_IDR 0x18 /* Interrupt Disable Register */
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#define AT91_SPI_IMR 0x1c /* Interrupt Mask Register */
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#define AT91_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */
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#define AT91_SPI_CPOL (1 << 0) /* Clock Polarity */
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#define AT91_SPI_NCPHA (1 << 1) /* Clock Phase */
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#define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */
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#define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */
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#define AT91_SPI_BITS_8 (0 << 4)
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#define AT91_SPI_BITS_9 (1 << 4)
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#define AT91_SPI_BITS_10 (2 << 4)
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#define AT91_SPI_BITS_11 (3 << 4)
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#define AT91_SPI_BITS_12 (4 << 4)
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#define AT91_SPI_BITS_13 (5 << 4)
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#define AT91_SPI_BITS_14 (6 << 4)
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#define AT91_SPI_BITS_15 (7 << 4)
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#define AT91_SPI_BITS_16 (8 << 4)
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#define AT91_SPI_SCBR (0xff << 8) /* Serial Clock Baud Rate */
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#define AT91_SPI_DLYBS (0xff << 16) /* Delay before SPCK */
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#define AT91_SPI_DLYBCT (0xff << 24) /* Delay between Consecutive Transfers */
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#endif
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96
include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h
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96
include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h
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@ -0,0 +1,96 @@
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/*
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* include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h
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*
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* Copyright (C) SAN People
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*
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* Serial Synchronous Controller (SSC) registers.
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* Based on AT91RM9200 datasheet revision E.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91RM9200_SSC_H
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#define AT91RM9200_SSC_H
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#define AT91_SSC_CR 0x00 /* Control Register */
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#define AT91_SSC_RXEN (1 << 0) /* Receive Enable */
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#define AT91_SSC_RXDIS (1 << 1) /* Receive Disable */
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#define AT91_SSC_TXEN (1 << 8) /* Transmit Enable */
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#define AT91_SSC_TXDIS (1 << 9) /* Transmit Disable */
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#define AT91_SSC_SWRST (1 << 15) /* Software Reset */
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#define AT91_SSC_CMR 0x04 /* Clock Mode Register */
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#define AT91_SSC_CMR_DIV (0xfff << 0) /* Clock Divider */
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#define AT91_SSC_RCMR 0x10 /* Receive Clock Mode Register */
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#define AT91_SSC_CKS (3 << 0) /* Clock Selection */
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#define AT91_SSC_CKS_DIV (0 << 0)
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#define AT91_SSC_CKS_CLOCK (1 << 0)
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#define AT91_SSC_CKS_PIN (2 << 0)
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#define AT91_SSC_CKO (7 << 2) /* Clock Output Mode Selection */
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#define AT91_SSC_CKO_NONE (0 << 2)
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#define AT91_SSC_CKO_CONTINUOUS (1 << 2)
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#define AT91_SSC_CKI (1 << 5) /* Clock Inversion */
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#define AT91_SSC_CKI_FALLING (0 << 5)
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#define AT91_SSC_CK_RISING (1 << 5)
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#define AT91_SSC_START (0xf << 8) /* Start Selection */
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#define AT91_SSC_START_CONTINUOUS (0 << 8)
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#define AT91_SSC_START_TX_RX (1 << 8)
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#define AT91_SSC_START_LOW_RF (2 << 8)
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#define AT91_SSC_START_HIGH_RF (3 << 8)
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#define AT91_SSC_START_FALLING_RF (4 << 8)
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#define AT91_SSC_START_RISING_RF (5 << 8)
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#define AT91_SSC_START_LEVEL_RF (6 << 8)
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#define AT91_SSC_START_EDGE_RF (7 << 8)
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#define AT91_SSC_STTDLY (0xff << 16) /* Start Delay */
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#define AT91_SSC_PERIOD (0xff << 24) /* Period Divider Selection */
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#define AT91_SSC_RFMR 0x14 /* Receive Frame Mode Register */
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#define AT91_SSC_DATALEN (0x1f << 0) /* Data Length */
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#define AT91_SSC_LOOP (1 << 5) /* Loop Mode */
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#define AT91_SSC_MSBF (1 << 7) /* Most Significant Bit First */
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#define AT91_SSC_DATNB (0xf << 8) /* Data Number per Frame */
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#define AT91_SSC_FSLEN (0xf << 16) /* Frame Sync Length */
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#define AT91_SSC_FSOS (7 << 20) /* Frame Sync Output Selection */
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#define AT91_SSC_FSOS_NONE (0 << 20)
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#define AT91_SSC_FSOS_NEGATIVE (1 << 20)
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#define AT91_SSC_FSOS_POSITIVE (2 << 20)
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#define AT91_SSC_FSOS_LOW (3 << 20)
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#define AT91_SSC_FSOS_HIGH (4 << 20)
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#define AT91_SSC_FSOS_TOGGLE (5 << 20)
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#define AT91_SSC_FSEDGE (1 << 24) /* Frame Sync Edge Detection */
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#define AT91_SSC_FSEDGE_POSITIVE (0 << 24)
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#define AT91_SSC_FSEDGE_NEGATIVE (1 << 24)
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#define AT91_SSC_TCMR 0x18 /* Transmit Clock Mode Register */
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#define AT91_SSC_TFMR 0x1c /* Transmit Fram Mode Register */
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#define AT91_SSC_DATDEF (1 << 5) /* Data Default Value */
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#define AT91_SSC_FSDEN (1 << 23) /* Frame Sync Data Enable */
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#define AT91_SSC_RHR 0x20 /* Receive Holding Register */
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#define AT91_SSC_THR 0x24 /* Transmit Holding Register */
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#define AT91_SSC_RSHR 0x30 /* Receive Sync Holding Register */
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#define AT91_SSC_TSHR 0x34 /* Transmit Sync Holding Register */
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#define AT91_SSC_SR 0x40 /* Status Register */
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#define AT91_SSC_TXRDY (1 << 0) /* Transmit Ready */
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#define AT91_SSC_TXEMPTY (1 << 1) /* Transmit Empty */
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#define AT91_SSC_ENDTX (1 << 2) /* End of Transmission */
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#define AT91_SSC_TXBUFE (1 << 3) /* Transmit Buffer Empty */
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#define AT91_SSC_RXRDY (1 << 4) /* Receive Ready */
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#define AT91_SSC_OVRUN (1 << 5) /* Receive Overrun */
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#define AT91_SSC_ENDRX (1 << 6) /* End of Reception */
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#define AT91_SSC_RXBUFF (1 << 7) /* Receive Buffer Full */
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#define AT91_SSC_TXSYN (1 << 10) /* Transmit Sync */
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#define AT91_SSC_RXSYN (1 << 11) /* Receive Sync */
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#define AT91_SSC_TXENA (1 << 16) /* Transmit Enable */
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#define AT91_SSC_RXENA (1 << 17) /* Receive Enable */
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#define AT91_SSC_IER 0x44 /* Interrupt Enable Register */
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#define AT91_SSC_IDR 0x48 /* Interrupt Disable Register */
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#define AT91_SSC_IMR 0x4c /* Interrupt Mask Register */
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#endif
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146
include/asm-arm/arch-at91rm9200/at91rm9200_tc.h
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146
include/asm-arm/arch-at91rm9200/at91rm9200_tc.h
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@ -0,0 +1,146 @@
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/*
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* include/asm-arm/arch-at91rm9200/at91rm9200_tc.h
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*
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* Copyright (C) SAN People
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*
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* Timer/Counter Unit (TC) registers.
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* Based on AT91RM9200 datasheet revision E.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91RM9200_TC_H
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#define AT91RM9200_TC_H
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#define AT91_TC_BCR 0xc0 /* TC Block Control Register */
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#define AT91_TC_SYNC (1 << 0) /* Synchro Command */
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#define AT91_TC_BMR 0xc4 /* TC Block Mode Register */
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#define AT91_TC_TC0XC0S (3 << 0) /* External Clock Signal 0 Selection */
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#define AT91_TC_TC0XC0S_TCLK0 (0 << 0)
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#define AT91_TC_TC0XC0S_NONE (1 << 0)
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#define AT91_TC_TC0XC0S_TIOA1 (2 << 0)
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#define AT91_TC_TC0XC0S_TIOA2 (3 << 0)
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#define AT91_TC_TC1XC1S (3 << 2) /* External Clock Signal 1 Selection */
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#define AT91_TC_TC1XC1S_TCLK1 (0 << 2)
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#define AT91_TC_TC1XC1S_NONE (1 << 2)
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#define AT91_TC_TC1XC1S_TIOA0 (2 << 2)
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#define AT91_TC_TC1XC1S_TIOA2 (3 << 2)
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#define AT91_TC_TC2XC2S (3 << 4) /* External Clock Signal 2 Selection */
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#define AT91_TC_TC2XC2S_TCLK2 (0 << 4)
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#define AT91_TC_TC2XC2S_NONE (1 << 4)
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#define AT91_TC_TC2XC2S_TIOA0 (2 << 4)
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#define AT91_TC_TC2XC2S_TIOA1 (3 << 4)
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#define AT91_TC_CCR 0x00 /* Channel Control Register */
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#define AT91_TC_CLKEN (1 << 0) /* Counter Clock Enable Command */
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#define AT91_TC_CLKDIS (1 << 1) /* Counter CLock Disable Command */
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#define AT91_TC_SWTRG (1 << 2) /* Software Trigger Command */
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#define AT91_TC_CMR 0x04 /* Channel Mode Register */
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#define AT91_TC_TCCLKS (7 << 0) /* Capture/Waveform Mode: Clock Selection */
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#define AT91_TC_TIMER_CLOCK1 (0 << 0)
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#define AT91_TC_TIMER_CLOCK2 (1 << 0)
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#define AT91_TC_TIMER_CLOCK3 (2 << 0)
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#define AT91_TC_TIMER_CLOCK4 (3 << 0)
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#define AT91_TC_TIMER_CLOCK5 (4 << 0)
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#define AT91_TC_XC0 (5 << 0)
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#define AT91_TC_XC1 (6 << 0)
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#define AT91_TC_XC2 (7 << 0)
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#define AT91_TC_CLKI (1 << 3) /* Capture/Waveform Mode: Clock Invert */
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#define AT91_TC_BURST (3 << 4) /* Capture/Waveform Mode: Burst Signal Selection */
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#define AT91_TC_LDBSTOP (1 << 6) /* Capture Mode: Counter Clock Stopped with TB Loading */
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#define AT91_TC_LDBDIS (1 << 7) /* Capture Mode: Counter Clock Disable with RB Loading */
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#define AT91_TC_ETRGEDG (3 << 8) /* Capture Mode: External Trigger Edge Selection */
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#define AT91_TC_ABETRG (1 << 10) /* Capture Mode: TIOA or TIOB External Trigger Selection */
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#define AT91_TC_CPCTRG (1 << 14) /* Capture Mode: RC Compare Trigger Enable */
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#define AT91_TC_WAVE (1 << 15) /* Capture/Waveform mode */
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#define AT91_TC_LDRA (3 << 16) /* Capture Mode: RA Loading Selection */
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#define AT91_TC_LDRB (3 << 18) /* Capture Mode: RB Loading Selection */
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#define AT91_TC_CPCSTOP (1 << 6) /* Waveform Mode: Counter Clock Stopped with RC Compare */
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#define AT91_TC_CPCDIS (1 << 7) /* Waveform Mode: Counter Clock Disable with RC Compare */
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#define AT91_TC_EEVTEDG (3 << 8) /* Waveform Mode: External Event Edge Selection */
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#define AT91_TC_EEVTEDG_NONE (0 << 8)
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#define AT91_TC_EEVTEDG_RISING (1 << 8)
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#define AT91_TC_EEVTEDG_FALLING (2 << 8)
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#define AT91_TC_EEVTEDG_BOTH (3 << 8)
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#define AT91_TC_EEVT (3 << 10) /* Waveform Mode: External Event Selection */
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#define AT91_TC_EEVT_TIOB (0 << 10)
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#define AT91_TC_EEVT_XC0 (1 << 10)
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#define AT91_TC_EEVT_XC1 (2 << 10)
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#define AT91_TC_EEVT_XC2 (3 << 10)
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#define AT91_TC_ENETRG (1 << 12) /* Waveform Mode: External Event Trigger Enable */
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#define AT91_TC_WAVESEL (3 << 13) /* Waveform Mode: Waveform Selection */
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#define AT91_TC_WAVESEL_UP (0 << 13)
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#define AT91_TC_WAVESEL_UP_AUTO (2 << 13)
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#define AT91_TC_WAVESEL_UPDOWN (1 << 13)
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#define AT91_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
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#define AT91_TC_ACPA (3 << 16) /* Waveform Mode: RA Compare Effect on TIOA */
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#define AT91_TC_ACPA_NONE (0 << 16)
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#define AT91_TC_ACPA_SET (1 << 16)
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#define AT91_TC_ACPA_CLEAR (2 << 16)
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#define AT91_TC_ACPA_TOGGLE (3 << 16)
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#define AT91_TC_ACPC (3 << 18) /* Waveform Mode: RC Compre Effect on TIOA */
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#define AT91_TC_ACPC_NONE (0 << 18)
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#define AT91_TC_ACPC_SET (1 << 18)
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#define AT91_TC_ACPC_CLEAR (2 << 18)
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#define AT91_TC_ACPC_TOGGLE (3 << 18)
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#define AT91_TC_AEEVT (3 << 20) /* Waveform Mode: External Event Effect on TIOA */
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#define AT91_TC_AEEVT_NONE (0 << 20)
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#define AT91_TC_AEEVT_SET (1 << 20)
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#define AT91_TC_AEEVT_CLEAR (2 << 20)
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#define AT91_TC_AEEVT_TOGGLE (3 << 20)
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#define AT91_TC_ASWTRG (3 << 22) /* Waveform Mode: Software Trigger Effect on TIOA */
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#define AT91_TC_ASWTRG_NONE (0 << 22)
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#define AT91_TC_ASWTRG_SET (1 << 22)
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#define AT91_TC_ASWTRG_CLEAR (2 << 22)
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#define AT91_TC_ASWTRG_TOGGLE (3 << 22)
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#define AT91_TC_BCPB (3 << 24) /* Waveform Mode: RB Compare Effect on TIOB */
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#define AT91_TC_BCPB_NONE (0 << 24)
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#define AT91_TC_BCPB_SET (1 << 24)
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#define AT91_TC_BCPB_CLEAR (2 << 24)
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#define AT91_TC_BCPB_TOGGLE (3 << 24)
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#define AT91_TC_BCPC (3 << 26) /* Waveform Mode: RC Compare Effect on TIOB */
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#define AT91_TC_BCPC_NONE (0 << 26)
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#define AT91_TC_BCPC_SET (1 << 26)
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#define AT91_TC_BCPC_CLEAR (2 << 26)
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#define AT91_TC_BCPC_TOGGLE (3 << 26)
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#define AT91_TC_BEEVT (3 << 28) /* Waveform Mode: External Event Effect on TIOB */
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#define AT91_TC_BEEVT_NONE (0 << 28)
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#define AT91_TC_BEEVT_SET (1 << 28)
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#define AT91_TC_BEEVT_CLEAR (2 << 28)
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#define AT91_TC_BEEVT_TOGGLE (3 << 28)
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#define AT91_TC_BSWTRG (3 << 30) /* Waveform Mode: Software Trigger Effect on TIOB */
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#define AT91_TC_BSWTRG_NONE (0 << 30)
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#define AT91_TC_BSWTRG_SET (1 << 30)
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#define AT91_TC_BSWTRG_CLEAR (2 << 30)
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#define AT91_TC_BSWTRG_TOGGLE (3 << 30)
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#define AT91_TC_CV 0x10 /* Counter Value */
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#define AT91_TC_RA 0x14 /* Register A */
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#define AT91_TC_RB 0x18 /* Register B */
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#define AT91_TC_RC 0x1c /* Register C */
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|
||||
#define AT91_TC_SR 0x20 /* Status Register */
|
||||
#define AT91_TC_COVFS (1 << 0) /* Counter Overflow Status */
|
||||
#define AT91_TC_LOVRS (1 << 1) /* Load Overrun Status */
|
||||
#define AT91_TC_CPAS (1 << 2) /* RA Compare Status */
|
||||
#define AT91_TC_CPBS (1 << 3) /* RB Compare Status */
|
||||
#define AT91_TC_CPCS (1 << 4) /* RC Compare Status */
|
||||
#define AT91_TC_LDRAS (1 << 5) /* RA Loading Status */
|
||||
#define AT91_TC_LDRBS (1 << 6) /* RB Loading Status */
|
||||
#define AT91_TC_ETRGS (1 << 7) /* External Trigger Status */
|
||||
#define AT91_TC_CLKSTA (1 << 16) /* Clock Enabling Status */
|
||||
#define AT91_TC_MTIOA (1 << 17) /* TIOA Mirror */
|
||||
#define AT91_TC_MTIOB (1 << 18) /* TIOB Mirror */
|
||||
|
||||
#define AT91_TC_IER 0x24 /* Interrupt Enable Register */
|
||||
#define AT91_TC_IDR 0x28 /* Interrupt Disable Register */
|
||||
#define AT91_TC_IMR 0x2c /* Interrupt Mask Register */
|
||||
|
||||
#endif
|
||||
77
include/asm-arm/arch-at91rm9200/at91rm9200_udp.h
Normal file
77
include/asm-arm/arch-at91rm9200/at91rm9200_udp.h
Normal file
@ -0,0 +1,77 @@
|
||||
/*
|
||||
* include/asm-arm/arch-at91rm9200/at91rm9200_udp.h
|
||||
*
|
||||
* Copyright (C) 2005 Ivan Kokshaysky
|
||||
* Copyright (C) SAN People
|
||||
*
|
||||
* USB Device Port (UDP) registers.
|
||||
* Based on AT91RM9200 datasheet revision E.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91RM9200_UDP_H
|
||||
#define AT91RM9200_UDP_H
|
||||
|
||||
#define AT91_UDP_FRM_NUM 0x00 /* Frame Number Register */
|
||||
#define AT91_UDP_NUM (0x7ff << 0) /* Frame Number */
|
||||
#define AT91_UDP_FRM_ERR (1 << 16) /* Frame Error */
|
||||
#define AT91_UDP_FRM_OK (1 << 17) /* Frame OK */
|
||||
|
||||
#define AT91_UDP_GLB_STAT 0x04 /* Global State Register */
|
||||
#define AT91_UDP_FADDEN (1 << 0) /* Function Address Enable */
|
||||
#define AT91_UDP_CONFG (1 << 1) /* Configured */
|
||||
#define AT91_UDP_ESR (1 << 2) /* Enable Send Resume */
|
||||
#define AT91_UDP_RSMINPR (1 << 3) /* Resume has been sent */
|
||||
#define AT91_UDP_RMWUPE (1 << 4) /* Remote Wake Up Enable */
|
||||
|
||||
#define AT91_UDP_FADDR 0x08 /* Function Address Register */
|
||||
#define AT91_UDP_FADD (0x7f << 0) /* Function Address Value */
|
||||
#define AT91_UDP_FEN (1 << 8) /* Function Enable */
|
||||
|
||||
#define AT91_UDP_IER 0x10 /* Interrupt Enable Register */
|
||||
#define AT91_UDP_IDR 0x14 /* Interrupt Disable Register */
|
||||
#define AT91_UDP_IMR 0x18 /* Interrupt Mask Register */
|
||||
|
||||
#define AT91_UDP_ISR 0x1c /* Interrupt Status Register */
|
||||
#define AT91_UDP_EP(n) (1 << (n)) /* Endpoint Interrupt Status */
|
||||
#define AT91_UDP_RXSUSP (1 << 8) /* USB Suspend Interrupt Status */
|
||||
#define AT91_UDP_RXRSM (1 << 9) /* USB Resume Interrupt Status */
|
||||
#define AT91_UDP_EXTRSM (1 << 10) /* External Resume Interrupt Status */
|
||||
#define AT91_UDP_SOFINT (1 << 11) /* Start of Frame Interrupt Status */
|
||||
#define AT91_UDP_ENDBUSRES (1 << 12) /* End of Bus Reset Interrpt Status */
|
||||
#define AT91_UDP_WAKEUP (1 << 13) /* USB Wakeup Interrupt Status */
|
||||
|
||||
#define AT91_UDP_ICR 0x20 /* Interrupt Clear Register */
|
||||
#define AT91_UDP_RST_EP 0x28 /* Reset Endpoint Register */
|
||||
|
||||
#define AT91_UDP_CSR(n) (0x30 + ((n) * 4)) /* Endpoint Control/Status Registers 0-7 */
|
||||
#define AT91_UDP_TXCOMP (1 << 0) /* Generates IN packet with data previously written in DPR */
|
||||
#define AT91_UDP_RX_DATA_BK0 (1 << 1) /* Receive Data Bank 0 */
|
||||
#define AT91_UDP_RXSETUP (1 << 2) /* Send STALL to the host */
|
||||
#define AT91_UDP_STALLSENT (1 << 3) /* Stall Sent / Isochronous error (Isochronous endpoints) */
|
||||
#define AT91_UDP_TXPKTRDY (1 << 4) /* Transmit Packet Ready */
|
||||
#define AT91_UDP_FORCESTALL (1 << 5) /* Force Stall */
|
||||
#define AT91_UDP_RX_DATA_BK1 (1 << 6) /* Receive Data Bank 1 */
|
||||
#define AT91_UDP_DIR (1 << 7) /* Transfer Direction */
|
||||
#define AT91_UDP_EPTYPE (7 << 8) /* Endpoint Type */
|
||||
#define AT91_UDP_EPTYPE_CTRL (0 << 8)
|
||||
#define AT91_UDP_EPTYPE_ISO_OUT (1 << 8)
|
||||
#define AT91_UDP_EPTYPE_BULK_OUT (2 << 8)
|
||||
#define AT91_UDP_EPTYPE_INT_OUT (3 << 8)
|
||||
#define AT91_UDP_EPTYPE_ISO_IN (5 << 8)
|
||||
#define AT91_UDP_EPTYPE_BULK_IN (6 << 8)
|
||||
#define AT91_UDP_EPTYPE_INT_IN (7 << 8)
|
||||
#define AT91_UDP_DTGLE (1 << 11) /* Data Toggle */
|
||||
#define AT91_UDP_EPEDS (1 << 15) /* Endpoint Enable/Disable */
|
||||
#define AT91_UDP_RXBYTECNT (0x7ff << 16) /* Number of bytes in FIFO */
|
||||
|
||||
#define AT91_UDP_FDR(n) (0x50 + ((n) * 4)) /* Endpoint FIFO Data Registers 0-7 */
|
||||
|
||||
#define AT91_UDP_TXVC 0x74 /* Transceiver Control Register */
|
||||
#define AT91_UDP_TXVC_TXVDIS (1 << 8) /* Transceiver Disable */
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user