From 2b20b6164ec737bec67641564e477aa6e008748b Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 9 Dec 2014 22:36:50 +0000 Subject: [PATCH 1/9] soc/tegra: pmc: restrict compilation of suspend-related support to ARM Tegra SoCs with 64-bit ARM support don't currently support deep CPU low-power states in mainline Linux. When this support is added in the future, it will probably look rather different from the existing 32-bit ARM support, since the ARM64 maintainers' strong preference is to use PSCI to implement it. So, for the time being, prevent the CPU suspend-related code and data in the Tegra PMC driver from compiling on ARM64. Signed-off-by: Paul Walmsley Signed-off-by: Paul Walmsley Cc: Thierry Reding Cc: Allen Martin Cc: Stephen Warren Cc: Alexandre Courbot Signed-off-by: Thierry Reding --- drivers/soc/tegra/pmc.c | 7 +++++-- include/soc/tegra/pm.h | 2 +- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index a2c0ceb95f8f..4bdc654bd747 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -739,7 +739,7 @@ static int tegra_pmc_probe(struct platform_device *pdev) return 0; } -#ifdef CONFIG_PM_SLEEP +#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) static int tegra_pmc_suspend(struct device *dev) { tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41); @@ -753,10 +753,11 @@ static int tegra_pmc_resume(struct device *dev) return 0; } -#endif static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume); +#endif + static const char * const tegra20_powergates[] = { [TEGRA_POWERGATE_CPU] = "cpu", [TEGRA_POWERGATE_3D] = "3d", @@ -894,7 +895,9 @@ static struct platform_driver tegra_pmc_driver = { .name = "tegra-pmc", .suppress_bind_attrs = true, .of_match_table = tegra_pmc_match, +#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) .pm = &tegra_pmc_pm_ops, +#endif }, .probe = tegra_pmc_probe, }; diff --git a/include/soc/tegra/pm.h b/include/soc/tegra/pm.h index 30fe2078a547..03909101d4e7 100644 --- a/include/soc/tegra/pm.h +++ b/include/soc/tegra/pm.h @@ -17,7 +17,7 @@ enum tegra_suspend_mode { TEGRA_MAX_SUSPEND_MODE, }; -#ifdef CONFIG_PM_SLEEP +#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) enum tegra_suspend_mode tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode); From 910978e753d0be0b429cf75b5adaed55b90c96b2 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 7 Jul 2014 15:26:30 +0200 Subject: [PATCH 2/9] clocksource: Build Tegra timer on 32-bit ARM only Instead of directly using the ARCH_TEGRA Kconfig symbol to enable this driver, add a new, non-user-visible Kconfig symbol (TEGRA_TIMER) which can be selected by the various SoCs. This is useful to disable building the driver on Tegra132 (64-bit ARM) where it doesn't currently compile but also isn't needed (yet). Acked-by: Daniel Lezcano Signed-off-by: Thierry Reding --- arch/arm/mach-tegra/Kconfig | 4 ++++ drivers/clocksource/Kconfig | 3 +++ drivers/clocksource/Makefile | 2 +- 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index d0be9a1ef6b8..5d1a318f1302 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -27,6 +27,7 @@ config ARCH_TEGRA_2x_SOC select PINCTRL_TEGRA20 select PL310_ERRATA_727915 if CACHE_L2X0 select PL310_ERRATA_769419 if CACHE_L2X0 + select TEGRA_TIMER help Support for NVIDIA Tegra AP20 and T20 processors, based on the ARM CortexA9MP CPU and the ARM PL310 L2 cache controller @@ -37,6 +38,7 @@ config ARCH_TEGRA_3x_SOC select ARM_ERRATA_764369 if SMP select PINCTRL_TEGRA30 select PL310_ERRATA_769419 if CACHE_L2X0 + select TEGRA_TIMER help Support for NVIDIA Tegra T30 processor family, based on the ARM CortexA9MP CPU and the ARM PL310 L2 cache controller @@ -47,6 +49,7 @@ config ARCH_TEGRA_114_SOC select ARM_L1_CACHE_SHIFT_6 select HAVE_ARM_ARCH_TIMER select PINCTRL_TEGRA114 + select TEGRA_TIMER help Support for NVIDIA Tegra T114 processor family, based on the ARM CortexA15MP CPU @@ -56,6 +59,7 @@ config ARCH_TEGRA_124_SOC select ARM_L1_CACHE_SHIFT_6 select HAVE_ARM_ARCH_TIMER select PINCTRL_TEGRA124 + select TEGRA_TIMER help Support for NVIDIA Tegra T124 processor family, based on the ARM CortexA15MP CPU diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index fc01ec27d3c8..c062b6105d49 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -47,6 +47,9 @@ config SUN5I_HSTIMER select CLKSRC_MMIO bool +config TEGRA_TIMER + bool + config VT8500_TIMER bool diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 94d90b24b56b..ba9ebd868ec5 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -27,7 +27,7 @@ obj-$(CONFIG_ARCH_U300) += timer-u300.o obj-$(CONFIG_SUN4I_TIMER) += sun4i_timer.o obj-$(CONFIG_SUN5I_HSTIMER) += timer-sun5i.o obj-$(CONFIG_MESON6_TIMER) += meson6_timer.o -obj-$(CONFIG_ARCH_TEGRA) += tegra20_timer.o +obj-$(CONFIG_TEGRA_TIMER) += tegra20_timer.o obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o obj-$(CONFIG_ARCH_NSPIRE) += zevio-timer.o obj-$(CONFIG_ARCH_BCM_MOBILE) += bcm_kona_timer.o From 24ef5745dafc2eaf287a0bb9ee9e4ff9a4f64108 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 8 Jan 2015 08:24:45 +0100 Subject: [PATCH 3/9] soc/tegra: Add Tegra132 support Add the chip ID for the NVIDIA Tegra132 SoC family. Signed-off-by: Thierry Reding --- include/soc/tegra/fuse.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/soc/tegra/fuse.h b/include/soc/tegra/fuse.h index 8e1249474e84..b5f7b5f8d008 100644 --- a/include/soc/tegra/fuse.h +++ b/include/soc/tegra/fuse.h @@ -21,6 +21,7 @@ #define TEGRA30 0x30 #define TEGRA114 0x35 #define TEGRA124 0x40 +#define TEGRA132 0x13 #define TEGRA_FUSE_SKU_CALIB_0 0xf0 #define TEGRA30_FUSE_SATA_CALIB 0x124 From 200d876a5ad136e9d92a107a8190dd8d017d76fc Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 8 Jan 2015 08:24:46 +0100 Subject: [PATCH 4/9] soc/tegra: fuse: Constify tegra_fuse_info structures These structures contain read-only data and are never modified, so they can be const. Signed-off-by: Thierry Reding --- drivers/soc/tegra/fuse/fuse-tegra30.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse/fuse-tegra30.c index 8646fa920d8d..d1a4290cda5c 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra30.c +++ b/drivers/soc/tegra/fuse/fuse-tegra30.c @@ -56,7 +56,7 @@ struct tegra_fuse_info { static void __iomem *fuse_base; static struct clk *fuse_clk; -static struct tegra_fuse_info *fuse_info; +static const struct tegra_fuse_info *fuse_info; u32 tegra30_fuse_readl(const unsigned int offset) { @@ -78,18 +78,18 @@ u32 tegra30_fuse_readl(const unsigned int offset) return val; } -static struct tegra_fuse_info tegra30_info = { +static const struct tegra_fuse_info tegra30_info = { .size = 0x2a4, .spare_bit = 0x144, .speedo_idx = SPEEDO_TEGRA30, }; -static struct tegra_fuse_info tegra114_info = { +static const struct tegra_fuse_info tegra114_info = { .size = 0x2a0, .speedo_idx = SPEEDO_TEGRA114, }; -static struct tegra_fuse_info tegra124_info = { +static const struct tegra_fuse_info tegra124_info = { .size = 0x300, .speedo_idx = SPEEDO_TEGRA124, }; From 9b07eb0537fb5f4d5fed1c2466febf59170f2b2e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 9 Jan 2015 11:49:33 +0100 Subject: [PATCH 5/9] soc/tegra: fuse: Add Tegra132 support Tegra132 is very similar to Tegra124 from a peripheral point of view and uses the same fuse controller. Signed-off-by: Thierry Reding --- drivers/soc/tegra/fuse/fuse-tegra.c | 1 + drivers/soc/tegra/fuse/fuse-tegra30.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c index 011a3363c265..c0d660f1aaac 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra.c +++ b/drivers/soc/tegra/fuse/fuse-tegra.c @@ -81,6 +81,7 @@ static const struct of_device_id car_match[] __initconst = { { .compatible = "nvidia,tegra30-car", }, { .compatible = "nvidia,tegra114-car", }, { .compatible = "nvidia,tegra124-car", }, + { .compatible = "nvidia,tegra132-car", }, {}, }; diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse/fuse-tegra30.c index d1a4290cda5c..4d2f71bf65c5 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra30.c +++ b/drivers/soc/tegra/fuse/fuse-tegra30.c @@ -182,6 +182,7 @@ static void __init legacy_fuse_init(void) fuse_info = &tegra114_info; break; case TEGRA124: + case TEGRA132: fuse_info = &tegra124_info; break; default: From a9a40a4a58bac4ff92d0c7e5aa82043074533a6a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 9 Jan 2015 11:15:33 +0100 Subject: [PATCH 6/9] soc/tegra: pmc: Add Tegra132 support Tegra132 uses the same GPU as Tegra124 and therefore requires the same method to remove clamps. However Tegra132 has a separate chip ID, so in order to avoid having to extend the list of chip IDs for the special case, add a feature flag to the SoC data. Reviewed-by: Paul Walmsley Signed-off-by: Thierry Reding --- drivers/soc/tegra/pmc.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 4bdc654bd747..0f096e76574a 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -88,6 +88,8 @@ struct tegra_pmc_soc { const char *const *powergates; unsigned int num_cpu_powergates; const u8 *cpu_powergates; + + bool has_gpu_clamps; }; /** @@ -225,11 +227,11 @@ int tegra_powergate_remove_clamping(int id) return -EINVAL; /* - * The Tegra124 GPU has a separate register (with different semantics) - * to remove clamps. + * On Tegra124 and later, the clamps for the GPU are controlled by a + * separate register (with different semantics). */ - if (tegra_get_chip_id() == TEGRA124) { - if (id == TEGRA_POWERGATE_3D) { + if (id == TEGRA_POWERGATE_3D) { + if (pmc->soc->has_gpu_clamps) { tegra_pmc_writel(0, GPU_RG_CNTRL); return 0; } @@ -773,6 +775,7 @@ static const struct tegra_pmc_soc tegra20_pmc_soc = { .powergates = tegra20_powergates, .num_cpu_powergates = 0, .cpu_powergates = NULL, + .has_gpu_clamps = false, }; static const char * const tegra30_powergates[] = { @@ -804,6 +807,7 @@ static const struct tegra_pmc_soc tegra30_pmc_soc = { .powergates = tegra30_powergates, .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), .cpu_powergates = tegra30_cpu_powergates, + .has_gpu_clamps = false, }; static const char * const tegra114_powergates[] = { @@ -839,6 +843,7 @@ static const struct tegra_pmc_soc tegra114_pmc_soc = { .powergates = tegra114_powergates, .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), .cpu_powergates = tegra114_cpu_powergates, + .has_gpu_clamps = false, }; static const char * const tegra124_powergates[] = { @@ -880,6 +885,7 @@ static const struct tegra_pmc_soc tegra124_pmc_soc = { .powergates = tegra124_powergates, .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), .cpu_powergates = tegra124_cpu_powergates, + .has_gpu_clamps = true, }; static const struct of_device_id tegra_pmc_match[] = { From f58d47258131aa2d0243fc1dc78e2adc578d5de4 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Tue, 6 Jan 2015 12:52:56 +0200 Subject: [PATCH 7/9] of: Add descriptions of thermtrip properties to Tegra PMC bindings Hardware-triggered thermal reset requires configuring the I2C reset procedure. This configuration is read from the device tree, so document the relevant properties in the binding documentation. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding --- .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt index 68ac65f82a1c..2fd50511ab4b 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt @@ -47,6 +47,23 @@ Required properties when nvidia,suspend-mode=<0>: sleep mode, the warm boot code will restore some PLLs, clocks and then bring up CPU0 for resuming the system. +Hardware-triggered thermal reset: +On Tegra30, Tegra114 and Tegra124, if the 'i2c-thermtrip' subnode exists, +hardware-triggered thermal reset will be enabled. + +Required properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'): +- nvidia,i2c-controller-id : ID of I2C controller to send poweroff command to. Valid values are + described in section 9.2.148 "APBDEV_PMC_SCRATCH53_0" of the + Tegra K1 Technical Reference Manual. +- nvidia,bus-addr : Bus address of the PMU on the I2C bus +- nvidia,reg-addr : I2C register address to write poweroff command to +- nvidia,reg-data : Poweroff command to write to PMU + +Optional properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'): +- nvidia,pinmux-id : Pinmux used by the hardware when issuing poweroff command. + Defaults to 0. Valid values are described in section 12.5.2 + "Pinmux Support" of the Tegra4 Technical Reference Manual. + Example: / SoC dts including file @@ -68,6 +85,15 @@ pmc@7000f400 { / Tegra board dts file { + ... + pmc@7000f400 { + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x40>; + nvidia,reg-addr = <0x36>; + nvidia,reg-data = <0x2>; + }; + }; ... clocks { compatible = "simple-bus"; From 9c963301538f857495d8a168de510d511a28d759 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Tue, 6 Jan 2015 12:52:57 +0200 Subject: [PATCH 8/9] ARM: tegra: Add PMC thermtrip programming to Jetson TK1 device tree This adds the required information to reset the board during an overheating situation to the Jetson TK1 device tree. The thermal reset is handled by the PMC by sending an I2C message to the PMIC. The entries specify the I2C message to be sent. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 4eb540be368f..dbfaba09703a 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1673,6 +1673,13 @@ nvidia,core-pwr-off-time = <61036>; nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; + + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x40>; + nvidia,reg-addr = <0x36>; + nvidia,reg-data = <0x2>; + }; }; /* Serial ATA */ From 3568df3d31d62b4368830cc6aac868cecdefd187 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Tue, 6 Jan 2015 12:52:58 +0200 Subject: [PATCH 9/9] soc: tegra: Add thermal reset (thermtrip) support to PMC This adds a device tree controlled option to enable PMC-based thermal reset in overheating situations. Thermtrip is supported on Tegra30, Tegra114 and Tegra124. The thermal reset only works when the thermal sensors are calibrated, so a soctherm driver is also required. The thermtrip event is triggered by the soctherm block, and all soctherm sensors default to showing a temperature of zero Celsius before they are initialized. Because of this, it is safe to initialize thermtrip and soctherm in any order. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding --- drivers/soc/tegra/pmc.c | 103 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 0f096e76574a..c956395cf46f 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -70,6 +70,10 @@ #define PMC_SCRATCH41 0x140 +#define PMC_SENSOR_CTRL 0x1b0 +#define PMC_SENSOR_CTRL_SCRATCH_WRITE (1 << 2) +#define PMC_SENSOR_CTRL_ENABLE_RST (1 << 1) + #define IO_DPD_REQ 0x1b8 #define IO_DPD_REQ_CODE_IDLE (0 << 30) #define IO_DPD_REQ_CODE_OFF (1 << 30) @@ -81,6 +85,18 @@ #define IO_DPD2_STATUS 0x1c4 #define SEL_DPD_TIM 0x1c8 +#define PMC_SCRATCH54 0x258 +#define PMC_SCRATCH54_DATA_SHIFT 8 +#define PMC_SCRATCH54_ADDR_SHIFT 0 + +#define PMC_SCRATCH55 0x25c +#define PMC_SCRATCH55_RESET_TEGRA (1 << 31) +#define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 +#define PMC_SCRATCH55_PINMUX_SHIFT 24 +#define PMC_SCRATCH55_16BITOP (1 << 15) +#define PMC_SCRATCH55_CHECKSUM_SHIFT 16 +#define PMC_SCRATCH55_I2CSLV1_SHIFT 0 + #define GPU_RG_CNTRL 0x2d4 struct tegra_pmc_soc { @@ -89,6 +105,7 @@ struct tegra_pmc_soc { unsigned int num_cpu_powergates; const u8 *cpu_powergates; + bool has_tsense_reset; bool has_gpu_clamps; }; @@ -112,6 +129,7 @@ struct tegra_pmc_soc { * @powergates_lock: mutex for power gate register access */ struct tegra_pmc { + struct device *dev; void __iomem *base; struct clk *clk; @@ -705,6 +723,83 @@ static void tegra_pmc_init(struct tegra_pmc *pmc) tegra_pmc_writel(value, PMC_CNTRL); } +void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) +{ + static const char disabled[] = "emergency thermal reset disabled"; + u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux; + struct device *dev = pmc->dev; + struct device_node *np; + u32 value, checksum; + + if (!pmc->soc->has_tsense_reset) + goto out; + + np = of_find_node_by_name(pmc->dev->of_node, "i2c-thermtrip"); + if (!np) { + dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); + goto out; + } + + if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { + dev_err(dev, "I2C controller ID missing, %s.\n", disabled); + goto out; + } + + if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { + dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); + goto out; + } + + if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { + dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); + goto out; + } + + if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { + dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); + goto out; + } + + if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) + pinmux = 0; + + value = tegra_pmc_readl(PMC_SENSOR_CTRL); + value |= PMC_SENSOR_CTRL_SCRATCH_WRITE; + tegra_pmc_writel(value, PMC_SENSOR_CTRL); + + value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) | + (reg_addr << PMC_SCRATCH54_ADDR_SHIFT); + tegra_pmc_writel(value, PMC_SCRATCH54); + + value = PMC_SCRATCH55_RESET_TEGRA; + value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT; + value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT; + value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT; + + /* + * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will + * contain the checksum and are currently zero, so they are not added. + */ + checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) + + ((value >> 24) & 0xff); + checksum &= 0xff; + checksum = 0x100 - checksum; + + value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT; + + tegra_pmc_writel(value, PMC_SCRATCH55); + + value = tegra_pmc_readl(PMC_SENSOR_CTRL); + value |= PMC_SENSOR_CTRL_ENABLE_RST; + tegra_pmc_writel(value, PMC_SENSOR_CTRL); + + dev_info(pmc->dev, "emergency thermal reset enabled\n"); + +out: + of_node_put(np); + return; +} + static int tegra_pmc_probe(struct platform_device *pdev) { void __iomem *base = pmc->base; @@ -730,8 +825,12 @@ static int tegra_pmc_probe(struct platform_device *pdev) return err; } + pmc->dev = &pdev->dev; + tegra_pmc_init(pmc); + tegra_pmc_init_tsense_reset(pmc); + if (IS_ENABLED(CONFIG_DEBUG_FS)) { err = tegra_powergate_debugfs_init(); if (err < 0) @@ -775,6 +874,7 @@ static const struct tegra_pmc_soc tegra20_pmc_soc = { .powergates = tegra20_powergates, .num_cpu_powergates = 0, .cpu_powergates = NULL, + .has_tsense_reset = false, .has_gpu_clamps = false, }; @@ -807,6 +907,7 @@ static const struct tegra_pmc_soc tegra30_pmc_soc = { .powergates = tegra30_powergates, .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), .cpu_powergates = tegra30_cpu_powergates, + .has_tsense_reset = true, .has_gpu_clamps = false, }; @@ -843,6 +944,7 @@ static const struct tegra_pmc_soc tegra114_pmc_soc = { .powergates = tegra114_powergates, .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), .cpu_powergates = tegra114_cpu_powergates, + .has_tsense_reset = true, .has_gpu_clamps = false, }; @@ -885,6 +987,7 @@ static const struct tegra_pmc_soc tegra124_pmc_soc = { .powergates = tegra124_powergates, .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), .cpu_powergates = tegra124_cpu_powergates, + .has_tsense_reset = true, .has_gpu_clamps = true, };