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perf/events/amd/uncore: Fix amd_uncore_llc ID to use pre-defined cpu_llc_id
Current logic iterates over CPUID Fn8000001d leafs (Cache Properties) to detect the last level cache, and derive the last-level cache ID. However, this information is already available in the cpu_llc_id. Therefore, make use of it instead. Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Borislav Petkov <bp@suse.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: "Peter Zijlstra (Intel)" <peterz@infradead.org> Cc: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com> Link: http://lkml.kernel.org/r/1524864877-111962-3-git-send-email-suravee.suthikulpanit@amd.com
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@ -19,6 +19,7 @@
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#include <asm/cpufeature.h>
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#include <asm/perf_event.h>
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#include <asm/msr.h>
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#include <asm/smp.h>
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#define NUM_COUNTERS_NB 4
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#define NUM_COUNTERS_L2 4
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@ -399,26 +400,8 @@ static int amd_uncore_cpu_starting(unsigned int cpu)
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}
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if (amd_uncore_llc) {
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unsigned int apicid = cpu_data(cpu).apicid;
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unsigned int nshared, subleaf, prev_eax = 0;
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uncore = *per_cpu_ptr(amd_uncore_llc, cpu);
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/*
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* Iterate over Cache Topology Definition leaves until no
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* more cache descriptions are available.
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*/
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for (subleaf = 0; subleaf < 5; subleaf++) {
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cpuid_count(0x8000001d, subleaf, &eax, &ebx, &ecx, &edx);
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/* EAX[0:4] gives type of cache */
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if (!(eax & 0x1f))
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break;
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prev_eax = eax;
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}
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nshared = ((prev_eax >> 14) & 0xfff) + 1;
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uncore->id = apicid - (apicid % nshared);
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uncore->id = per_cpu(cpu_llc_id, cpu);
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uncore = amd_uncore_find_online_sibling(uncore, amd_uncore_llc);
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*per_cpu_ptr(amd_uncore_llc, cpu) = uncore;
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