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spi: s3c64xx: prepare for a different flavor of iowrite rep

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There are SoCs (gs101) that allow only 32 bit register accesses. As the
requirement is rare enough, for those SoCs we'll open code in the driver
some s3c64xx_iowrite{8,16}_32_rep() accessors. Prepare for such addition.

Suggested-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240207111516.2563218-3-tudor.ambarus@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Tudor Ambarus 2024-02-07 11:15:14 +00:00 committed by Mark Brown
parent ff690e75d6
commit 80d3204a3b
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
1 changed files with 21 additions and 14 deletions
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35
drivers/spi/spi-s3c64xx.c
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@ -414,6 +414,26 @@ static bool s3c64xx_spi_can_dma(struct spi_controller *host,
}
static void s3c64xx_iowrite_rep(const struct s3c64xx_spi_driver_data *sdd,
struct spi_transfer *xfer)
{
void __iomem *addr = sdd->regs + S3C64XX_SPI_TX_DATA;
const void *buf = xfer->tx_buf;
unsigned int len = xfer->len;
switch (sdd->cur_bpw) {
case 32:
iowrite32_rep(addr, buf, len / 4);
break;
case 16:
iowrite16_rep(addr, buf, len / 2);
break;
default:
iowrite8_rep(addr, buf, len);
break;
}
}
static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd,
struct spi_transfer *xfer, int dma_mode)
{
@ -447,20 +467,7 @@ static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd,
modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
ret = prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
} else {
switch (sdd->cur_bpw) {
case 32:
iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
xfer->tx_buf, xfer->len / 4);
break;
case 16:
iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
xfer->tx_buf, xfer->len / 2);
break;
default:
iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
xfer->tx_buf, xfer->len);
break;
}
s3c64xx_iowrite_rep(sdd, xfer);
}
}