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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Browse Source 
Pull MIPS updates from Ralf Baechle:
 "This is the main pull request for 4.3 for MIPS.  Here's the summary:

  Three fixes that didn't make 4.2-stable:

   - a -Os build might compile the kernel using the MIPS16 instruction
     set but the R2 optimized inline functions in <uapi/asm/swab.h> are
     implemented using 32-bit wide instructions which is invalid.

   - a build error in pgtable-bits.h for a particular kernel
     configuration.

   - accessing registers of the CM GCR might have been compiled to use
     64 bit accesses but these registers are onl 32 bit wide.

  And also a few new bits:

   - move the ATH79 GPIO driver to drivers/gpio

   - the definition of IRQCHIP_DECLARE has moved to linux/irqchip.h,
     change ATH79 accordingly.

   - fix definition of pgprot_writecombine

   - add an implementation of dma_map_ops.mmap

   - fix alignment of quiet build output for vmlinuz link

   - BCM47xx: Use kmemdup rather than duplicating its implementation

   - Netlogic: Fix 0x0x prefixes of constants.

   - merge Bjorn Helgaas' series to remove most of the weak keywords
     from function declarations.

   - CP0 and CP1 registers are best considered treated as unsigned
     values to avoid large values from becoming negative values.

   - improve support for the MIPS GIC timer.

   - enable common clock framework for Malta and SEAD3.

   - a number of improvments and fixes to dump_tlb().

   - document the MIPS TLB dump functionality in Magic SysRq.

   - Cavium Octeon CN68XX improvments.

   - NetLogic improvments.

   - irq: Use access helper irq_data_get_affinity_mask.

   - handle MSA unaligned accesses.

   - a number of R6-related math-emu fixes.

   - support for I6400.

   - improvments to MSA support.

   - add uprobes support.

   - move from deprecated __initcall to arch_initcall.

   - remove finish_arch_switch().

   - IRQ cleanups by Thomas Gleixner.

   - migrate to new 'set-state' interface.

   - random small cleanups"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (148 commits)
  MIPS: UAPI: Fix unrecognized opcode WSBH/DSBH/DSHD when using MIPS16.
  MIPS: Fix alignment of quiet build output for vmlinuz link
  MIPS: math-emu: Remove unused handle_dsemul function declaration
  MIPS: math-emu: Add support for the MIPS R6 MAX{, A} FPU instruction
  MIPS: math-emu: Add support for the MIPS R6 MIN{, A} FPU instruction
  MIPS: math-emu: Add support for the MIPS R6 CLASS FPU instruction
  MIPS: math-emu: Add support for the MIPS R6 RINT FPU instruction
  MIPS: math-emu: Add support for the MIPS R6 MSUBF FPU instruction
  MIPS: math-emu: Add support for the MIPS R6 MADDF FPU instruction
  MIPS: math-emu: Add support for the MIPS R6 SELNEZ FPU instruction
  MIPS: math-emu: Add support for the MIPS R6 SELEQZ FPU instruction
  MIPS: math-emu: Add support for the CMP.condn.fmt R6 instruction
  MIPS: inst.h: Add new MIPS R6 FPU opcodes
  MIPS: Octeon: Fix management port MII address on Kontron S1901
  MIPS: BCM47xx: Use kmemdup rather than duplicating its implementation
  STAGING: Octeon: Use common helpers for determining interface and port
  MIPS: Octeon: Support interfaces 4 and 5
  MIPS: Octeon: Set up 1:1 mapping between CN68XX PKO queues and ports
  MIPS: Octeon: Initialize CN68XX PKO
  STAGING: Octeon: Support CN68XX style WQE
  ...
This commit is contained in:
Linus Torvalds 2015-09-03 16:55:55 -07:00
commit 807249d3ad
195 changed files with 6344 additions and 2098 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
Documentation/devicetree/bindings/timer/img,pistachio-gptimer.txt Normal file
View File

@ -0,0 +1,28 @@
* Pistachio general-purpose timer based clocksource
Required properties:
- compatible: "img,pistachio-gptimer".
- reg: Address range of the timer registers.
- interrupts: An interrupt for each of the four timers
- clocks: Should contain a clock specifier for each entry in clock-names
- clock-names: Should contain the following entries:
"sys", interface clock
"slow", slow counter clock
"fast", fast counter clock
- img,cr-periph: Must contain a phandle to the peripheral control
syscon node.
Example:
timer: timer@18102000 {
compatible = "img,pistachio-gptimer";
reg = <0x18102000 0x100>;
interrupts = <GIC_SHARED 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 61 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 62 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_periph PERIPH_CLK_COUNTER_FAST>,
<&clk_periph PERIPH_CLK_COUNTER_SLOW>,
<&cr_periph SYS_CLK_TIMER>;
clock-names = "fast", "slow", "sys";
img,cr-periph = <&cr_periph>;
};

2
Documentation/features/debug/uprobes/arch-support.txt
View File

@ -22,7 +22,7 @@
| m68k: | TODO |
| metag: | TODO |
| microblaze: | TODO |
| mips: | TODO |
| mips: | ok |
| mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |

1
Documentation/sysrq.txt
View File

@ -119,6 +119,7 @@ On all - write a character to /proc/sysrq-trigger. e.g.:
'x' - Used by xmon interface on ppc/powerpc platforms.
Show global PMU Registers on sparc64.
Dump all TLB entries on MIPS.
'y' - Show global CPU Registers [SPARC-64 specific]

25
arch/mips/Kconfig
View File

@ -1,8 +1,10 @@
config MIPS
bool
default y
select ARCH_SUPPORTS_UPROBES
select ARCH_MIGHT_HAVE_PC_PARPORT
select ARCH_MIGHT_HAVE_PC_SERIO
select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
select HAVE_CONTEXT_TRACKING
select HAVE_GENERIC_DMA_COHERENT
select HAVE_IDE
@ -13,7 +15,6 @@ config MIPS
select HAVE_ARCH_SECCOMP_FILTER
select HAVE_ARCH_TRACEHOOK
select HAVE_BPF_JIT if !CPU_MICROMIPS
select ARCH_HAVE_CUSTOM_GPIO_H
select HAVE_FUNCTION_TRACER
select HAVE_DYNAMIC_FTRACE
select HAVE_FTRACE_MCOUNT_RECORD
@ -409,6 +410,7 @@ config MIPS_MALTA
select CEVT_R4K
select CSRC_R4K
select CLKSRC_MIPS_GIC
select COMMON_CLK
select DMA_MAYBE_COHERENT
select GENERIC_ISA_DMA
select HAVE_PCSPKR_PLATFORM
@ -459,6 +461,7 @@ config MIPS_SEAD3
select CEVT_R4K
select CSRC_R4K
select CLKSRC_MIPS_GIC
select COMMON_CLK
select CPU_MIPSR2_IRQ_VI
select CPU_MIPSR2_IRQ_EI
select DMA_NONCOHERENT
@ -899,6 +902,7 @@ config NLM_XLP_BOARD
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select ARCH_PHYS_ADDR_T_64BIT
select ARCH_REQUIRE_GPIOLIB
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_HIGHMEM
@ -948,6 +952,7 @@ source "arch/mips/jazz/Kconfig"
source "arch/mips/jz4740/Kconfig"
source "arch/mips/lantiq/Kconfig"
source "arch/mips/lasat/Kconfig"
source "arch/mips/pistachio/Kconfig"
source "arch/mips/pmcs-msp71xx/Kconfig"
source "arch/mips/ralink/Kconfig"
source "arch/mips/sgi-ip27/Kconfig"
@ -1041,6 +1046,9 @@ config FW_CFE
config ARCH_DMA_ADDR_T_64BIT
def_bool (HIGHMEM && ARCH_PHYS_ADDR_T_64BIT) || 64BIT
config ARCH_SUPPORTS_UPROBES
bool
config DMA_MAYBE_COHERENT
select DMA_NONCOHERENT
bool
@ -1364,7 +1372,7 @@ config CPU_MIPS32_R2
otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
config CPU_MIPS32_R6
bool "MIPS32 Release 6 (EXPERIMENTAL)"
bool "MIPS32 Release 6"
depends on SYS_HAS_CPU_MIPS32_R6
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
@ -1415,7 +1423,7 @@ config CPU_MIPS64_R2
otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
config CPU_MIPS64_R6
bool "MIPS64 Release 6 (EXPERIMENTAL)"
bool "MIPS64 Release 6"
depends on SYS_HAS_CPU_MIPS64_R6
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
@ -1965,6 +1973,7 @@ config 32BIT
select TRAD_SIGNALS
help
Select this option if you want to build a 32-bit kernel.
config 64BIT
bool "64-bit kernel"
depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
@ -2110,7 +2119,7 @@ config CPU_R4K_CACHE_TLB
config MIPS_MT_SMP
bool "MIPS MT SMP support (1 TC on each available VPE)"
depends on SYS_SUPPORTS_MULTITHREADING
depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6
select CPU_MIPSR2_IRQ_VI
select CPU_MIPSR2_IRQ_EI
select SYNC_R4K
@ -2211,7 +2220,7 @@ config MIPS_VPE_APSP_API_MT
config MIPS_CMP
bool "MIPS CMP framework support (DEPRECATED)"
depends on SYS_SUPPORTS_MIPS_CMP
depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
select MIPS_GIC_IPI
select SMP
select SYNC_R4K
@ -2228,7 +2237,7 @@ config MIPS_CMP
config MIPS_CPS
bool "MIPS Coherent Processing System support"
depends on SYS_SUPPORTS_MIPS_CPS
depends on SYS_SUPPORTS_MIPS_CPS && !CPU_MIPSR6
select MIPS_CM
select MIPS_CPC
select MIPS_CPS_PM if HOTPLUG_CPU
@ -2303,7 +2312,7 @@ config CPU_MICROMIPS
endchoice
config CPU_HAS_MSA
bool "Support for the MIPS SIMD Architecture (EXPERIMENTAL)"
bool "Support for the MIPS SIMD Architecture"
depends on CPU_SUPPORTS_MSA
depends on 64BIT || MIPS_O32_FP64_SUPPORT
help
@ -2643,7 +2652,7 @@ config SECCOMP
If unsure, say Y. Only embedded should say N here.
config MIPS_O32_FP64_SUPPORT
bool "Support for O32 binaries using 64-bit FP (EXPERIMENTAL)"
bool "Support for O32 binaries using 64-bit FP"
depends on 32BIT || MIPS32_O32
help
When this is enabled, the kernel will support use of 64-bit floating

9
arch/mips/Kconfig.debug
View File

@ -87,15 +87,6 @@ config SB1XXX_CORELIS
Select compile flags that produce code that can be processed by the
Corelis mksym utility and UDB Emulator.
config RUNTIME_DEBUG
bool "Enable run-time debugging"
depends on DEBUG_KERNEL
help
If you say Y here, some debugging macros will do run-time checking.
If you say N here, those macros will mostly turn to no-ops. See
arch/mips/include/asm/debug.h for debugging macros.
If unsure, say N.
config DEBUG_ZBOOT
bool "Enable compressed kernel support debugging"
depends on DEBUG_KERNEL && SYS_SUPPORTS_ZBOOT

7
arch/mips/alchemy/Kconfig
View File

@ -6,13 +6,6 @@ config ALCHEMY_GPIOINT_AU1000
config ALCHEMY_GPIOINT_AU1300
bool
# select this in your board config if you don't want to use the gpio
# namespace as documented in the manuals. In this case however you need
# to create the necessary gpio_* functions in your board code/headers!
# see arch/mips/include/asm/mach-au1x00/gpio.h for more information.
config ALCHEMY_GPIO_INDIRECT
def_bool n
choice
prompt "Machine type"
depends on MIPS_ALCHEMY

1
arch/mips/alchemy/board-gpr.c
View File

@ -34,6 +34,7 @@
#include <asm/idle.h>
#include <asm/reboot.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/gpio-au1000.h>
#include <prom.h>
const char *get_system_type(void)

1
arch/mips/alchemy/board-mtx1.c
View File

@ -32,6 +32,7 @@
#include <asm/bootinfo.h>
#include <asm/reboot.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/gpio-au1000.h>
#include <asm/mach-au1x00/au1xxx_eth.h>
#include <prom.h>

7
arch/mips/alchemy/common/Makefile
View File

@ -5,10 +5,5 @@
# Makefile for the Alchemy Au1xx0 CPUs, generic files.
#
obj-y += prom.o time.o clock.o platform.o power.o \
obj-y += prom.o time.o clock.o platform.o power.o gpiolib.o \
setup.o sleeper.o dma.o dbdma.o vss.o irq.o usb.o
# optional gpiolib support
ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)
obj-$(CONFIG_GPIOLIB) += gpiolib.o
endif

4
arch/mips/alchemy/common/irq.c
View File

@ -491,7 +491,7 @@ static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type)
default:
ret = -EINVAL;
}
__irq_set_chip_handler_name_locked(d->irq, chip, handler, name);
irq_set_chip_handler_name_locked(d, chip, handler, name);
wmb();
@ -703,7 +703,7 @@ static int au1300_gpic_settype(struct irq_data *d, unsigned int type)
return -EINVAL;
}
__irq_set_chip_handler_name_locked(d->irq, &au1300_gpic, hdl, name);
irq_set_chip_handler_name_locked(d, &au1300_gpic, hdl, name);
au1300_gpic_chgcfg(d->irq - ALCHEMY_GPIC_INT_BASE, GPIC_CFG_IC_MASK, s);

6
arch/mips/alchemy/common/time.c
View File

@ -69,11 +69,6 @@ static int au1x_rtcmatch2_set_next_event(unsigned long delta,
return 0;
}
static void au1x_rtcmatch2_set_mode(enum clock_event_mode mode,
struct clock_event_device *cd)
{
}
static irqreturn_t au1x_rtcmatch2_irq(int irq, void *dev_id)
{
struct clock_event_device *cd = dev_id;
@ -86,7 +81,6 @@ static struct clock_event_device au1x_rtcmatch2_clockdev = {
.features = CLOCK_EVT_FEAT_ONESHOT,
.rating = 1500,
.set_next_event = au1x_rtcmatch2_set_next_event,
.set_mode = au1x_rtcmatch2_set_mode,
.cpumask = cpu_all_mask,
};

6
arch/mips/alchemy/devboards/bcsr.c
View File

@ -8,6 +8,7 @@
*/
#include <linux/interrupt.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/irq.h>
@ -88,10 +89,11 @@ EXPORT_SYMBOL_GPL(bcsr_mod);
static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d)
{
unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT);
struct irq_chip *chip = irq_desc_get_chip(d);
disable_irq_nosync(irq);
chained_irq_enter(chip, d);
generic_handle_irq(bcsr_csc_base + __ffs(bisr));
enable_irq(irq);
chained_irq_exit(chip, d);
}
static void bcsr_irq_mask(struct irq_data *d)

1
arch/mips/alchemy/devboards/db1000.c
View File

@ -33,6 +33,7 @@
#include <linux/spi/spi_gpio.h>
#include <linux/spi/ads7846.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/gpio-au1000.h>
#include <asm/mach-au1x00/au1000_dma.h>
#include <asm/mach-au1x00/au1100_mmc.h>
#include <asm/mach-db1x00/bcsr.h>

1
arch/mips/alchemy/devboards/db1300.c
View File

@ -24,6 +24,7 @@
#include <linux/wm97xx.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/gpio-au1300.h>
#include <asm/mach-au1x00/au1100_mmc.h>
#include <asm/mach-au1x00/au1200fb.h>
#include <asm/mach-au1x00/au1xxx_dbdma.h>

1
arch/mips/alchemy/devboards/db1550.c
View File

@ -20,6 +20,7 @@
#include <linux/spi/flash.h>
#include <asm/bootinfo.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/gpio-au1000.h>
#include <asm/mach-au1x00/au1xxx_eth.h>
#include <asm/mach-au1x00/au1xxx_dbdma.h>
#include <asm/mach-au1x00/au1xxx_psc.h>

2
arch/mips/alchemy/devboards/pm.c
View File

@ -9,7 +9,7 @@
#include <linux/suspend.h>
#include <linux/sysfs.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/gpio.h>
#include <asm/mach-au1x00/gpio-au1000.h>
#include <asm/mach-db1x00/bcsr.h>
/*

5
arch/mips/ar7/gpio.c
View File

@ -21,7 +21,10 @@
#include <linux/module.h>
#include <linux/gpio.h>
#include <asm/mach-ar7/gpio.h>
#include <asm/mach-ar7/ar7.h>
#define AR7_GPIO_MAX 32
#define TITAN_GPIO_MAX 51
struct ar7_gpio_chip {
void __iomem *regs;

1
arch/mips/ar7/platform.c
View File

@ -39,7 +39,6 @@
#include <asm/addrspace.h>
#include <asm/mach-ar7/ar7.h>
#include <asm/mach-ar7/gpio.h>
#include <asm/mach-ar7/prom.h>
/*****************************************************************************

1
arch/mips/ar7/setup.c
View File

@ -23,7 +23,6 @@
#include <asm/reboot.h>
#include <asm/mach-ar7/ar7.h>
#include <asm/mach-ar7/prom.h>
#include <asm/mach-ar7/gpio.h>
static void ar7_machine_restart(char *command)
{

2
arch/mips/ath79/Makefile
View File

@ -8,7 +8,7 @@
# under the terms of the GNU General Public License version 2 as published
# by the Free Software Foundation.
obj-y := prom.o setup.o irq.o common.o clock.o gpio.o
obj-y := prom.o setup.o irq.o common.o clock.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
obj-$(CONFIG_PCI) += pci.o

3
arch/mips/ath79/common.h
View File

@ -25,9 +25,6 @@ unsigned long ath79_get_sys_clk_rate(const char *id);
void ath79_ddr_ctrl_init(void);
void ath79_ddr_wb_flush(unsigned int reg);
void ath79_gpio_function_enable(u32 mask);
void ath79_gpio_function_disable(u32 mask);
void ath79_gpio_function_setup(u32 set, u32 clear);
void ath79_gpio_init(void);
#endif /* __ATH79_COMMON_H */

18
arch/mips/ath79/irq.c
View File

@ -123,8 +123,6 @@ static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
{
u32 status;
disable_irq_nosync(irq);
status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
@ -136,8 +134,6 @@ static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
} else {
spurious_interrupt();
}
enable_irq(irq);
}
static void ar934x_ip2_irq_init(void)
@ -156,14 +152,12 @@ static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
{
u32 status;
disable_irq_nosync(irq);
status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL;
if (status == 0) {
spurious_interrupt();
goto enable;
return;
}
if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) {
@ -175,17 +169,12 @@ static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
/* TODO: flush DDR? */
generic_handle_irq(ATH79_IP2_IRQ(1));
}
enable:
enable_irq(irq);
}
static void qca955x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc)
{
u32 status;
disable_irq_nosync(irq);
status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
status &= QCA955X_EXT_INT_PCIE_RC2_ALL |
QCA955X_EXT_INT_USB1 |
@ -193,7 +182,7 @@ static void qca955x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc)
if (status == 0) {
spurious_interrupt();
goto enable;
return;
}
if (status & QCA955X_EXT_INT_USB1) {
@ -210,9 +199,6 @@ static void qca955x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc)
/* TODO: flush DDR? */
generic_handle_irq(ATH79_IP3_IRQ(2));
}
enable:
enable_irq(irq);
}
static void qca955x_irq_init(void)

3
arch/mips/bcm47xx/buttons.c
View File

@ -396,10 +396,9 @@ static int __init bcm47xx_buttons_copy(const struct gpio_keys_button *buttons,
{
size_t size = nbuttons * sizeof(*buttons);
bcm47xx_button_pdata.buttons = kmalloc(size, GFP_KERNEL);
bcm47xx_button_pdata.buttons = kmemdup(buttons, size, GFP_KERNEL);
if (!bcm47xx_button_pdata.buttons)
return -ENOMEM;
memcpy(bcm47xx_button_pdata.buttons, buttons, size);
bcm47xx_button_pdata.nbuttons = nbuttons;
return 0;

6
arch/mips/bcm63xx/irq.c
View File

@ -60,7 +60,7 @@ static inline int enable_irq_for_cpu(int cpu, struct irq_data *d,
if (m)
enable &= cpumask_test_cpu(cpu, m);
else if (irqd_affinity_was_set(d))
enable &= cpumask_test_cpu(cpu, d->affinity);
enable &= cpumask_test_cpu(cpu, irq_data_get_affinity_mask(d));
#endif
return enable;
}
@ -365,9 +365,9 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d,
irqd_set_trigger_type(d, flow_type);
if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
__irq_set_handler_locked(d->irq, handle_level_irq);
irq_set_handler_locked(d, handle_level_irq);
else
__irq_set_handler_locked(d->irq, handle_edge_irq);
irq_set_handler_locked(d, handle_edge_irq);
return IRQ_SET_MASK_OK_NOCOPY;
}

2
arch/mips/boot/compressed/Makefile
View File

@ -78,7 +78,7 @@ endif
vmlinuzobjs-y += $(obj)/piggy.o
quiet_cmd_zld = LD $@
quiet_cmd_zld = LD $@
cmd_zld = $(LD) $(LDFLAGS) -Ttext $(VMLINUZ_LOAD_ADDRESS) -T $< $(vmlinuzobjs-y) -o $@
quiet_cmd_strip = STRIP $@
cmd_strip = $(STRIP) -s $@

12
arch/mips/boot/dts/netlogic/xlp_evp.dts
View File

@ -110,6 +110,18 @@
read-only;
};
};
gpio: xlp_gpio@34100 {
compatible = "netlogic,xlp832-gpio";
reg = <0 0x34100 0x1000>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-parent = <&pic>;
interrupts = <39>;
interrupt-controller;
};
};
chosen {

12
arch/mips/boot/dts/netlogic/xlp_fvp.dts
View File

@ -110,6 +110,18 @@
read-only;
};
};
gpio: xlp_gpio@34100 {
compatible = "netlogic,xlp208-gpio";
reg = <0 0x34100 0x1000>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-parent = <&pic>;
interrupts = <39>;
interrupt-controller;
};
};
chosen {

11
arch/mips/boot/dts/netlogic/xlp_gvp.dts
View File

@ -69,6 +69,17 @@
};
};
gpio: xlp_gpio@114100 {
compatible = "netlogic,xlp980-gpio";
reg = <0 0x114100 0x1000>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-parent = <&pic>;
interrupts = <39>;
interrupt-controller;
};
};
chosen {

11
arch/mips/boot/dts/netlogic/xlp_rvp.dts
View File

@ -69,6 +69,17 @@
};
};
gpio: xlp_gpio@114100 {
compatible = "netlogic,xlp532-gpio";
reg = <0 0x114100 0x1000>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-parent = <&pic>;
interrupts = <39>;
interrupt-controller;
};
};
chosen {

12
arch/mips/boot/dts/netlogic/xlp_svp.dts
View File

@ -110,6 +110,18 @@
read-only;
};
};
gpio: xlp_gpio@34100 {
compatible = "netlogic,xlp316-gpio";
reg = <0 0x34100 0x1000>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-parent = <&pic>;
interrupts = <39>;
interrupt-controller;
};
};
chosen {

6
arch/mips/cavium-octeon/executive/cvmx-helper-board.c
View File

@ -195,6 +195,12 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
return 8;
else
return -1;
case CVMX_BOARD_TYPE_KONTRON_S1901:
if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT)
return 1;
else
return -1;
}
/* Some unknown board. Somebody forgot to update this function... */

20
arch/mips/cavium-octeon/executive/cvmx-helper-util.c
View File

@ -95,9 +95,9 @@ int cvmx_helper_dump_packet(cvmx_wqe_t *work)
uint8_t *data_address;
uint8_t *end_of_data;
cvmx_dprintf("Packet Length: %u\n", work->len);
cvmx_dprintf(" Input Port: %u\n", work->ipprt);
cvmx_dprintf(" QoS: %u\n", work->qos);
cvmx_dprintf("Packet Length: %u\n", work->word1.len);
cvmx_dprintf(" Input Port: %u\n", cvmx_wqe_get_port(work));
cvmx_dprintf(" QoS: %u\n", cvmx_wqe_get_qos(work));
cvmx_dprintf(" Buffers: %u\n", work->word2.s.bufs);
if (work->word2.s.bufs == 0) {
@ -127,7 +127,7 @@ int cvmx_helper_dump_packet(cvmx_wqe_t *work)
}
} else
buffer_ptr = work->packet_ptr;
remaining_bytes = work->len;
remaining_bytes = work->word1.len;
while (remaining_bytes) {
start_of_buffer =
@ -382,6 +382,10 @@ int cvmx_helper_get_ipd_port(int interface, int port)
return port + 32;
case 3:
return port + 36;
case 4:
return port + 40;
case 5:
return port + 44;
}
return -1;
}
@ -404,6 +408,10 @@ int cvmx_helper_get_interface_num(int ipd_port)
return 2;
else if (ipd_port < 40)
return 3;
else if (ipd_port < 44)
return 4;
else if (ipd_port < 48)
return 5;
else
cvmx_dprintf("cvmx_helper_get_interface_num: Illegal IPD "
"port number\n");
@ -428,6 +436,10 @@ int cvmx_helper_get_interface_index_num(int ipd_port)
return ipd_port & 3;
else if (ipd_port < 40)
return ipd_port & 3;
else if (ipd_port < 44)
return ipd_port & 3;
else if (ipd_port < 48)
return ipd_port & 3;
else
cvmx_dprintf("cvmx_helper_get_interface_index_num: "
"Illegal IPD port number\n");

14
arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
View File

@ -124,6 +124,13 @@ int __cvmx_helper_xaui_enable(int interface)
union cvmx_gmxx_tx_int_en gmx_tx_int_en;
union cvmx_pcsxx_int_en_reg pcsx_int_en_reg;
/* Setup PKND */
if (octeon_has_feature(OCTEON_FEATURE_PKND)) {
gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
gmx_cfg.s.pknd = cvmx_helper_get_ipd_port(interface, 0);
cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
}
/* (1) Interface has already been enabled. */
/* (2) Disable GMX. */
@ -151,7 +158,12 @@ int __cvmx_helper_xaui_enable(int interface)
/* (4)c Aply reset sequence */
xauiCtl.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));
xauiCtl.s.lo_pwr = 0;
xauiCtl.s.reset = 1;
/* Issuing a reset here seems to hang some CN68XX chips. */
if (!OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_X) &&
!OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2_X))
xauiCtl.s.reset = 1;
cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), xauiCtl.u64);
/* Wait for PCS to come out of reset */

17
arch/mips/cavium-octeon/executive/cvmx-helper.c
View File

@ -83,6 +83,8 @@ static cvmx_helper_link_info_t
*/
int cvmx_helper_get_number_of_interfaces(void)
{
if (OCTEON_IS_MODEL(OCTEON_CN68XX))
return 9;
if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
return 4;
else
@ -656,6 +658,21 @@ static int __cvmx_helper_global_setup_pko(void)
fau_to.s.tout_val = 0xfff;
fau_to.s.tout_enb = 0;
cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_to.u64);
if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
union cvmx_pko_reg_min_pkt min_pkt;
min_pkt.u64 = 0;
min_pkt.s.size1 = 59;
min_pkt.s.size2 = 59;
min_pkt.s.size3 = 59;
min_pkt.s.size4 = 59;
min_pkt.s.size5 = 59;
min_pkt.s.size6 = 59;
min_pkt.s.size7 = 59;
cvmx_write_csr(CVMX_PKO_REG_MIN_PKT, min_pkt.u64);
}
return 0;
}

149
arch/mips/cavium-octeon/executive/cvmx-pko.c
View File

@ -39,6 +39,143 @@
* Internal state of packet output
*/
static int __cvmx_pko_int(int interface, int index)
{
switch (interface) {
case 0:
return index;
case 1:
return 4;
case 2:
return index + 0x08;
case 3:
return index + 0x0c;
case 4:
return index + 0x10;
case 5:
return 0x1c;
case 6:
return 0x1d;
case 7:
return 0x1e;
case 8:
return 0x1f;
default:
return -1;
}
}
static void __cvmx_pko_iport_config(int pko_port)
{
int queue;
const int num_queues = 1;
const int base_queue = pko_port;
const int static_priority_end = 1;
const int static_priority_base = 1;
for (queue = 0; queue < num_queues; queue++) {
union cvmx_pko_mem_iqueue_ptrs config;
cvmx_cmd_queue_result_t cmd_res;
uint64_t *buf_ptr;
config.u64 = 0;
config.s.index = queue;
config.s.qid = base_queue + queue;
config.s.ipid = pko_port;
config.s.tail = (queue == (num_queues - 1));
config.s.s_tail = (queue == static_priority_end);
config.s.static_p = (static_priority_base >= 0);
config.s.static_q = (queue <= static_priority_end);
config.s.qos_mask = 0xff;
cmd_res = cvmx_cmd_queue_initialize(
CVMX_CMD_QUEUE_PKO(base_queue + queue),
CVMX_PKO_MAX_QUEUE_DEPTH,
CVMX_FPA_OUTPUT_BUFFER_POOL,
(CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE -
CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST * 8));
WARN(cmd_res,
"%s: cmd_res=%d pko_port=%d base_queue=%d num_queues=%d queue=%d\n",
__func__, (int)cmd_res, pko_port, base_queue,
num_queues, queue);
buf_ptr = (uint64_t *)cvmx_cmd_queue_buffer(
CVMX_CMD_QUEUE_PKO(base_queue + queue));
config.s.buf_ptr = cvmx_ptr_to_phys(buf_ptr) >> 7;
CVMX_SYNCWS;
cvmx_write_csr(CVMX_PKO_MEM_IQUEUE_PTRS, config.u64);
}
}
static void __cvmx_pko_queue_alloc_o68(void)
{
int port;
for (port = 0; port < 48; port++)
__cvmx_pko_iport_config(port);
}
static void __cvmx_pko_port_map_o68(void)
{
int port;
int interface, index;
cvmx_helper_interface_mode_t mode;
union cvmx_pko_mem_iport_ptrs config;
/*
* Initialize every iport with the invalid eid.
*/
config.u64 = 0;
config.s.eid = 31; /* Invalid */
for (port = 0; port < 128; port++) {
config.s.ipid = port;
cvmx_write_csr(CVMX_PKO_MEM_IPORT_PTRS, config.u64);
}
/*
* Set up PKO_MEM_IPORT_PTRS
*/
for (port = 0; port < 48; port++) {
interface = cvmx_helper_get_interface_num(port);
index = cvmx_helper_get_interface_index_num(port);
mode = cvmx_helper_interface_get_mode(interface);
if (mode == CVMX_HELPER_INTERFACE_MODE_DISABLED)
continue;
config.s.ipid = port;
config.s.qos_mask = 0xff;
config.s.crc = 1;
config.s.min_pkt = 1;
config.s.intr = __cvmx_pko_int(interface, index);
config.s.eid = config.s.intr;
config.s.pipe = (mode == CVMX_HELPER_INTERFACE_MODE_LOOP) ?
index : port;
cvmx_write_csr(CVMX_PKO_MEM_IPORT_PTRS, config.u64);
}
}
static void __cvmx_pko_chip_init(void)
{
int i;
if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
__cvmx_pko_port_map_o68();
__cvmx_pko_queue_alloc_o68();
return;
}
/*
* Initialize queues
*/
for (i = 0; i < CVMX_PKO_MAX_OUTPUT_QUEUES; i++) {
const uint64_t priority = 8;
cvmx_pko_config_port(CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID, i, 1,
&priority);
}
}
/**
* Call before any other calls to initialize the packet
* output system. This does chip global config, and should only be
@ -47,8 +184,6 @@
void cvmx_pko_initialize_global(void)
{
int i;
uint64_t priority = 8;
union cvmx_pko_reg_cmd_buf config;
/*
@ -62,9 +197,10 @@ void cvmx_pko_initialize_global(void)
cvmx_write_csr(CVMX_PKO_REG_CMD_BUF, config.u64);
for (i = 0; i < CVMX_PKO_MAX_OUTPUT_QUEUES; i++)
cvmx_pko_config_port(CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID, i, 1,
&priority);
/*
* Chip-specific setup.
*/
__cvmx_pko_chip_init();
/*
* If we aren't using all of the queues optimize PKO's
@ -212,6 +348,9 @@ cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue,
int static_priority_base = -1;
int static_priority_end = -1;
if (OCTEON_IS_MODEL(OCTEON_CN68XX))
return CVMX_PKO_SUCCESS;
if ((port >= CVMX_PKO_NUM_OUTPUT_PORTS)
&& (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID)) {
cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid port %llu\n",

36
arch/mips/cavium-octeon/octeon-irq.c
View File

@ -225,13 +225,14 @@ static int next_cpu_for_irq(struct irq_data *data)
#ifdef CONFIG_SMP
int cpu;
int weight = cpumask_weight(data->affinity);
struct cpumask *mask = irq_data_get_affinity_mask(data);
int weight = cpumask_weight(mask);
struct octeon_ciu_chip_data *cd = irq_data_get_irq_chip_data(data);
if (weight > 1) {
cpu = cd->current_cpu;
for (;;) {
cpu = cpumask_next(cpu, data->affinity);
cpu = cpumask_next(cpu, mask);
if (cpu >= nr_cpu_ids) {
cpu = -1;
continue;
@ -240,7 +241,7 @@ static int next_cpu_for_irq(struct irq_data *data)
}
}
} else if (weight == 1) {
cpu = cpumask_first(data->affinity);
cpu = cpumask_first(mask);
} else {
cpu = smp_processor_id();
}
@ -662,6 +663,11 @@ static int octeon_irq_ciu_gpio_set_type(struct irq_data *data, unsigned int t)
irqd_set_trigger_type(data, t);
octeon_irq_gpio_setup(data);
if (irqd_get_trigger_type(data) & IRQ_TYPE_EDGE_BOTH)
irq_set_handler_locked(data, handle_edge_irq);
else
irq_set_handler_locked(data, handle_level_irq);
return IRQ_SET_MASK_OK;
}
@ -696,32 +702,23 @@ static void octeon_irq_ciu_gpio_ack(struct irq_data *data)
cvmx_write_csr(CVMX_GPIO_INT_CLR, mask);
}
static void octeon_irq_handle_trigger(unsigned int irq, struct irq_desc *desc)
{
struct irq_data *data = irq_desc_get_irq_data(desc);
if (irqd_get_trigger_type(data) & IRQ_TYPE_EDGE_BOTH)
handle_edge_irq(irq, desc);
else
handle_level_irq(irq, desc);
}
#ifdef CONFIG_SMP
static void octeon_irq_cpu_offline_ciu(struct irq_data *data)
{
int cpu = smp_processor_id();
cpumask_t new_affinity;
struct cpumask *mask = irq_data_get_affinity_mask(data);
if (!cpumask_test_cpu(cpu, data->affinity))
if (!cpumask_test_cpu(cpu, mask))
return;
if (cpumask_weight(data->affinity) > 1) {
if (cpumask_weight(mask) > 1) {
/*
* It has multi CPU affinity, just remove this CPU
* from the affinity set.
*/
cpumask_copy(&new_affinity, data->affinity);
cpumask_copy(&new_affinity, mask);
cpumask_clear_cpu(cpu, &new_affinity);
} else {
/* Otherwise, put it on lowest numbered online CPU. */
@ -1227,8 +1224,13 @@ static int octeon_irq_gpio_map(struct irq_domain *d,
octeon_irq_ciu_to_irq[line][bit] != 0)
return -EINVAL;
/*
* Default to handle_level_irq. If the DT contains a different
* trigger type, it will call the irq_set_type callback and
* the handler gets updated.
*/
r = octeon_irq_set_ciu_mapping(virq, line, bit, hw,
octeon_irq_gpio_chip, octeon_irq_handle_trigger);
octeon_irq_gpio_chip, handle_level_irq);
return r;
}

1
arch/mips/include/asm/Kbuild
View File

@ -16,6 +16,5 @@ generic-y += sections.h
generic-y += segment.h
generic-y += serial.h
generic-y += trace_clock.h
generic-y += ucontext.h
generic-y += user.h
generic-y += xor.h

4
arch/mips/include/asm/abi.h
View File

@ -20,6 +20,10 @@ struct mips_abi {
struct pt_regs *regs, sigset_t *set);
const unsigned long rt_signal_return_offset;
const unsigned long restart;
unsigned off_sc_fpregs;
unsigned off_sc_fpc_csr;
unsigned off_sc_used_math;
};
#endif /* _ASM_ABI_H */

114
arch/mips/include/asm/asmmacro.h
View File

@ -232,6 +232,30 @@
.set pop
.endm
.macro ld_b wd, off, base
.set push
.set mips32r2
.set msa
ld.b $w\wd, \off(\base)
.set pop
.endm
.macro ld_h wd, off, base
.set push
.set mips32r2
.set msa
ld.h $w\wd, \off(\base)
.set pop
.endm
.macro ld_w wd, off, base
.set push
.set mips32r2
.set msa
ld.w $w\wd, \off(\base)
.set pop
.endm
.macro ld_d wd, off, base
.set push
.set mips32r2
@ -241,6 +265,30 @@
.set pop
.endm
.macro st_b wd, off, base
.set push
.set mips32r2
.set msa
st.b $w\wd, \off(\base)
.set pop
.endm
.macro st_h wd, off, base
.set push
.set mips32r2
.set msa
st.h $w\wd, \off(\base)
.set pop
.endm
.macro st_w wd, off, base
.set push
.set mips32r2
.set msa
st.w $w\wd, \off(\base)
.set pop
.endm
.macro st_d wd, off, base
.set push
.set mips32r2
@ -290,7 +338,13 @@
#ifdef CONFIG_CPU_MICROMIPS
#define CFC_MSA_INSN 0x587e0056
#define CTC_MSA_INSN 0x583e0816
#define LDB_MSA_INSN 0x58000807
#define LDH_MSA_INSN 0x58000817
#define LDW_MSA_INSN 0x58000827
#define LDD_MSA_INSN 0x58000837
#define STB_MSA_INSN 0x5800080f
#define STH_MSA_INSN 0x5800081f
#define STW_MSA_INSN 0x5800082f
#define STD_MSA_INSN 0x5800083f
#define COPY_UW_MSA_INSN 0x58f00056
#define COPY_UD_MSA_INSN 0x58f80056
@ -299,7 +353,13 @@
#else
#define CFC_MSA_INSN 0x787e0059
#define CTC_MSA_INSN 0x783e0819
#define LDB_MSA_INSN 0x78000820
#define LDH_MSA_INSN 0x78000821
#define LDW_MSA_INSN 0x78000822
#define LDD_MSA_INSN 0x78000823
#define STB_MSA_INSN 0x78000824
#define STH_MSA_INSN 0x78000825
#define STW_MSA_INSN 0x78000826
#define STD_MSA_INSN 0x78000827
#define COPY_UW_MSA_INSN 0x78f00059
#define COPY_UD_MSA_INSN 0x78f80059
@ -329,6 +389,33 @@
.set pop
.endm
.macro ld_b wd, off, base
.set push
.set noat
SET_HARDFLOAT
addu $1, \base, \off
.word LDB_MSA_INSN | (\wd << 6)
.set pop
.endm
.macro ld_h wd, off, base
.set push
.set noat
SET_HARDFLOAT
addu $1, \base, \off
.word LDH_MSA_INSN | (\wd << 6)
.set pop
.endm
.macro ld_w wd, off, base
.set push
.set noat
SET_HARDFLOAT
addu $1, \base, \off
.word LDW_MSA_INSN | (\wd << 6)
.set pop
.endm
.macro ld_d wd, off, base
.set push
.set noat
@ -338,6 +425,33 @@
.set pop
.endm
.macro st_b wd, off, base
.set push
.set noat
SET_HARDFLOAT
addu $1, \base, \off
.word STB_MSA_INSN | (\wd << 6)
.set pop
.endm
.macro st_h wd, off, base
.set push
.set noat
SET_HARDFLOAT
addu $1, \base, \off
.word STH_MSA_INSN | (\wd << 6)
.set pop
.endm
.macro st_w wd, off, base
.set push
.set noat
SET_HARDFLOAT
addu $1, \base, \off
.word STW_MSA_INSN | (\wd << 6)
.set pop
.endm
.macro st_d wd, off, base
.set push
.set noat

4
arch/mips/include/asm/cdmm.h
View File

@ -53,7 +53,7 @@ struct mips_cdmm_driver {
* mips_cdmm_phys_base() - Choose a physical base address for CDMM region.
*
* Picking a suitable physical address at which to map the CDMM region is
* platform specific, so this weak function can be defined by platform code to
* platform specific, so this function can be defined by platform code to
* pick a suitable value if none is configured by the bootloader.
*
* This address must be 32kB aligned, and the region occupies a maximum of 32kB
@ -61,7 +61,7 @@ struct mips_cdmm_driver {
*
* Returns: Physical base address for CDMM region, or 0 on failure.
*/
phys_addr_t __weak mips_cdmm_phys_base(void);
phys_addr_t mips_cdmm_phys_base(void);
extern struct bus_type mips_cdmm_bustype;
void __iomem *mips_cdmm_early_probe(unsigned int dev_type);

1
arch/mips/include/asm/cevt-r4k.h
View File

@ -21,7 +21,6 @@ DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device);
void mips_event_handler(struct clock_event_device *dev);
int c0_compare_int_usable(void);
void mips_set_clock_mode(enum clock_event_mode, struct clock_event_device *);
irqreturn_t c0_compare_interrupt(int, void *);
extern struct irqaction c0_compare_irqaction;

4
arch/mips/include/asm/cpu-features.h
View File

@ -411,4 +411,8 @@
# define cpu_has_cdmm (cpu_data[0].options & MIPS_CPU_CDMM)
#endif
#ifndef cpu_has_small_pages
# define cpu_has_small_pages (cpu_data[0].options & MIPS_CPU_SP)
#endif
#endif /* __ASM_CPU_FEATURES_H */

4
arch/mips/include/asm/cpu-type.h
View File

@ -77,6 +77,10 @@ static inline int __pure __get_cpu_type(const int cpu_type)
*/
#endif
#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R6
case CPU_I6400:
#endif
#ifdef CONFIG_SYS_HAS_CPU_R3000
case CPU_R2000:
case CPU_R3000:

3
arch/mips/include/asm/cpu.h
View File

@ -120,6 +120,7 @@
#define PRID_IMP_PROAPTIV_MP 0xa300
#define PRID_IMP_M5150 0xa700
#define PRID_IMP_P5600 0xa800
#define PRID_IMP_I6400 0xa900
/*
* These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
@ -307,6 +308,7 @@ enum cpu_type_enum {
CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K, CPU_M5150,
CPU_I6400,
/*
* MIPS64 class processors
@ -382,6 +384,7 @@ enum cpu_type_enum {
#define MIPS_CPU_XPA 0x2000000000ull /* CPU supports Extended Physical Addressing */
#define MIPS_CPU_CDMM 0x4000000000ull /* CPU has Common Device Memory Map */
#define MIPS_CPU_BP_GHIST 0x8000000000ull /* R12K+ Branch Prediction Global History */
#define MIPS_CPU_SP 0x10000000000ull /* Small (1KB) page support */
/*
* CPU ASE encodings

48
arch/mips/include/asm/debug.h
View File

@ -1,48 +0,0 @@
/*
* Debug macros for run-time debugging.
* Turned on/off with CONFIG_RUNTIME_DEBUG option.
*
* Copyright (C) 2001 MontaVista Software Inc.
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef _ASM_DEBUG_H
#define _ASM_DEBUG_H
/*
* run-time macros for catching spurious errors. Eable CONFIG_RUNTIME_DEBUG in
* kernel hacking config menu to use them.
*
* Use them as run-time debugging aid. NEVER USE THEM AS ERROR HANDLING CODE!!!
*/
#ifdef CONFIG_RUNTIME_DEBUG
#include <linux/kernel.h>
#define db_assert(x) if (!(x)) { \
panic("assertion failed at %s:%d: %s", __FILE__, __LINE__, #x); }
#define db_warn(x) if (!(x)) { \
printk(KERN_WARNING "warning at %s:%d: %s", __FILE__, __LINE__, #x); }
#define db_verify(x, y) db_assert(x y)
#define db_verify_warn(x, y) db_warn(x y)
#define db_run(x) do { x; } while (0)
#else
#define db_assert(x)
#define db_warn(x)
#define db_verify(x, y) x
#define db_verify_warn(x, y) x
#define db_run(x)
#endif
#endif /* _ASM_DEBUG_H */

4
arch/mips/include/asm/elf.h
View File

@ -382,7 +382,9 @@ do { \
instruction set this cpu supports. This could be done in userspace,
but it's not easy, and we've already done it here. */
#define ELF_HWCAP (0)
#define ELF_HWCAP (elf_hwcap)
extern unsigned int elf_hwcap;
#include <asm/hwcap.h>
/*
* This yields a string that ld.so will use to load implementation

21
arch/mips/include/asm/fpu.h
View File

@ -164,25 +164,30 @@ static inline int own_fpu(int restore)
return ret;
}
static inline void lose_fpu(int save)
static inline void lose_fpu_inatomic(int save, struct task_struct *tsk)
{
preempt_disable();
if (is_msa_enabled()) {
if (save) {
save_msa(current);
current->thread.fpu.fcr31 =
save_msa(tsk);
tsk->thread.fpu.fcr31 =
read_32bit_cp1_register(CP1_STATUS);
}
disable_msa();
clear_thread_flag(TIF_USEDMSA);
clear_tsk_thread_flag(tsk, TIF_USEDMSA);
__disable_fpu();
} else if (is_fpu_owner()) {
if (save)
_save_fp(current);
_save_fp(tsk);
__disable_fpu();
}
KSTK_STATUS(current) &= ~ST0_CU1;
clear_thread_flag(TIF_USEDFPU);
KSTK_STATUS(tsk) &= ~ST0_CU1;
clear_tsk_thread_flag(tsk, TIF_USEDFPU);
}
static inline void lose_fpu(int save)
{
preempt_disable();
lose_fpu_inatomic(save, current);
preempt_enable();
}

6
arch/mips/include/asm/gpio.h
View File

@ -1,6 +0,0 @@
#ifndef __ASM_MIPS_GPIO_H
#define __ASM_MIPS_GPIO_H
#include <gpio.h>
#endif /* __ASM_MIPS_GPIO_H */

2
arch/mips/include/asm/irq.h
View File

@ -49,7 +49,7 @@ extern int cp0_compare_irq_shift;
extern int cp0_perfcount_irq;
extern int cp0_fdc_irq;
extern int __weak get_c0_fdc_int(void);
extern int get_c0_fdc_int(void);
void arch_trigger_all_cpu_backtrace(bool);
#define arch_trigger_all_cpu_backtrace arch_trigger_all_cpu_backtrace

4
arch/mips/include/asm/kdebug.h
View File

@ -11,7 +11,9 @@ enum die_val {
DIE_PAGE_FAULT,
DIE_BREAK,
DIE_SSTEPBP,
DIE_MSAFP
DIE_MSAFP,
DIE_UPROBE,
DIE_UPROBE_XOL,
};
#endif /* _ASM_MIPS_KDEBUG_H */

1
arch/mips/include/asm/linkage.h
View File

@ -5,7 +5,6 @@
#include <asm/asm.h>
#endif
#define __weak __attribute__((weak))
#define cond_syscall(x) asm(".weak\t" #x "\n" #x "\t=\tsys_ni_syscall")
#define SYSCALL_ALIAS(alias, name) \
asm ( #alias " = " #name "\n\t.globl " #alias)

2
arch/mips/include/asm/maar.h
View File

@ -26,7 +26,7 @@
*
* Return: The number of MAAR pairs configured.
*/
unsigned __weak platform_maar_init(unsigned num_pairs);
unsigned platform_maar_init(unsigned num_pairs);
/**
* write_maar_pair() - write to a pair of MAARs

4
arch/mips/include/asm/mach-ar7/ar7.h
View File

@ -203,4 +203,8 @@ static inline void ar7_device_off(u32 bit)
int __init ar7_gpio_init(void);
void __init ar7_init_clocks(void);
/* Board specific GPIO functions */
int ar7_gpio_enable(unsigned gpio);
int ar7_gpio_disable(unsigned gpio);
#endif /* __AR7_H__ */

41
arch/mips/include/asm/mach-ar7/gpio.h
View File

@ -1,41 +0,0 @@
/*
* Copyright (C) 2007-2009 Florian Fainelli <florian@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __AR7_GPIO_H__
#define __AR7_GPIO_H__
#include <asm/mach-ar7/ar7.h>
#define AR7_GPIO_MAX 32
#define TITAN_GPIO_MAX 51
#define NR_BUILTIN_GPIO TITAN_GPIO_MAX
#define gpio_to_irq(gpio) -1
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
/* Board specific GPIO functions */
int ar7_gpio_enable(unsigned gpio);
int ar7_gpio_disable(unsigned gpio);
#include <asm-generic/gpio.h>
#endif

16
arch/mips/include/asm/mach-ath25/gpio.h
View File

@ -1,16 +0,0 @@
#ifndef __ASM_MACH_ATH25_GPIO_H
#define __ASM_MACH_ATH25_GPIO_H
#include <asm-generic/gpio.h>
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#define gpio_to_irq __gpio_to_irq
static inline int irq_to_gpio(unsigned irq)
{
return -EINVAL;
}
#endif /* __ASM_MACH_ATH25_GPIO_H */

26
arch/mips/include/asm/mach-ath79/gpio.h
View File

@ -1,26 +0,0 @@
/*
* Atheros AR71XX/AR724X/AR913X GPIO API definitions
*
* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
*/
#ifndef __ASM_MACH_ATH79_GPIO_H
#define __ASM_MACH_ATH79_GPIO_H
#define ARCH_NR_GPIOS 64
#include <asm-generic/gpio.h>
int gpio_to_irq(unsigned gpio);
int irq_to_gpio(unsigned irq);
int gpio_get_value(unsigned gpio);
void gpio_set_value(unsigned gpio, int value);
#define gpio_cansleep __gpio_cansleep
#endif /* __ASM_MACH_ATH79_GPIO_H */

148
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
View File

@ -266,6 +266,17 @@ static inline int alchemy_gpio1_to_irq(int gpio)
return -ENXIO;
}
/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
* SYS_PININPUTEN is written to at least once. On Au1550/Au1200/Au1300 this
* register enables use of GPIOs as wake source.
*/
static inline void alchemy_gpio1_input_enable(void)
{
void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
__raw_writel(0, base + 0x110); /* the write op is key */
wmb();
}
/*
* GPIO2 block macros for common linux GPIO functions. The 'gpio'
* parameter must be in range of ALCHEMY_GPIO2_BASE..ALCHEMY_GPIO2_MAX.
@ -518,141 +529,4 @@ static inline int alchemy_irq_to_gpio(int irq)
return -ENXIO;
}
/**********************************************************************/
/* Linux gpio framework integration.
*
* 4 use cases of Au1000-Au1200 GPIOS:
*(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y:
* Board must register gpiochips.
*(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n:
* 2 (1 for Au1000) gpio_chips are registered.
*
*(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
* the boards' gpio.h must provide the linux gpio wrapper functions,
*
*(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
* inlinable gpio functions are provided which enable access to the
* Au1000 gpios only by using the numbers straight out of the data-
* sheets.
* Cases 1 and 3 are intended for boards which want to provide their own
* GPIO namespace and -operations (i.e. for example you have 8 GPIOs
* which are in part provided by spare Au1000 GPIO pins and in part by
* an external FPGA but you still want them to be accssible in linux
* as gpio0-7. The board can of course use the alchemy_gpioX_* functions
* as required).
*/
#ifndef CONFIG_GPIOLIB
#ifdef CONFIG_ALCHEMY_GPIOINT_AU1000
#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */
static inline int gpio_direction_input(int gpio)
{
return alchemy_gpio_direction_input(gpio);
}
static inline int gpio_direction_output(int gpio, int v)
{
return alchemy_gpio_direction_output(gpio, v);
}
static inline int gpio_get_value(int gpio)
{
return alchemy_gpio_get_value(gpio);
}
static inline void gpio_set_value(int gpio, int v)
{
alchemy_gpio_set_value(gpio, v);
}
static inline int gpio_get_value_cansleep(unsigned gpio)
{
return gpio_get_value(gpio);
}
static inline void gpio_set_value_cansleep(unsigned gpio, int value)
{
gpio_set_value(gpio, value);
}
static inline int gpio_is_valid(int gpio)
{
return alchemy_gpio_is_valid(gpio);
}
static inline int gpio_cansleep(int gpio)
{
return alchemy_gpio_cansleep(gpio);
}
static inline int gpio_to_irq(int gpio)
{
return alchemy_gpio_to_irq(gpio);
}
static inline int irq_to_gpio(int irq)
{
return alchemy_irq_to_gpio(irq);
}
static inline int gpio_request(unsigned gpio, const char *label)
{
return 0;
}
static inline int gpio_request_one(unsigned gpio,
unsigned long flags, const char *label)
{
return 0;
}
static inline int gpio_request_array(struct gpio *array, size_t num)
{
return 0;
}
static inline void gpio_free(unsigned gpio)
{
}
static inline void gpio_free_array(struct gpio *array, size_t num)
{
}
static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
{
return -ENOSYS;
}
static inline int gpio_export(unsigned gpio, bool direction_may_change)
{
return -ENOSYS;
}
static inline int gpio_export_link(struct device *dev, const char *name,
unsigned gpio)
{
return -ENOSYS;
}
static inline int gpio_sysfs_set_active_low(unsigned gpio, int value)
{
return -ENOSYS;
}
static inline void gpio_unexport(unsigned gpio)
{
}
#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
#endif /* CONFIG_ALCHEMY_GPIOINT_AU1000 */
#endif /* !CONFIG_GPIOLIB */
#endif /* _ALCHEMY_GPIO_AU1000_H_ */

86
arch/mips/include/asm/mach-au1x00/gpio.h
View File

@ -1,86 +0,0 @@
/*
* Alchemy GPIO support.
*
* With CONFIG_GPIOLIB=y different types of on-chip GPIO can be supported within
* the same kernel image.
* With CONFIG_GPIOLIB=n, your board must select ALCHEMY_GPIOINT_AU1XXX for the
* appropriate CPU type (AU1000 currently).
*/
#ifndef _ALCHEMY_GPIO_H_
#define _ALCHEMY_GPIO_H_
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/gpio-au1000.h>
#include <asm/mach-au1x00/gpio-au1300.h>
/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
* SYS_PININPUTEN is written to at least once. On Au1550/Au1200/Au1300 this
* register enables use of GPIOs as wake source.
*/
static inline void alchemy_gpio1_input_enable(void)
{
void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
__raw_writel(0, base + 0x110); /* the write op is key */
wmb();
}
/* Linux gpio framework integration.
*
* 4 use cases of Alchemy GPIOS:
*(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y:
* Board must register gpiochips.
*(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n:
* A gpiochip for the 75 GPIOs is registered.
*
*(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
* the boards' gpio.h must provide the linux gpio wrapper functions,
*
*(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
* inlinable gpio functions are provided which enable access to the
* Au1300 gpios only by using the numbers straight out of the data-
* sheets.
* Cases 1 and 3 are intended for boards which want to provide their own
* GPIO namespace and -operations (i.e. for example you have 8 GPIOs
* which are in part provided by spare Au1300 GPIO pins and in part by
* an external FPGA but you still want them to be accssible in linux
* as gpio0-7. The board can of course use the alchemy_gpioX_* functions
* as required).
*/
#ifdef CONFIG_GPIOLIB
/* wraps the cpu-dependent irq_to_gpio functions */
/* FIXME: gpiolib needs an irq_to_gpio hook */
static inline int __au_irq_to_gpio(unsigned int irq)
{
switch (alchemy_get_cputype()) {
case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200:
return alchemy_irq_to_gpio(irq);
case ALCHEMY_CPU_AU1300:
return au1300_irq_to_gpio(irq);
}
return -EINVAL;
}
/* using gpiolib to provide up to 2 gpio_chips for on-chip gpios */
#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (2) */
/* get everything through gpiolib */
#define gpio_to_irq __gpio_to_irq
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#define irq_to_gpio __au_irq_to_gpio
#include <asm-generic/gpio.h>
#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
#endif /* CONFIG_GPIOLIB */
#endif /* _ALCHEMY_GPIO_H_ */

17
arch/mips/include/asm/mach-bcm47xx/gpio.h
View File

@ -1,17 +0,0 @@
#ifndef __ASM_MIPS_MACH_BCM47XX_GPIO_H
#define __ASM_MIPS_MACH_BCM47XX_GPIO_H
#include <asm-generic/gpio.h>
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#define gpio_to_irq __gpio_to_irq
static inline int irq_to_gpio(unsigned int irq)
{
return -EINVAL;
}
#endif

15
arch/mips/include/asm/mach-bcm63xx/gpio.h
View File

@ -1,15 +0,0 @@
#ifndef __ASM_MIPS_MACH_BCM63XX_GPIO_H
#define __ASM_MIPS_MACH_BCM63XX_GPIO_H
#include <bcm63xx_gpio.h>
#define gpio_to_irq(gpio) -1
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#include <asm-generic/gpio.h>
#endif /* __ASM_MIPS_MACH_BCM63XX_GPIO_H */

21
arch/mips/include/asm/mach-cavium-octeon/gpio.h
View File

@ -1,21 +0,0 @@
#ifndef __ASM_MACH_CAVIUM_OCTEON_GPIO_H
#define __ASM_MACH_CAVIUM_OCTEON_GPIO_H
#ifdef CONFIG_GPIOLIB
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#else
int gpio_request(unsigned gpio, const char *label);
void gpio_free(unsigned gpio);
int gpio_direction_input(unsigned gpio);
int gpio_direction_output(unsigned gpio, int value);
int gpio_get_value(unsigned gpio);
void gpio_set_value(unsigned gpio, int value);
#endif
#include <asm-generic/gpio.h>
#define gpio_to_irq __gpio_to_irq
#endif /* __ASM_MACH_GENERIC_GPIO_H */

21
arch/mips/include/asm/mach-generic/gpio.h
View File

@ -1,21 +0,0 @@
#ifndef __ASM_MACH_GENERIC_GPIO_H
#define __ASM_MACH_GENERIC_GPIO_H
#ifdef CONFIG_GPIOLIB
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#else
int gpio_request(unsigned gpio, const char *label);
void gpio_free(unsigned gpio);
int gpio_direction_input(unsigned gpio);
int gpio_direction_output(unsigned gpio, int value);
int gpio_get_value(unsigned gpio);
void gpio_set_value(unsigned gpio, int value);
#endif
int gpio_to_irq(unsigned gpio);
int irq_to_gpio(unsigned irq);
#include <asm-generic/gpio.h> /* cansleep wrappers */
#endif /* __ASM_MACH_GENERIC_GPIO_H */

2
arch/mips/include/asm/mach-jz4740/gpio.h
View File

@ -73,8 +73,6 @@ int jz_gpio_port_direction_output(int port, uint32_t mask);
void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask);
uint32_t jz_gpio_port_get_value(int port, uint32_t mask);
#include <asm/mach-generic/gpio.h>
#define JZ_GPIO_PORTA(x) ((x) + 32 * 0)
#define JZ_GPIO_PORTB(x) ((x) + 32 * 1)
#define JZ_GPIO_PORTC(x) ((x) + 32 * 2)

13
arch/mips/include/asm/mach-lantiq/gpio.h
View File

@ -1,13 +0,0 @@
#ifndef __ASM_MIPS_MACH_LANTIQ_GPIO_H
#define __ASM_MIPS_MACH_LANTIQ_GPIO_H
#define gpio_to_irq __gpio_to_irq
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#include <asm-generic/gpio.h>
#endif

36
arch/mips/include/asm/mach-loongson64/gpio.h
View File

@ -1,36 +0,0 @@
/*
* Loongson GPIO Support
*
* Copyright (c) 2008 Richard Liu, STMicroelectronics <richard.liu@st.com>
* Copyright (c) 2008-2010 Arnaud Patard <apatard@mandriva.com>
* Copyright (c) 2014 Huacai Chen <chenhc@lemote.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __LOONGSON_GPIO_H
#define __LOONGSON_GPIO_H
#include <asm-generic/gpio.h>
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
/* The chip can do interrupt
* but it has not been tested and doc not clear
*/
static inline int gpio_to_irq(int gpio)
{
return -EINVAL;
}
static inline int irq_to_gpio(int gpio)
{
return -EINVAL;
}
#endif /* __LOONGSON_GPIO_H */

21
arch/mips/include/asm/mach-pistachio/gpio.h
View File

@ -1,21 +0,0 @@
/*
* Pistachio IRQ setup
*
* Copyright (C) 2014 Google, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
#ifndef __ASM_MACH_PISTACHIO_GPIO_H
#define __ASM_MACH_PISTACHIO_GPIO_H
#include <asm-generic/gpio.h>
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#define gpio_to_irq __gpio_to_irq
#endif /* __ASM_MACH_PISTACHIO_GPIO_H */

12
arch/mips/include/asm/mach-rc32434/gpio.h
View File

@ -13,18 +13,6 @@
#ifndef _RC32434_GPIO_H_
#define _RC32434_GPIO_H_
#include <linux/types.h>
#include <asm-generic/gpio.h>
#define NR_BUILTIN_GPIO 32
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#define gpio_to_irq(gpio) (8 + 4 * 32 + gpio)
#define irq_to_gpio(irq) (irq - (8 + 4 * 32))
struct rb532_gpio_reg {
u32 gpiofunc; /* GPIO Function Register
* gpiofunc[x]==0 bit = gpio

89
arch/mips/include/asm/mips-cm.h
View File

@ -33,6 +33,29 @@ extern void __iomem *mips_cm_l2sync_base;
*/
extern phys_addr_t __mips_cm_phys_base(void);
/*
* mips_cm_is64 - determine CM register width
*
* The CM register width is processor and CM specific. A 64-bit processor
* usually has a 64-bit CM and a 32-bit one has a 32-bit CM but a 64-bit
* processor could come with a 32-bit CM. Moreover, accesses on 64-bit CMs
* can be done either using regular 64-bit load/store instructions, or 32-bit
* load/store instruction on 32-bit register pairs. We opt for using 64-bit
* accesses on 64-bit CMs and kernels and 32-bit in any other case.
*
* It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
*/
extern int mips_cm_is64;
/**
* mips_cm_error_report - Report CM cache errors
*/
#ifdef CONFIG_MIPS_CM
extern void mips_cm_error_report(void);
#else
static inline void mips_cm_error_report(void) {}
#endif
/**
* mips_cm_probe - probe for a Coherence Manager
*
@ -90,20 +113,46 @@ static inline bool mips_cm_has_l2sync(void)
/* Macros to ease the creation of register access functions */
#define BUILD_CM_R_(name, off) \
static inline u32 __iomem *addr_gcr_##name(void) \
static inline unsigned long __iomem *addr_gcr_##name(void) \
{ \
return (u32 __iomem *)(mips_cm_base + (off)); \
return (unsigned long __iomem *)(mips_cm_base + (off)); \
} \
\
static inline u32 read_gcr_##name(void) \
static inline u32 read32_gcr_##name(void) \
{ \
return __raw_readl(addr_gcr_##name()); \
} \
\
static inline u64 read64_gcr_##name(void) \
{ \
return __raw_readq(addr_gcr_##name()); \
} \
\
static inline unsigned long read_gcr_##name(void) \
{ \
if (mips_cm_is64) \
return read64_gcr_##name(); \
else \
return read32_gcr_##name(); \
}
#define BUILD_CM__W(name, off) \
static inline void write_gcr_##name(u32 value) \
static inline void write32_gcr_##name(u32 value) \
{ \
__raw_writel(value, addr_gcr_##name()); \
} \
\
static inline void write64_gcr_##name(u64 value) \
{ \
__raw_writeq(value, addr_gcr_##name()); \
} \
\
static inline void write_gcr_##name(unsigned long value) \
{ \
if (mips_cm_is64) \
write64_gcr_##name(value); \
else \
write32_gcr_##name(value); \
}
#define BUILD_CM_RW(name, off) \
@ -144,6 +193,7 @@ BUILD_CM_RW(reg3_base, MIPS_CM_GCB_OFS + 0xc0)
BUILD_CM_RW(reg3_mask, MIPS_CM_GCB_OFS + 0xc8)
BUILD_CM_R_(gic_status, MIPS_CM_GCB_OFS + 0xd0)
BUILD_CM_R_(cpc_status, MIPS_CM_GCB_OFS + 0xf0)
BUILD_CM_RW(l2_config, MIPS_CM_GCB_OFS + 0x130)
/* Core Local & Core Other register accessor functions */
BUILD_CM_Cx_RW(reset_release, 0x00)
@ -189,6 +239,13 @@ BUILD_CM_Cx_R_(tcid_8_priority, 0x80)
#define CM_GCR_REV_MINOR_SHF 0
#define CM_GCR_REV_MINOR_MSK (_ULCAST_(0xff) << 0)
#define CM_ENCODE_REV(major, minor) \
(((major) << CM_GCR_REV_MAJOR_SHF) | \
((minor) << CM_GCR_REV_MINOR_SHF))
#define CM_REV_CM2 CM_ENCODE_REV(6, 0)
#define CM_REV_CM3 CM_ENCODE_REV(8, 0)
/* GCR_ERROR_CAUSE register fields */
#define CM_GCR_ERROR_CAUSE_ERRTYPE_SHF 27
#define CM_GCR_ERROR_CAUSE_ERRTYPE_MSK (_ULCAST_(0x1f) << 27)
@ -249,6 +306,16 @@ BUILD_CM_Cx_R_(tcid_8_priority, 0x80)
#define CM_GCR_CPC_STATUS_EX_SHF 0
#define CM_GCR_CPC_STATUS_EX_MSK (_ULCAST_(0x1) << 0)
/* GCR_L2_CONFIG register fields */
#define CM_GCR_L2_CONFIG_BYPASS_SHF 20
#define CM_GCR_L2_CONFIG_BYPASS_MSK (_ULCAST_(0x1) << 20)
#define CM_GCR_L2_CONFIG_SET_SIZE_SHF 12
#define CM_GCR_L2_CONFIG_SET_SIZE_MSK (_ULCAST_(0xf) << 12)
#define CM_GCR_L2_CONFIG_LINE_SIZE_SHF 8
#define CM_GCR_L2_CONFIG_LINE_SIZE_MSK (_ULCAST_(0xf) << 8)
#define CM_GCR_L2_CONFIG_ASSOC_SHF 0
#define CM_GCR_L2_CONFIG_ASSOC_MSK (_ULCAST_(0xff) << 0)
/* GCR_Cx_COHERENCE register fields */
#define CM_GCR_Cx_COHERENCE_COHDOMAINEN_SHF 0
#define CM_GCR_Cx_COHERENCE_COHDOMAINEN_MSK (_ULCAST_(0xff) << 0)
@ -324,4 +391,18 @@ static inline int mips_cm_l2sync(void)
return 0;
}
/**
* mips_cm_revision() - return CM revision
*
* Return: The revision of the CM, from GCR_REV, or 0 if no CM is present. The
* return value should be checked against the CM_REV_* macros.
*/
static inline int mips_cm_revision(void)
{
if (!mips_cm_present())
return 0;
return read_gcr_rev();
}
#endif /* __MIPS_ASM_MIPS_CM_H__ */

10
arch/mips/include/asm/mips-cpc.h
View File

@ -27,16 +27,6 @@ extern void __iomem *mips_cpc_base;
*/
extern phys_addr_t mips_cpc_default_phys_base(void);
/**
* mips_cpc_phys_base - retrieve the physical base address of the CPC
*
* This function returns the physical base address of the Cluster Power
* Controller memory mapped registers, or 0 if no Cluster Power Controller
* is present. It may be overriden by individual platforms which determine
* this address in a different way.
*/
extern phys_addr_t __weak mips_cpc_phys_base(void);
/**
* mips_cpc_probe - probe for a Cluster Power Controller
*

60
arch/mips/include/asm/mipsregs.h
View File

@ -112,6 +112,30 @@
#define CP0_TX39_CACHE $7
/* Generic EntryLo bit definitions */
#define ENTRYLO_G (_ULCAST_(1) << 0)
#define ENTRYLO_V (_ULCAST_(1) << 1)
#define ENTRYLO_D (_ULCAST_(1) << 2)
#define ENTRYLO_C_SHIFT 3
#define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT)
/* R3000 EntryLo bit definitions */
#define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
#define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
#define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
#define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
/* MIPS32/64 EntryLo bit definitions */
#ifdef CONFIG_64BIT
/* as read by dmfc0 */
#define MIPS_ENTRYLO_XI (_ULCAST_(1) << 62)
#define MIPS_ENTRYLO_RI (_ULCAST_(1) << 63)
#else
/* as read by mfc0 */
#define MIPS_ENTRYLO_XI (_ULCAST_(1) << 30)
#define MIPS_ENTRYLO_RI (_ULCAST_(1) << 31)
#endif
/*
* Values for PageMask register
*/
@ -203,6 +227,9 @@
#define PG_ESP (_ULCAST_(1) << 28)
#define PG_IEC (_ULCAST_(1) << 27)
/* MIPS32/64 EntryHI bit definitions */
#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
/*
* R4x00 interrupt enable / cause bits
*/
@ -579,6 +606,8 @@
#define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
#define MIPS_CONF7_AR (_ULCAST_(1) << 16)
/* FTLB probability bits for R6 */
#define MIPS_CONF7_FTLBP_SHIFT (18)
/* MAAR bit definitions */
#define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
@ -586,31 +615,6 @@
#define MIPS_MAAR_S (_ULCAST_(1) << 1)
#define MIPS_MAAR_V (_ULCAST_(1) << 0)
/* EntryHI bit definition */
#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
/* R3000 EntryLo bit definitions */
#define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
#define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
#define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
#define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
/* R4000 compatible EntryLo bit definitions */
#define MIPS_ENTRYLO_G (_ULCAST_(1) << 0)
#define MIPS_ENTRYLO_V (_ULCAST_(1) << 1)
#define MIPS_ENTRYLO_D (_ULCAST_(1) << 2)
#define MIPS_ENTRYLO_C_SHIFT 3
#define MIPS_ENTRYLO_C (_ULCAST_(7) << MIPS_ENTRYLO_C_SHIFT)
#ifdef CONFIG_64BIT
/* as read by dmfc0 */
#define MIPS_ENTRYLO_XI (_ULCAST_(1) << 62)
#define MIPS_ENTRYLO_RI (_ULCAST_(1) << 63)
#else
/* as read by mfc0 */
#define MIPS_ENTRYLO_XI (_ULCAST_(1) << 30)
#define MIPS_ENTRYLO_RI (_ULCAST_(1) << 31)
#endif
/* CMGCRBase bit definitions */
#define MIPS_CMGCRB_BASE 11
#define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
@ -932,7 +936,7 @@ do { \
*/
#define __read_32bit_c0_register(source, sel) \
({ int __res; \
({ unsigned int __res; \
if (sel == 0) \
__asm__ __volatile__( \
"mfc0\t%0, " #source "\n\t" \
@ -1014,7 +1018,7 @@ do { \
* On RM7000/RM9000 these are uses to access cop0 set 1 registers
*/
#define __read_32bit_c0_ctrl_register(source) \
({ int __res; \
({ unsigned int __res; \
__asm__ __volatile__( \
"cfc0\t%0, " #source "\n\t" \
: "=r" (__res)); \
@ -1471,7 +1475,7 @@ do { \
*/
#define _read_32bit_cp1_register(source, gas_hardfloat) \
({ \
int __res; \
unsigned int __res; \
\
__asm__ __volatile__( \
" .set push \n" \

80
arch/mips/include/asm/msa.h
View File

@ -14,10 +14,90 @@
#ifndef __ASSEMBLY__
#include <asm/inst.h>
extern void _save_msa(struct task_struct *);
extern void _restore_msa(struct task_struct *);
extern void _init_msa_upper(void);
extern void read_msa_wr_b(unsigned idx, union fpureg *to);
extern void read_msa_wr_h(unsigned idx, union fpureg *to);
extern void read_msa_wr_w(unsigned idx, union fpureg *to);
extern void read_msa_wr_d(unsigned idx, union fpureg *to);
/**
* read_msa_wr() - Read a single MSA vector register
* @idx: The index of the vector register to read
* @to: The FPU register union to store the registers value in
* @fmt: The format of the data in the vector register
*
* Read the value of MSA vector register idx into the FPU register
* union to, using the format fmt.
*/
static inline void read_msa_wr(unsigned idx, union fpureg *to,
enum msa_2b_fmt fmt)
{
switch (fmt) {
case msa_fmt_b:
read_msa_wr_b(idx, to);
break;
case msa_fmt_h:
read_msa_wr_h(idx, to);
break;
case msa_fmt_w:
read_msa_wr_w(idx, to);
break;
case msa_fmt_d:
read_msa_wr_d(idx, to);
break;
default:
BUG();
}
}
extern void write_msa_wr_b(unsigned idx, union fpureg *from);
extern void write_msa_wr_h(unsigned idx, union fpureg *from);
extern void write_msa_wr_w(unsigned idx, union fpureg *from);
extern void write_msa_wr_d(unsigned idx, union fpureg *from);
/**
* write_msa_wr() - Write a single MSA vector register
* @idx: The index of the vector register to write
* @from: The FPU register union to take the registers value from
* @fmt: The format of the data in the vector register
*
* Write the value from the FPU register union from into MSA vector
* register idx, using the format fmt.
*/
static inline void write_msa_wr(unsigned idx, union fpureg *from,
enum msa_2b_fmt fmt)
{
switch (fmt) {
case msa_fmt_b:
write_msa_wr_b(idx, from);
break;
case msa_fmt_h:
write_msa_wr_h(idx, from);
break;
case msa_fmt_w:
write_msa_wr_w(idx, from);
break;
case msa_fmt_d:
write_msa_wr_d(idx, from);
break;
default:
BUG();
}
}
static inline void enable_msa(void)
{
if (cpu_has_msa) {

2
arch/mips/include/asm/octeon/cvmx-bootinfo.h
View File

@ -284,6 +284,7 @@ enum cvmx_board_types_enum {
CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001,
CVMX_BOARD_TYPE_UBNT_E100 = 20002,
CVMX_BOARD_TYPE_CUST_DSR1000N = 20006,
CVMX_BOARD_TYPE_KONTRON_S1901 = 21901,
CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000,
/* The remaining range is reserved for future use. */
@ -384,6 +385,7 @@ static inline const char *cvmx_board_type_to_string(enum
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E100)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DSR1000N)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KONTRON_S1901)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX)
}
return "Unsupported Board";

2
arch/mips/include/asm/octeon/cvmx-pip.h
View File

@ -37,7 +37,7 @@
#include <asm/octeon/cvmx-fpa.h>
#include <asm/octeon/cvmx-pip-defs.h>
#define CVMX_PIP_NUM_INPUT_PORTS 40
#define CVMX_PIP_NUM_INPUT_PORTS 48
#define CVMX_PIP_NUM_WATCHERS 4
/*

3
arch/mips/include/asm/octeon/cvmx-pko.h
View File

@ -542,6 +542,9 @@ static inline int cvmx_pko_get_base_queue_per_core(int port, int core)
*/
static inline int cvmx_pko_get_base_queue(int port)
{
if (OCTEON_IS_MODEL(OCTEON_CN68XX))
return port;
return cvmx_pko_get_base_queue_per_core(port, 0);
}

29
arch/mips/include/asm/octeon/cvmx-pow-defs.h
View File

@ -52,6 +52,12 @@
#define CVMX_POW_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000080ull) + ((offset) & 15) * 8)
#define CVMX_POW_WS_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000280ull) + ((offset) & 15) * 8)
#define CVMX_SSO_WQ_INT (CVMX_ADD_IO_SEG(0x0001670000001000ull))
#define CVMX_SSO_WQ_IQ_DIS (CVMX_ADD_IO_SEG(0x0001670000001010ull))
#define CVMX_SSO_WQ_INT_PC (CVMX_ADD_IO_SEG(0x0001670000001020ull))
#define CVMX_SSO_PPX_GRP_MSK(offset) (CVMX_ADD_IO_SEG(0x0001670000006000ull) + ((offset) & 31) * 8)
#define CVMX_SSO_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000007000ull) + ((offset) & 63) * 8)
union cvmx_pow_bist_stat {
uint64_t u64;
struct cvmx_pow_bist_stat_s {
@ -1286,4 +1292,27 @@ union cvmx_pow_ws_pcx {
struct cvmx_pow_ws_pcx_s cnf71xx;
};
union cvmx_sso_wq_int_thrx {
uint64_t u64;
struct {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_33_63:31;
uint64_t tc_en:1;
uint64_t tc_thr:4;
uint64_t reserved_26_27:2;
uint64_t ds_thr:12;
uint64_t reserved_12_13:2;
uint64_t iq_thr:12;
#else
uint64_t iq_thr:12;
uint64_t reserved_12_13:2;
uint64_t ds_thr:12;
uint64_t reserved_26_27:2;
uint64_t tc_thr:4;
uint64_t tc_en:1;
uint64_t reserved_33_63:31;
#endif
} s;
};
#endif

9
arch/mips/include/asm/octeon/cvmx-pow.h
View File

@ -1810,10 +1810,11 @@ static inline void cvmx_pow_work_submit(cvmx_wqe_t *wqp, uint32_t tag,
cvmx_addr_t ptr;
cvmx_pow_tag_req_t tag_req;
wqp->qos = qos;
wqp->tag = tag;
wqp->tag_type = tag_type;
wqp->grp = grp;
wqp->word1.tag = tag;
wqp->word1.tag_type = tag_type;
cvmx_wqe_set_qos(wqp, qos);
cvmx_wqe_set_grp(wqp, grp);
tag_req.u64 = 0;
tag_req.s.op = CVMX_POW_TAG_OP_ADDWQ;

308
arch/mips/include/asm/octeon/cvmx-wqe.h
View File

@ -193,6 +193,53 @@ typedef union {
uint64_t bufs:8;
#endif
} s;
struct {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t bufs:8;
uint64_t ip_offset:8;
uint64_t vlan_valid:1;
uint64_t vlan_stacked:1;
uint64_t unassigned:1;
uint64_t vlan_cfi:1;
uint64_t vlan_id:12;
uint64_t port:12; /* MAC/PIP port number. */
uint64_t dec_ipcomp:1;
uint64_t tcp_or_udp:1;
uint64_t dec_ipsec:1;
uint64_t is_v6:1;
uint64_t software:1;
uint64_t L4_error:1;
uint64_t is_frag:1;
uint64_t IP_exc:1;
uint64_t is_bcast:1;
uint64_t is_mcast:1;
uint64_t not_IP:1;
uint64_t rcv_error:1;
uint64_t err_code:8;
#else
uint64_t err_code:8;
uint64_t rcv_error:1;
uint64_t not_IP:1;
uint64_t is_mcast:1;
uint64_t is_bcast:1;
uint64_t IP_exc:1;
uint64_t is_frag:1;
uint64_t L4_error:1;
uint64_t software:1;
uint64_t is_v6:1;
uint64_t dec_ipsec:1;
uint64_t tcp_or_udp:1;
uint64_t dec_ipcomp:1;
uint64_t port:12;
uint64_t vlan_id:12;
uint64_t vlan_cfi:1;
uint64_t unassigned:1;
uint64_t vlan_stacked:1;
uint64_t vlan_valid:1;
uint64_t ip_offset:8;
uint64_t bufs:8;
#endif
} s_cn68xx;
/* use this to get at the 16 vlan bits */
struct {
@ -355,6 +402,146 @@ typedef union {
} cvmx_pip_wqe_word2;
union cvmx_pip_wqe_word0 {
struct {
#ifdef __BIG_ENDIAN_BITFIELD
/**
* raw chksum result generated by the HW
*/
uint16_t hw_chksum;
/**
* Field unused by hardware - available for software
*/
uint8_t unused;
/**
* Next pointer used by hardware for list maintenance.
* May be written/read by HW before the work queue
* entry is scheduled to a PP (Only 36 bits used in
* Octeon 1)
*/
uint64_t next_ptr:40;
#else
uint64_t next_ptr:40;
uint8_t unused;
uint16_t hw_chksum;
#endif
} cn38xx;
struct {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t l4ptr:8; /* 56..63 */
uint64_t unused0:8; /* 48..55 */
uint64_t l3ptr:8; /* 40..47 */
uint64_t l2ptr:8; /* 32..39 */
uint64_t unused1:18; /* 14..31 */
uint64_t bpid:6; /* 8..13 */
uint64_t unused2:2; /* 6..7 */
uint64_t pknd:6; /* 0..5 */
#else
uint64_t pknd:6; /* 0..5 */
uint64_t unused2:2; /* 6..7 */
uint64_t bpid:6; /* 8..13 */
uint64_t unused1:18; /* 14..31 */
uint64_t l2ptr:8; /* 32..39 */
uint64_t l3ptr:8; /* 40..47 */
uint64_t unused0:8; /* 48..55 */
uint64_t l4ptr:8; /* 56..63 */
#endif
} cn68xx;
};
union cvmx_wqe_word0 {
uint64_t u64;
union cvmx_pip_wqe_word0 pip;
};
union cvmx_wqe_word1 {
uint64_t u64;
struct {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t len:16;
uint64_t varies:14;
/**
* the type of the tag (ORDERED, ATOMIC, NULL)
*/
uint64_t tag_type:2;
uint64_t tag:32;
#else
uint64_t tag:32;
uint64_t tag_type:2;
uint64_t varies:14;
uint64_t len:16;
#endif
};
struct {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t len:16;
uint64_t zero_0:1;
/**
* HW sets this to what it thought the priority of
* the input packet was
*/
uint64_t qos:3;
uint64_t zero_1:1;
/**
* the group that the work queue entry will be scheduled to
*/
uint64_t grp:6;
uint64_t zero_2:3;
uint64_t tag_type:2;
uint64_t tag:32;
#else
uint64_t tag:32;
uint64_t tag_type:2;
uint64_t zero_2:3;
uint64_t grp:6;
uint64_t zero_1:1;
uint64_t qos:3;
uint64_t zero_0:1;
uint64_t len:16;
#endif
} cn68xx;
struct {
#ifdef __BIG_ENDIAN_BITFIELD
/**
* HW sets to the total number of bytes in the packet
*/
uint64_t len:16;
/**
* HW sets this to input physical port
*/
uint64_t ipprt:6;
/**
* HW sets this to what it thought the priority of
* the input packet was
*/
uint64_t qos:3;
/**
* the group that the work queue entry will be scheduled to
*/
uint64_t grp:4;
/**
* the type of the tag (ORDERED, ATOMIC, NULL)
*/
uint64_t tag_type:3;
/**
* the synchronization/ordering tag
*/
uint64_t tag:32;
#else
uint64_t tag:32;
uint64_t tag_type:2;
uint64_t zero_2:1;
uint64_t grp:4;
uint64_t qos:3;
uint64_t ipprt:6;
uint64_t len:16;
#endif
} cn38xx;
};
/**
* Work queue entry format
*
@ -366,70 +553,13 @@ typedef struct {
* WORD 0
* HW WRITE: the following 64 bits are filled by HW when a packet arrives
*/
#ifdef __BIG_ENDIAN_BITFIELD
/**
* raw chksum result generated by the HW
*/
uint16_t hw_chksum;
/**
* Field unused by hardware - available for software
*/
uint8_t unused;
/**
* Next pointer used by hardware for list maintenance.
* May be written/read by HW before the work queue
* entry is scheduled to a PP
* (Only 36 bits used in Octeon 1)
*/
uint64_t next_ptr:40;
#else
uint64_t next_ptr:40;
uint8_t unused;
uint16_t hw_chksum;
#endif
union cvmx_wqe_word0 word0;
/*****************************************************************
* WORD 1
* HW WRITE: the following 64 bits are filled by HW when a packet arrives
*/
#ifdef __BIG_ENDIAN_BITFIELD
/**
* HW sets to the total number of bytes in the packet
*/
uint64_t len:16;
/**
* HW sets this to input physical port
*/
uint64_t ipprt:6;
/**
* HW sets this to what it thought the priority of the input packet was
*/
uint64_t qos:3;
/**
* the group that the work queue entry will be scheduled to
*/
uint64_t grp:4;
/**
* the type of the tag (ORDERED, ATOMIC, NULL)
*/
uint64_t tag_type:3;
/**
* the synchronization/ordering tag
*/
uint64_t tag:32;
#else
uint64_t tag:32;
uint64_t tag_type:2;
uint64_t zero_2:1;
uint64_t grp:4;
uint64_t qos:3;
uint64_t ipprt:6;
uint64_t len:16;
#endif
union cvmx_wqe_word1 word1;
/**
* WORD 2 HW WRITE: the following 64-bits are filled in by
@ -465,4 +595,64 @@ typedef struct {
} CVMX_CACHE_LINE_ALIGNED cvmx_wqe_t;
static inline int cvmx_wqe_get_port(cvmx_wqe_t *work)
{
int port;
if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
port = work->word2.s_cn68xx.port;
else
port = work->word1.cn38xx.ipprt;
return port;
}
static inline void cvmx_wqe_set_port(cvmx_wqe_t *work, int port)
{
if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
work->word2.s_cn68xx.port = port;
else
work->word1.cn38xx.ipprt = port;
}
static inline int cvmx_wqe_get_grp(cvmx_wqe_t *work)
{
int grp;
if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
grp = work->word1.cn68xx.grp;
else
grp = work->word1.cn38xx.grp;
return grp;
}
static inline void cvmx_wqe_set_grp(cvmx_wqe_t *work, int grp)
{
if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
work->word1.cn68xx.grp = grp;
else
work->word1.cn38xx.grp = grp;
}
static inline int cvmx_wqe_get_qos(cvmx_wqe_t *work)
{
int qos;
if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
qos = work->word1.cn68xx.qos;
else
qos = work->word1.cn38xx.qos;
return qos;
}
static inline void cvmx_wqe_set_qos(cvmx_wqe_t *work, int qos)
{
if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
work->word1.cn68xx.qos = qos;
else
work->word1.cn38xx.qos = qos;
}
#endif /* __CVMX_WQE_H__ */

25
arch/mips/include/asm/pgtable-bits.h
View File

@ -133,20 +133,13 @@
#define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT)
#define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT + 1)
#define _PAGE_SPLITTING (1 << _PAGE_SPLITTING_SHIFT)
/* Only R2 or newer cores have the XI bit */
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
#define _PAGE_NO_EXEC_SHIFT (_PAGE_SPLITTING_SHIFT + 1)
#else
#define _PAGE_GLOBAL_SHIFT (_PAGE_SPLITTING_SHIFT + 1)
#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
#endif /* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */
#endif /* CONFIG_64BIT && CONFIG_MIPS_HUGE_TLB_SUPPORT */
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
/* XI - page cannot be executed */
#ifndef _PAGE_NO_EXEC_SHIFT
#ifdef _PAGE_SPLITTING_SHIFT
#define _PAGE_NO_EXEC_SHIFT (_PAGE_SPLITTING_SHIFT + 1)
#else
#define _PAGE_NO_EXEC_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
#endif
#define _PAGE_NO_EXEC (cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0)
@ -156,14 +149,16 @@
#define _PAGE_READ (cpu_has_rixi ? 0 : (1 << _PAGE_READ_SHIFT))
#define _PAGE_NO_READ_SHIFT _PAGE_READ_SHIFT
#define _PAGE_NO_READ (cpu_has_rixi ? (1 << _PAGE_READ_SHIFT) : 0)
#endif /* defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) */
#if defined(_PAGE_NO_READ_SHIFT)
#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1)
#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
#else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR6 */
#elif defined(_PAGE_SPLITTING_SHIFT)
#define _PAGE_GLOBAL_SHIFT (_PAGE_SPLITTING_SHIFT + 1)
#else
#define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
#endif
#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
#endif /* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */
#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
@ -249,7 +244,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */
#define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */
#elif defined(CONFIG_MACH_JZ4740)
#elif defined(CONFIG_MACH_INGENIC)
/* Ingenic uses the WA bit to achieve write-combine memory writes */
#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)

2
arch/mips/include/asm/pgtable.h
View File

@ -393,6 +393,8 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot)
return __pgprot(prot);
}
#define pgprot_writecombine pgprot_writecombine
static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
{
unsigned long prot = pgprot_val(_prot);

2
arch/mips/include/asm/processor.h
View File

@ -275,6 +275,7 @@ struct thread_struct {
unsigned long cp0_badvaddr; /* Last user fault */
unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
unsigned long error_code;
unsigned long trap_nr;
#ifdef CONFIG_CPU_CAVIUM_OCTEON
struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
@ -341,6 +342,7 @@ struct thread_struct {
.cp0_badvaddr = 0, \
.cp0_baduaddr = 0, \
.error_code = 0, \
.trap_nr = 0, \
/* \
* Platform specific cop2 registers(null if no COP2) \
*/ \

80
arch/mips/include/asm/ptrace.h
View File

@ -14,11 +14,16 @@
#include <linux/linkage.h>
#include <linux/types.h>
#include <asm/isadep.h>
#include <asm/page.h>
#include <asm/thread_info.h>
#include <uapi/asm/ptrace.h>
/*
* This struct defines the way the registers are stored on the stack during a
* system call/exception. As usual the registers k0/k1 aren't being saved.
*
* If you add a register here, also add it to regoffset_table[] in
* arch/mips/kernel/ptrace.c.
*/
struct pt_regs {
#ifdef CONFIG_32BIT
@ -43,8 +48,83 @@ struct pt_regs {
unsigned long long mpl[6]; /* MTM{0-5} */
unsigned long long mtp[6]; /* MTP{0-5} */
#endif
unsigned long __last[0];
} __aligned(8);
static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
{
return regs->regs[31];
}
/*
* Don't use asm-generic/ptrace.h it defines FP accessors that don't make
* sense on MIPS. We rather want an error if they get invoked.
*/
static inline void instruction_pointer_set(struct pt_regs *regs,
unsigned long val)
{
regs->cp0_epc = val;
}
/* Query offset/name of register from its name/offset */
extern int regs_query_register_offset(const char *name);
#define MAX_REG_OFFSET (offsetof(struct pt_regs, __last))
/**
* regs_get_register() - get register value from its offset
* @regs: pt_regs from which register value is gotten.
* @offset: offset number of the register.
*
* regs_get_register returns the value of a register. The @offset is the
* offset of the register in struct pt_regs address which specified by @regs.
* If @offset is bigger than MAX_REG_OFFSET, this returns 0.
*/
static inline unsigned long regs_get_register(struct pt_regs *regs,
unsigned int offset)
{
if (unlikely(offset > MAX_REG_OFFSET))
return 0;
return *(unsigned long *)((unsigned long)regs + offset);
}
/**
* regs_within_kernel_stack() - check the address in the stack
* @regs: pt_regs which contains kernel stack pointer.
* @addr: address which is checked.
*
* regs_within_kernel_stack() checks @addr is within the kernel stack page(s).
* If @addr is within the kernel stack, it returns true. If not, returns false.
*/
static inline int regs_within_kernel_stack(struct pt_regs *regs,
unsigned long addr)
{
return ((addr & ~(THREAD_SIZE - 1)) ==
(kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1)));
}
/**
* regs_get_kernel_stack_nth() - get Nth entry of the stack
* @regs: pt_regs which contains kernel stack pointer.
* @n: stack entry number.
*
* regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which
* is specified by @regs. If the @n th entry is NOT in the kernel stack,
* this returns 0.
*/
static inline unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
unsigned int n)
{
unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs);
addr += n;
if (regs_within_kernel_stack(regs, (unsigned long)addr))
return *addr;
else
return 0;
}
struct task_struct;
extern int ptrace_getregs(struct task_struct *child,

3
arch/mips/include/asm/signal.h
View File

@ -23,4 +23,7 @@
#define __ARCH_HAS_IRIX_SIGACTION
extern int protected_save_fp_context(void __user *sc);
extern int protected_restore_fp_context(void __user *sc);
#endif /* _ASM_SIGNAL_H */

5
arch/mips/include/asm/spinlock.h
View File

@ -42,6 +42,11 @@ static inline int arch_spin_is_locked(arch_spinlock_t *lock)
return ((counters >> 16) ^ counters) & 0xffff;
}
static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
{
return lock.h.serving_now == lock.h.ticket;
}
#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
#define arch_spin_unlock_wait(x) \
while (arch_spin_is_locked(x)) { cpu_relax(); }

21
arch/mips/include/asm/switch_to.h
View File

@ -16,29 +16,21 @@
#include <asm/watch.h>
#include <asm/dsp.h>
#include <asm/cop2.h>
#include <asm/msa.h>
#include <asm/fpu.h>
struct task_struct;
enum {
FP_SAVE_NONE = 0,
FP_SAVE_VECTOR = -1,
FP_SAVE_SCALAR = 1,
};
/**
* resume - resume execution of a task
* @prev: The task previously executed.
* @next: The task to begin executing.
* @next_ti: task_thread_info(next).
* @fp_save: Which, if any, FP context to save for prev.
*
* This function is used whilst scheduling to save the context of prev & load
* the context of next. Returns prev.
*/
extern asmlinkage struct task_struct *resume(struct task_struct *prev,
struct task_struct *next, struct thread_info *next_ti,
s32 fp_save);
struct task_struct *next, struct thread_info *next_ti);
extern unsigned int ll_bit;
extern struct task_struct *ll_task;
@ -91,8 +83,8 @@ do { if (cpu_has_rw_llb) { \
*/
#define switch_to(prev, next, last) \
do { \
s32 __fpsave = FP_SAVE_NONE; \
__mips_mt_fpaff_switch_to(prev); \
lose_fpu_inatomic(1, prev); \
if (cpu_has_dsp) { \
__save_dsp(prev); \
__restore_dsp(next); \
@ -111,15 +103,10 @@ do { \
clear_c0_status(ST0_CU2); \
} \
__clear_software_ll_bit(); \
if (test_and_clear_tsk_thread_flag(prev, TIF_USEDFPU)) \
__fpsave = FP_SAVE_SCALAR; \
if (test_and_clear_tsk_thread_flag(prev, TIF_USEDMSA)) \
__fpsave = FP_SAVE_VECTOR; \
if (cpu_has_userlocal) \
write_c0_userlocal(task_thread_info(next)->tp_value); \
__restore_watch(); \
disable_msa(); \
(last) = resume(prev, next, task_thread_info(next), __fpsave); \
(last) = resume(prev, next, task_thread_info(next)); \
} while (0)
#endif /* _ASM_SWITCH_TO_H */

5
arch/mips/include/asm/thread_info.h
View File

@ -99,6 +99,7 @@ static inline struct thread_info *current_thread_info(void)
#define TIF_SYSCALL_AUDIT 3 /* syscall auditing active */
#define TIF_SECCOMP 4 /* secure computing */
#define TIF_NOTIFY_RESUME 5 /* callback before returning to user */
#define TIF_UPROBE 6 /* breakpointed or singlestepping */
#define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */
#define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */
#define TIF_MEMDIE 18 /* is terminating due to OOM killer */
@ -122,6 +123,7 @@ static inline struct thread_info *current_thread_info(void)
#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
#define _TIF_SECCOMP (1<<TIF_SECCOMP)
#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
#define _TIF_UPROBE (1<<TIF_UPROBE)
#define _TIF_USEDFPU (1<<TIF_USEDFPU)
#define _TIF_NOHZ (1<<TIF_NOHZ)
#define _TIF_FIXADE (1<<TIF_FIXADE)
@ -146,7 +148,8 @@ static inline struct thread_info *current_thread_info(void)
/* work to do on interrupt/exception return */
#define _TIF_WORK_MASK \
(_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_NOTIFY_RESUME)
(_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_NOTIFY_RESUME | \
_TIF_UPROBE)
/* work to do on any return to u-space */
#define _TIF_ALLWORK_MASK (_TIF_NOHZ | _TIF_WORK_MASK | \
_TIF_WORK_SYSCALL_EXIT | \

2
arch/mips/include/asm/time.h
View File

@ -51,7 +51,7 @@ extern int __weak get_c0_perfcount_int(void);
/*
* Initialize the calling CPU's compare interrupt as clockevent device
*/
extern unsigned int __weak get_c0_compare_int(void);
extern unsigned int get_c0_compare_int(void);
extern int r4k_clockevent_init(void);
static inline int mips_clockevent_init(void)

1
arch/mips/include/asm/tlbdebug.h
View File

@ -11,6 +11,7 @@
/*
* TLB debugging functions:
*/
extern void dump_tlb_regs(void);
extern void dump_tlb_all(void);
#endif /* __ASM_TLBDEBUG_H */

58
arch/mips/include/asm/uprobes.h Normal file
View File

@ -0,0 +1,58 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_UPROBES_H
#define __ASM_UPROBES_H
#include <linux/notifier.h>
#include <linux/types.h>
#include <asm/break.h>
#include <asm/inst.h>
/*
* We want this to be defined as union mips_instruction but that makes the
* generic code blow up.
*/
typedef u32 uprobe_opcode_t;
/*
* Classic MIPS (note this implementation doesn't consider microMIPS yet)
* instructions are always 4 bytes but in order to deal with branches and
* their delay slots, we treat instructions as having 8 bytes maximum.
*/
#define MAX_UINSN_BYTES 8
#define UPROBE_XOL_SLOT_BYTES 128 /* Max. cache line size */
#define UPROBE_BRK_UPROBE 0x000d000d /* break 13 */
#define UPROBE_BRK_UPROBE_XOL 0x000e000d /* break 14 */
#define UPROBE_SWBP_INSN UPROBE_BRK_UPROBE
#define UPROBE_SWBP_INSN_SIZE 4
struct arch_uprobe {
unsigned long resume_epc;
u32 insn[2];
u32 ixol[2];
union mips_instruction orig_inst[MAX_UINSN_BYTES / 4];
};
struct arch_uprobe_task {
unsigned long saved_trap_nr;
};
extern int arch_uprobe_analyze_insn(struct arch_uprobe *aup,
struct mm_struct *mm, unsigned long addr);
extern int arch_uprobe_pre_xol(struct arch_uprobe *aup, struct pt_regs *regs);
extern int arch_uprobe_post_xol(struct arch_uprobe *aup, struct pt_regs *regs);
extern bool arch_uprobe_xol_was_trapped(struct task_struct *tsk);
extern int arch_uprobe_exception_notify(struct notifier_block *self,
unsigned long val, void *data);
extern void arch_uprobe_abort_xol(struct arch_uprobe *aup,
struct pt_regs *regs);
extern unsigned long arch_uretprobe_hijack_return_addr(
unsigned long trampoline_vaddr, struct pt_regs *regs);
#endif /* __ASM_UPROBES_H */

2
arch/mips/include/asm/vpe.h
View File

@ -122,7 +122,7 @@ void release_vpe(struct vpe *v);
void *alloc_progmem(unsigned long len);
void release_progmem(void *ptr);
int __weak vpe_run(struct vpe *v);
int vpe_run(struct vpe *v);
void cleanup_tc(struct tc *tc);
int __init vpe_module_init(void);

2
arch/mips/include/uapi/asm/break.h
View File

@ -21,6 +21,8 @@
#define BRK_DIVZERO 7 /* Divide by zero check */
#define BRK_RANGE 8 /* Range error check */
#define BRK_BUG 12 /* Used by BUG() */
#define BRK_UPROBE 13 /* See <asm/uprobes.h> */
#define BRK_UPROBE_XOL 14 /* See <asm/uprobes.h> */
#define BRK_MEMU 514 /* Used by FPU emulator */
#define BRK_KPROBE_BP 515 /* Kprobe break */
#define BRK_KPROBE_SSTEPBP 516 /* Kprobe single step software implementation */

8
arch/mips/include/uapi/asm/hwcap.h Normal file
View File

@ -0,0 +1,8 @@
#ifndef _UAPI_ASM_HWCAP_H
#define _UAPI_ASM_HWCAP_H
/* HWCAP flags */
#define HWCAP_MIPS_R6 (1 << 0)
#define HWCAP_MIPS_MSA (1 << 1)
#endif /* _UAPI_ASM_HWCAP_H */

40
arch/mips/include/uapi/asm/inst.h
View File

@ -26,7 +26,7 @@ enum major_op {
cop0_op, cop1_op, cop2_op, cop1x_op,
beql_op, bnel_op, blezl_op, bgtzl_op,
daddi_op, cbcond1_op = daddi_op, daddiu_op, ldl_op, ldr_op,
spec2_op, jalx_op, mdmx_op, spec3_op,
spec2_op, jalx_op, mdmx_op, msa_op = mdmx_op, spec3_op,
lb_op, lh_op, lwl_op, lw_op,
lbu_op, lhu_op, lwr_op, lwu_op,
sb_op, sh_op, swl_op, sw_op,
@ -167,8 +167,13 @@ enum cop1_sdw_func {
fround_op = 0x0c, ftrunc_op = 0x0d,
fceil_op = 0x0e, ffloor_op = 0x0f,
fmovc_op = 0x11, fmovz_op = 0x12,
fmovn_op = 0x13, frecip_op = 0x15,
frsqrt_op = 0x16, fcvts_op = 0x20,
fmovn_op = 0x13, fseleqz_op = 0x14,
frecip_op = 0x15, frsqrt_op = 0x16,
fselnez_op = 0x17, fmaddf_op = 0x18,
fmsubf_op = 0x19, frint_op = 0x1a,
fclass_op = 0x1b, fmin_op = 0x1c,
fmina_op = 0x1d, fmax_op = 0x1e,
fmaxa_op = 0x1f, fcvts_op = 0x20,
fcvtd_op = 0x21, fcvte_op = 0x22,
fcvtw_op = 0x24, fcvtl_op = 0x25,
fcmp_op = 0x30
@ -220,6 +225,24 @@ enum bshfl_func {
seh_op = 0x18,
};
/*
* func field for MSA MI10 format.
*/
enum msa_mi10_func {
msa_ld_op = 8,
msa_st_op = 9,
};
/*
* MSA 2 bit format fields.
*/
enum msa_2b_fmt {
msa_fmt_b = 0,
msa_fmt_h = 1,
msa_fmt_w = 2,
msa_fmt_d = 3,
};
/*
* (microMIPS) Major opcodes.
*/
@ -611,6 +634,16 @@ struct v_format { /* MDMX vector format */
;)))))))
};
struct msa_mi10_format { /* MSA MI10 */
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(signed int s10 : 10,
__BITFIELD_FIELD(unsigned int rs : 5,
__BITFIELD_FIELD(unsigned int wd : 5,
__BITFIELD_FIELD(unsigned int func : 4,
__BITFIELD_FIELD(unsigned int df : 2,
;))))))
};
struct spec3_format { /* SPEC3 */
__BITFIELD_FIELD(unsigned int opcode:6,
__BITFIELD_FIELD(unsigned int rs:5,
@ -888,6 +921,7 @@ union mips_instruction {
struct p_format p_format;
struct f_format f_format;
struct ma_format ma_format;
struct msa_mi10_format msa_mi10_format;
struct b_format b_format;
struct ps_format ps_format;
struct v_format v_format;

12
arch/mips/include/uapi/asm/sigcontext.h
View File

@ -12,6 +12,18 @@
#include <linux/types.h>
#include <asm/sgidefs.h>
/* scalar FP context was used */
#define USED_FP (1 << 0)
/* the value of Status.FR when context was saved */
#define USED_FR1 (1 << 1)
/* FR=1, but with odd singles in bits 63:32 of preceding even double */
#define USED_HYBRID_FPRS (1 << 2)
/* extended context was used, see struct extcontext for details */
#define USED_EXTCONTEXT (1 << 3)
#if _MIPS_SIM == _MIPS_SIM_ABI32
/*

12
arch/mips/include/uapi/asm/swab.h
View File

@ -16,11 +16,13 @@
#if (defined(__mips_isa_rev) && (__mips_isa_rev >= 2)) || \
defined(_MIPS_ARCH_LOONGSON3A)
static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
static inline __attribute__((nomips16)) __attribute_const__
__u16 __arch_swab16(__u16 x)
{
__asm__(
" .set push \n"
" .set arch=mips32r2 \n"
" .set nomips16 \n"
" wsbh %0, %1 \n"
" .set pop \n"
: "=r" (x)
@ -30,11 +32,13 @@ static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
}
#define __arch_swab16 __arch_swab16
static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
static inline __attribute__((nomips16)) __attribute_const__
__u32 __arch_swab32(__u32 x)
{
__asm__(
" .set push \n"
" .set arch=mips32r2 \n"
" .set nomips16 \n"
" wsbh %0, %1 \n"
" rotr %0, %0, 16 \n"
" .set pop \n"
@ -50,11 +54,13 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
* 64-bit kernel on r2 CPUs.
*/
#ifdef __mips64
static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
static inline __attribute__((nomips16)) __attribute_const__
__u64 __arch_swab64(__u64 x)
{
__asm__(
" .set push \n"
" .set arch=mips64r2 \n"
" .set nomips16 \n"
" dsbh %0, %1 \n"
" dshd %0, %0 \n"
" .set pop \n"

65
arch/mips/include/uapi/asm/ucontext.h Normal file
View File

@ -0,0 +1,65 @@
#ifndef __MIPS_UAPI_ASM_UCONTEXT_H
#define __MIPS_UAPI_ASM_UCONTEXT_H
/**
* struct extcontext - extended context header structure
* @magic: magic value identifying the type of extended context
* @size: the size in bytes of the enclosing structure
*
* Extended context structures provide context which does not fit within struct
* sigcontext. They are placed sequentially in memory at the end of struct
* ucontext and struct sigframe, with each extended context structure beginning
* with a header defined by this struct. The type of context represented is
* indicated by the magic field. Userland may check each extended context
* structure against magic values that it recognises. The size field allows any
* unrecognised context to be skipped, allowing for future expansion. The end
* of the extended context data is indicated by the magic value
* END_EXTCONTEXT_MAGIC.
*/
struct extcontext {
unsigned int magic;
unsigned int size;
};
/**
* struct msa_extcontext - MSA extended context structure
* @ext: the extended context header, with magic == MSA_EXTCONTEXT_MAGIC
* @wr: the most significant 64 bits of each MSA vector register
* @csr: the value of the MSA control & status register
*
* If MSA context is live for a task at the time a signal is delivered to it,
* this structure will hold the MSA context of the task as it was prior to the
* signal delivery.
*/
struct msa_extcontext {
struct extcontext ext;
#define MSA_EXTCONTEXT_MAGIC 0x784d5341 /* xMSA */
unsigned long long wr[32];
unsigned int csr;
};
#define END_EXTCONTEXT_MAGIC 0x78454e44 /* xEND */
/**
* struct ucontext - user context structure
* @uc_flags:
* @uc_link:
* @uc_stack:
* @uc_mcontext: holds basic processor state
* @uc_sigmask:
* @uc_extcontext: holds extended processor state
*/
struct ucontext {
/* Historic fields matching asm-generic */
unsigned long uc_flags;
struct ucontext *uc_link;
stack_t uc_stack;
struct sigcontext uc_mcontext;
sigset_t uc_sigmask;
/* Extended context structures may follow ucontext */
unsigned long long uc_extcontext[0];
};
#endif /* __MIPS_UAPI_ASM_UCONTEXT_H */

7
arch/mips/jazz/irq.c
View File

@ -110,18 +110,11 @@ asmlinkage void plat_irq_dispatch(void)
}
}
static void r4030_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
/* Nothing to do ... */
}
struct clock_event_device r4030_clockevent = {
.name = "r4030",
.features = CLOCK_EVT_FEAT_PERIODIC,
.rating = 300,
.irq = JAZZ_TIMER_IRQ,
.set_mode = r4030_set_mode,
};
static irqreturn_t r4030_timer_interrupt(int irq, void *dev_id)

24
arch/mips/jz4740/gpio.c
View File

@ -231,6 +231,13 @@ static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
return 0;
}
static int jz_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
{
struct jz_gpio_chip *jz_gpio = gpio_chip_to_jz_gpio_chip(chip);
return jz_gpio->irq_base + gpio;
}
int jz_gpio_port_direction_input(int port, uint32_t mask)
{
writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_CLEAR));
@ -262,18 +269,6 @@ uint32_t jz_gpio_port_get_value(int port, uint32_t mask)
}
EXPORT_SYMBOL(jz_gpio_port_get_value);
int gpio_to_irq(unsigned gpio)
{
return JZ4740_IRQ_GPIO(0) + gpio;
}
EXPORT_SYMBOL_GPL(gpio_to_irq);
int irq_to_gpio(unsigned irq)
{
return irq - JZ4740_IRQ_GPIO(0);
}
EXPORT_SYMBOL_GPL(irq_to_gpio);
#define IRQ_TO_BIT(irq) BIT(irq_to_gpio(irq) & 0x1f)
static void jz_gpio_check_trigger_both(struct jz_gpio_chip *chip, unsigned int irq)
@ -403,6 +398,7 @@ static int jz_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
.get = jz_gpio_get_value, \
.direction_output = jz_gpio_direction_output, \
.direction_input = jz_gpio_direction_input, \
.to_irq = jz_gpio_to_irq, \
.base = JZ4740_GPIO_BASE_ ## _bank, \
.ngpio = JZ4740_GPIO_NUM_ ## _bank, \
}, \
@ -423,8 +419,8 @@ static void jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
chip->base = ioremap(JZ4740_GPIO_BASE_ADDR + (id * 0x100), 0x100);
chip->irq = JZ4740_IRQ_INTC_GPIO(id);
irq_set_handler_data(chip->irq, chip);
irq_set_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
irq_set_chained_handler_and_data(chip->irq,
jz_gpio_irq_demux_handler, chip);
gc = irq_alloc_generic_chip(chip->gpio_chip.label, 1, chip->irq_base,
chip->base, handle_level_irq);

46
arch/mips/jz4740/time.c
View File

@ -58,7 +58,7 @@ static irqreturn_t jz4740_clockevent_irq(int irq, void *devid)
jz4740_timer_ack_full(TIMER_CLOCKEVENT);
if (cd->mode != CLOCK_EVT_MODE_PERIODIC)
if (!clockevent_state_periodic(cd))
jz4740_timer_disable(TIMER_CLOCKEVENT);
cd->event_handler(cd);
@ -66,24 +66,29 @@ static irqreturn_t jz4740_clockevent_irq(int irq, void *devid)
return IRQ_HANDLED;
}
static void jz4740_clockevent_set_mode(enum clock_event_mode mode,
struct clock_event_device *cd)
static int jz4740_clockevent_set_periodic(struct clock_event_device *evt)
{
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
jz4740_timer_set_count(TIMER_CLOCKEVENT, 0);
jz4740_timer_set_period(TIMER_CLOCKEVENT, jz4740_jiffies_per_tick);
case CLOCK_EVT_MODE_RESUME:
jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT);
jz4740_timer_enable(TIMER_CLOCKEVENT);
break;
case CLOCK_EVT_MODE_ONESHOT:
case CLOCK_EVT_MODE_SHUTDOWN:
jz4740_timer_disable(TIMER_CLOCKEVENT);
break;
default:
break;
}
jz4740_timer_set_count(TIMER_CLOCKEVENT, 0);
jz4740_timer_set_period(TIMER_CLOCKEVENT, jz4740_jiffies_per_tick);
jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT);
jz4740_timer_enable(TIMER_CLOCKEVENT);
return 0;
}
static int jz4740_clockevent_resume(struct clock_event_device *evt)
{
jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT);
jz4740_timer_enable(TIMER_CLOCKEVENT);
return 0;
}
static int jz4740_clockevent_shutdown(struct clock_event_device *evt)
{
jz4740_timer_disable(TIMER_CLOCKEVENT);
return 0;
}
static int jz4740_clockevent_set_next(unsigned long evt,
@ -100,7 +105,10 @@ static struct clock_event_device jz4740_clockevent = {
.name = "jz4740-timer",
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.set_next_event = jz4740_clockevent_set_next,
.set_mode = jz4740_clockevent_set_mode,
.set_state_shutdown = jz4740_clockevent_shutdown,
.set_state_periodic = jz4740_clockevent_set_periodic,
.set_state_oneshot = jz4740_clockevent_shutdown,
.tick_resume = jz4740_clockevent_resume,
.rating = 200,
#ifdef CONFIG_MACH_JZ4740
.irq = JZ4740_IRQ_TCU0,

1
arch/mips/kernel/Makefile
View File

@ -99,6 +99,7 @@ obj-$(CONFIG_PERF_EVENTS) += perf_event.o
obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o
obj-$(CONFIG_JUMP_LABEL) += jump_label.o
obj-$(CONFIG_UPROBES) += uprobes.o
obj-$(CONFIG_MIPS_CM) += mips-cm.o
obj-$(CONFIG_MIPS_CPC) += mips-cpc.o

12
arch/mips/kernel/asm-offsets.c
View File

@ -128,6 +128,7 @@ void output_thread_defines(void)
thread.cp0_baduaddr);
OFFSET(THREAD_ECODE, task_struct, \
thread.error_code);
OFFSET(THREAD_TRAPNO, task_struct, thread.trap_nr);
BLANK();
}
@ -245,17 +246,6 @@ void output_sc_defines(void)
}
#endif
#ifdef CONFIG_MIPS32_COMPAT
void output_sc32_defines(void)
{
COMMENT("Linux 32-bit sigcontext offsets.");
OFFSET(SC32_FPREGS, sigcontext32, sc_fpregs);
OFFSET(SC32_FPC_CSR, sigcontext32, sc_fpc_csr);
OFFSET(SC32_FPC_EIR, sigcontext32, sc_fpc_eir);
BLANK();
}
#endif
void output_signal_defined(void)
{
COMMENT("Linux signal numbers.");

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