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drm/amd/display: Dynamic cursor cache size for MALL eligibility check

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[Why]
Currently we use the maximum possible cursor cache size when deciding if we
should attempt to enable MALL, but this prevents us from enabling the
feature for certain key use cases.

[How]
 - consider cursor bpp when calculating if the cursor fits

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Bhawanpreet Lakha 2021-01-19 14:10:21 -05:00 committed by Alex Deucher
parent b153d8d7d0
commit 7fc75382ec
6 changed files with 33 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/drm/amd/display/dc/core/dc.c
View File

@ -3156,11 +3156,11 @@ void dc_lock_memory_clock_frequency(struct dc *dc)
core_link_enable_stream(dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);
}
bool dc_is_plane_eligible_for_idle_optimizaitons(struct dc *dc, struct dc_plane_state *plane)
bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
struct dc_cursor_attributes *cursor_attr)
{
if (dc->hwss.does_plane_fit_in_mall && dc->hwss.does_plane_fit_in_mall(dc, plane))
if (dc->hwss.does_plane_fit_in_mall && dc->hwss.does_plane_fit_in_mall(dc, plane, cursor_attr))
return true;
return false;
}

4
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -1272,8 +1272,8 @@ enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32
void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
#if defined(CONFIG_DRM_AMD_DC_DCN)
bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc,
struct dc_plane_state *plane);
bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
struct dc_cursor_attributes *cursor_attr);
void dc_allow_idle_optimizations(struct dc *dc, bool allow);

25
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
View File

@ -814,17 +814,38 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
return true;
}
bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane)
bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane, struct dc_cursor_attributes *cursor_attr)
{
// add meta size?
unsigned int surface_size = plane->plane_size.surface_pitch * plane->plane_size.surface_size.height *
(plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4);
unsigned int mall_size = dc->caps.mall_size_total;
unsigned int cursor_size = 0;
if (dc->debug.mall_size_override)
mall_size = 1024 * 1024 * dc->debug.mall_size_override;
return (surface_size + dc->caps.cursor_cache_size) < mall_size;
if (cursor_attr) {
cursor_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size;
switch (cursor_attr->color_format) {
case CURSOR_MODE_MONO:
cursor_size /= 2;
break;
case CURSOR_MODE_COLOR_1BIT_AND:
case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
cursor_size *= 4;
break;
case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
cursor_size *= 8;
break;
}
}
return (surface_size + cursor_size) < mall_size;
}
void dcn30_hardware_release(struct dc *dc)

3
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
View File

@ -65,7 +65,8 @@ void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx);
void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx);
bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane);
bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane,
struct dc_cursor_attributes *cursor_attr);
bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable);

1
drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
View File

@ -1317,6 +1317,7 @@ static bool dcn302_resource_construct(
dc->caps.min_horizontal_blanking_period = 80;
dc->caps.dmdata_alloc_size = 2048;
dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
dc->caps.max_slave_planes = 1;
dc->caps.post_blend_color_processing = true;
dc->caps.force_dp_tps4_for_cp2520 = true;

3
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
View File

@ -218,7 +218,8 @@ struct hw_sequencer_funcs {
/* Idle Optimization Related */
bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable);
bool (*does_plane_fit_in_mall)(struct dc *dc, struct dc_plane_state *plane);
bool (*does_plane_fit_in_mall)(struct dc *dc, struct dc_plane_state *plane,
struct dc_cursor_attributes *cursor_attr);
bool (*is_abm_supported)(struct dc *dc,
struct dc_state *context, struct dc_stream_state *stream);