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media: platform: mtk-mdp3: Add support for MT8188 MDP3 components
MT8195 and MT8188 share a similar MDP3 macro-block, with minor differences - as in, the latter supports a subset of the number of components supported by the former, but are otherwise handled in the same way. Add driver data for MT8188, reusing the already present MT8195 data where possible. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Fei Shao <fshao@chromium.org> Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
This commit is contained in:
AngeloGioacchino Del Regno
Hans Verkuil
parent
8da17fe240
commit
7fc65b78b4
@ -46,6 +46,53 @@ enum mt8183_mdp_comp_id {
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MT8183_MDP_COMP_WROT1, /* 25 */
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};
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enum mt8188_mdp_comp_id {
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/* MT8188 Comp id */
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/* ISP */
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MT8188_MDP_COMP_WPEI = 0,
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MT8188_MDP_COMP_WPEO, /* 1 */
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/* MDP */
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MT8188_MDP_COMP_CAMIN, /* 2 */
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MT8188_MDP_COMP_RDMA0, /* 3 */
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MT8188_MDP_COMP_RDMA2, /* 4 */
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MT8188_MDP_COMP_RDMA3, /* 5 */
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MT8188_MDP_COMP_FG0, /* 6 */
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MT8188_MDP_COMP_FG2, /* 7 */
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MT8188_MDP_COMP_FG3, /* 8 */
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MT8188_MDP_COMP_TO_SVPP2MOUT, /* 9 */
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MT8188_MDP_COMP_TO_SVPP3MOUT, /* 10 */
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MT8188_MDP_COMP_TO_WARP0MOUT, /* 11 */
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MT8188_MDP_COMP_VPP0_SOUT, /* 12 */
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MT8188_MDP_COMP_VPP1_SOUT, /* 13 */
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MT8188_MDP_COMP_PQ0_SOUT, /* 14 */
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MT8188_MDP_COMP_HDR0, /* 15 */
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MT8188_MDP_COMP_HDR2, /* 16 */
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MT8188_MDP_COMP_HDR3, /* 17 */
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MT8188_MDP_COMP_AAL0, /* 18 */
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MT8188_MDP_COMP_AAL2, /* 19 */
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MT8188_MDP_COMP_AAL3, /* 20 */
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MT8188_MDP_COMP_RSZ0, /* 21 */
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MT8188_MDP_COMP_RSZ2, /* 22 */
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MT8188_MDP_COMP_RSZ3, /* 23 */
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MT8188_MDP_COMP_TDSHP0, /* 24 */
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MT8188_MDP_COMP_TDSHP2, /* 25 */
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MT8188_MDP_COMP_TDSHP3, /* 26 */
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MT8188_MDP_COMP_COLOR0, /* 27 */
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MT8188_MDP_COMP_COLOR2, /* 28 */
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MT8188_MDP_COMP_COLOR3, /* 29 */
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MT8188_MDP_COMP_OVL0, /* 30 */
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MT8188_MDP_COMP_PAD0, /* 31 */
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MT8188_MDP_COMP_PAD2, /* 32 */
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MT8188_MDP_COMP_PAD3, /* 33 */
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MT8188_MDP_COMP_TCC0, /* 34 */
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MT8188_MDP_COMP_WROT0, /* 35 */
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MT8188_MDP_COMP_WROT2, /* 36 */
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MT8188_MDP_COMP_WROT3, /* 37 */
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MT8188_MDP_COMP_MERGE2, /* 38 */
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MT8188_MDP_COMP_MERGE3, /* 39 */
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};
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enum mt8195_mdp_comp_id {
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/* MT8195 Comp id */
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/* ISP */
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@ -123,6 +170,13 @@ static const struct of_device_id mt8183_mdp_probe_infra[MDP_INFRA_MAX] = {
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[MDP_INFRA_SCP] = { .compatible = "mediatek,mt8183-scp" }
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};
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static const struct of_device_id mt8188_mdp_probe_infra[MDP_INFRA_MAX] = {
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[MDP_INFRA_MMSYS] = { .compatible = "mediatek,mt8188-vppsys0" },
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[MDP_INFRA_MMSYS2] = { .compatible = "mediatek,mt8188-vppsys1" },
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[MDP_INFRA_MUTEX] = { .compatible = "mediatek,mt8188-vpp-mutex" },
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[MDP_INFRA_MUTEX2] = { .compatible = "mediatek,mt8188-vpp-mutex" },
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};
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static const struct of_device_id mt8195_mdp_probe_infra[MDP_INFRA_MAX] = {
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[MDP_INFRA_MMSYS] = { .compatible = "mediatek,mt8195-vppsys0" },
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[MDP_INFRA_MMSYS2] = { .compatible = "mediatek,mt8195-vppsys1" },
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@ -167,6 +221,40 @@ static const u32 mt8183_mutex_idx[MDP_MAX_COMP_COUNT] = {
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[MDP_COMP_CCORR0] = MUTEX_MOD_IDX_MDP_CCORR0,
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};
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static const u32 mt8188_mutex_idx[MDP_MAX_COMP_COUNT] = {
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[MDP_COMP_RDMA0] = MUTEX_MOD_IDX_MDP_RDMA0,
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[MDP_COMP_RDMA2] = MUTEX_MOD_IDX_MDP_RDMA2,
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[MDP_COMP_RDMA3] = MUTEX_MOD_IDX_MDP_RDMA3,
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[MDP_COMP_FG0] = MUTEX_MOD_IDX_MDP_FG0,
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[MDP_COMP_FG2] = MUTEX_MOD_IDX_MDP_FG2,
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[MDP_COMP_FG3] = MUTEX_MOD_IDX_MDP_FG3,
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[MDP_COMP_HDR0] = MUTEX_MOD_IDX_MDP_HDR0,
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[MDP_COMP_HDR2] = MUTEX_MOD_IDX_MDP_HDR2,
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[MDP_COMP_HDR3] = MUTEX_MOD_IDX_MDP_HDR3,
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[MDP_COMP_AAL0] = MUTEX_MOD_IDX_MDP_AAL0,
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[MDP_COMP_AAL2] = MUTEX_MOD_IDX_MDP_AAL2,
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[MDP_COMP_AAL3] = MUTEX_MOD_IDX_MDP_AAL3,
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[MDP_COMP_RSZ0] = MUTEX_MOD_IDX_MDP_RSZ0,
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[MDP_COMP_RSZ2] = MUTEX_MOD_IDX_MDP_RSZ2,
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[MDP_COMP_RSZ3] = MUTEX_MOD_IDX_MDP_RSZ3,
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[MDP_COMP_MERGE2] = MUTEX_MOD_IDX_MDP_MERGE2,
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[MDP_COMP_MERGE3] = MUTEX_MOD_IDX_MDP_MERGE3,
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[MDP_COMP_TDSHP0] = MUTEX_MOD_IDX_MDP_TDSHP0,
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[MDP_COMP_TDSHP2] = MUTEX_MOD_IDX_MDP_TDSHP2,
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[MDP_COMP_TDSHP3] = MUTEX_MOD_IDX_MDP_TDSHP3,
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[MDP_COMP_COLOR0] = MUTEX_MOD_IDX_MDP_COLOR0,
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[MDP_COMP_COLOR2] = MUTEX_MOD_IDX_MDP_COLOR2,
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[MDP_COMP_COLOR3] = MUTEX_MOD_IDX_MDP_COLOR3,
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[MDP_COMP_OVL0] = MUTEX_MOD_IDX_MDP_OVL0,
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[MDP_COMP_PAD0] = MUTEX_MOD_IDX_MDP_PAD0,
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[MDP_COMP_PAD2] = MUTEX_MOD_IDX_MDP_PAD2,
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[MDP_COMP_PAD3] = MUTEX_MOD_IDX_MDP_PAD3,
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[MDP_COMP_TCC0] = MUTEX_MOD_IDX_MDP_TCC0,
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[MDP_COMP_WROT0] = MUTEX_MOD_IDX_MDP_WROT0,
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[MDP_COMP_WROT2] = MUTEX_MOD_IDX_MDP_WROT2,
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[MDP_COMP_WROT3] = MUTEX_MOD_IDX_MDP_WROT3,
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};
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static const u32 mt8195_mutex_idx[MDP_MAX_COMP_COUNT] = {
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[MDP_COMP_RDMA0] = MUTEX_MOD_IDX_MDP_RDMA0,
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[MDP_COMP_RDMA1] = MUTEX_MOD_IDX_MDP_RDMA1,
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@ -288,6 +376,171 @@ static const struct mdp_comp_data mt8183_mdp_comp_data[MDP_MAX_COMP_COUNT] = {
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},
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};
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static const struct mdp_comp_data mt8188_mdp_comp_data[MDP_MAX_COMP_COUNT] = {
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[MDP_COMP_WPEI] = {
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{MDP_COMP_TYPE_WPEI, 0, MT8188_MDP_COMP_WPEI, MDP_MM_SUBSYS_0},
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{0, 0, 0}
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},
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[MDP_COMP_WPEO] = {
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{MDP_COMP_TYPE_EXTO, 0, MT8188_MDP_COMP_WPEO, MDP_MM_SUBSYS_0},
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{0, 0, 0}
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},
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[MDP_COMP_CAMIN] = {
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{MDP_COMP_TYPE_DL_PATH, 0, MT8188_MDP_COMP_CAMIN, MDP_MM_SUBSYS_0},
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{3, 3, 0}
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},
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[MDP_COMP_RDMA0] = {
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{MDP_COMP_TYPE_RDMA, 0, MT8188_MDP_COMP_RDMA0, MDP_MM_SUBSYS_0},
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{3, 0, 0}
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},
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[MDP_COMP_RDMA2] = {
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{MDP_COMP_TYPE_RDMA, 1, MT8188_MDP_COMP_RDMA2, MDP_MM_SUBSYS_1},
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{3, 0, 0}
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},
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[MDP_COMP_RDMA3] = {
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{MDP_COMP_TYPE_RDMA, 2, MT8188_MDP_COMP_RDMA3, MDP_MM_SUBSYS_1},
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{3, 0, 0}
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},
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[MDP_COMP_FG0] = {
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{MDP_COMP_TYPE_FG, 0, MT8188_MDP_COMP_FG0, MDP_MM_SUBSYS_0},
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{1, 0, 0}
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},
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[MDP_COMP_FG2] = {
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{MDP_COMP_TYPE_FG, 1, MT8188_MDP_COMP_FG2, MDP_MM_SUBSYS_1},
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{1, 0, 0}
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},
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[MDP_COMP_FG3] = {
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{MDP_COMP_TYPE_FG, 2, MT8188_MDP_COMP_FG3, MDP_MM_SUBSYS_1},
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{1, 0, 0}
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},
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[MDP_COMP_HDR0] = {
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{MDP_COMP_TYPE_HDR, 0, MT8188_MDP_COMP_HDR0, MDP_MM_SUBSYS_0},
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{1, 0, 0}
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},
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[MDP_COMP_HDR2] = {
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{MDP_COMP_TYPE_HDR, 1, MT8188_MDP_COMP_HDR2, MDP_MM_SUBSYS_1},
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{1, 0, 0}
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},
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[MDP_COMP_HDR3] = {
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{MDP_COMP_TYPE_HDR, 2, MT8188_MDP_COMP_HDR3, MDP_MM_SUBSYS_1},
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{1, 0, 0}
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},
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[MDP_COMP_AAL0] = {
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{MDP_COMP_TYPE_AAL, 0, MT8188_MDP_COMP_AAL0, MDP_MM_SUBSYS_0},
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{1, 0, 0}
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},
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[MDP_COMP_AAL2] = {
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{MDP_COMP_TYPE_AAL, 1, MT8188_MDP_COMP_AAL2, MDP_MM_SUBSYS_1},
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{1, 0, 0}
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},
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[MDP_COMP_AAL3] = {
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{MDP_COMP_TYPE_AAL, 2, MT8188_MDP_COMP_AAL3, MDP_MM_SUBSYS_1},
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{1, 0, 0}
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},
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[MDP_COMP_RSZ0] = {
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{MDP_COMP_TYPE_RSZ, 0, MT8188_MDP_COMP_RSZ0, MDP_MM_SUBSYS_0},
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{1, 0, 0}
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},
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[MDP_COMP_RSZ2] = {
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{MDP_COMP_TYPE_RSZ, 1, MT8188_MDP_COMP_RSZ2, MDP_MM_SUBSYS_1},
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{2, 0, 0},
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{MDP_COMP_MERGE2, true, true}
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},
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[MDP_COMP_RSZ3] = {
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{MDP_COMP_TYPE_RSZ, 2, MT8188_MDP_COMP_RSZ3, MDP_MM_SUBSYS_1},
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{2, 0, 0},
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{MDP_COMP_MERGE3, true, true}
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},
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[MDP_COMP_TDSHP0] = {
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{MDP_COMP_TYPE_TDSHP, 0, MT8188_MDP_COMP_TDSHP0, MDP_MM_SUBSYS_0},
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{1, 0, 0}
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},
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[MDP_COMP_TDSHP2] = {
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{MDP_COMP_TYPE_TDSHP, 1, MT8188_MDP_COMP_TDSHP2, MDP_MM_SUBSYS_1},
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{1, 0, 0}
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},
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[MDP_COMP_TDSHP3] = {
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{MDP_COMP_TYPE_TDSHP, 2, MT8188_MDP_COMP_TDSHP3, MDP_MM_SUBSYS_1},
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{1, 0, 0}
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},
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[MDP_COMP_COLOR0] = {
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{MDP_COMP_TYPE_COLOR, 0, MT8188_MDP_COMP_COLOR0, MDP_MM_SUBSYS_0},
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{1, 0, 0}
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},
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[MDP_COMP_COLOR2] = {
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{MDP_COMP_TYPE_COLOR, 1, MT8188_MDP_COMP_COLOR2, MDP_MM_SUBSYS_1},
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{1, 0, 0}
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},
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[MDP_COMP_COLOR3] = {
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{MDP_COMP_TYPE_COLOR, 2, MT8188_MDP_COMP_COLOR3, MDP_MM_SUBSYS_1},
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{1, 0, 0}
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},
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[MDP_COMP_OVL0] = {
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{MDP_COMP_TYPE_OVL, 0, MT8188_MDP_COMP_OVL0, MDP_MM_SUBSYS_0},
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{1, 0, 0}
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},
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[MDP_COMP_PAD0] = {
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{MDP_COMP_TYPE_PAD, 0, MT8188_MDP_COMP_PAD0, MDP_MM_SUBSYS_0},
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{1, 0, 0}
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},
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[MDP_COMP_PAD2] = {
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{MDP_COMP_TYPE_PAD, 1, MT8188_MDP_COMP_PAD2, MDP_MM_SUBSYS_1},
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{1, 0, 0}
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},
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[MDP_COMP_PAD3] = {
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{MDP_COMP_TYPE_PAD, 2, MT8188_MDP_COMP_PAD3, MDP_MM_SUBSYS_1},
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{1, 0, 0}
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},
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[MDP_COMP_TCC0] = {
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{MDP_COMP_TYPE_TCC, 0, MT8188_MDP_COMP_TCC0, MDP_MM_SUBSYS_0},
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{1, 0, 0}
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},
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[MDP_COMP_WROT0] = {
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{MDP_COMP_TYPE_WROT, 0, MT8188_MDP_COMP_WROT0, MDP_MM_SUBSYS_0},
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{1, 0, 0}
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},
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[MDP_COMP_WROT2] = {
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{MDP_COMP_TYPE_WROT, 1, MT8188_MDP_COMP_WROT2, MDP_MM_SUBSYS_1},
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{1, 0, 0}
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},
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[MDP_COMP_WROT3] = {
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{MDP_COMP_TYPE_WROT, 2, MT8188_MDP_COMP_WROT3, MDP_MM_SUBSYS_1},
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{1, 0, 0}
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},
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[MDP_COMP_MERGE2] = {
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{MDP_COMP_TYPE_MERGE, 0, MT8188_MDP_COMP_MERGE2, MDP_MM_SUBSYS_1},
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{1, 0, 0}
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},
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[MDP_COMP_MERGE3] = {
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{MDP_COMP_TYPE_MERGE, 1, MT8188_MDP_COMP_MERGE3, MDP_MM_SUBSYS_1},
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{1, 0, 0}
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},
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[MDP_COMP_PQ0_SOUT] = {
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{MDP_COMP_TYPE_DUMMY, 0, MT8188_MDP_COMP_PQ0_SOUT, MDP_MM_SUBSYS_0},
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{0, 0, 0}
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},
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[MDP_COMP_TO_WARP0MOUT] = {
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{MDP_COMP_TYPE_DUMMY, 1, MT8188_MDP_COMP_TO_WARP0MOUT, MDP_MM_SUBSYS_0},
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{0, 0, 0}
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},
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[MDP_COMP_TO_SVPP2MOUT] = {
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{MDP_COMP_TYPE_DUMMY, 2, MT8188_MDP_COMP_TO_SVPP2MOUT, MDP_MM_SUBSYS_1},
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{0, 0, 0}
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},
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[MDP_COMP_TO_SVPP3MOUT] = {
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{MDP_COMP_TYPE_DUMMY, 3, MT8188_MDP_COMP_TO_SVPP3MOUT, MDP_MM_SUBSYS_1},
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{0, 0, 0}
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},
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[MDP_COMP_VPP0_SOUT] = {
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{MDP_COMP_TYPE_PATH, 0, MT8188_MDP_COMP_VPP0_SOUT, MDP_MM_SUBSYS_1},
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{2, 6, 0}
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},
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[MDP_COMP_VPP1_SOUT] = {
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{MDP_COMP_TYPE_PATH, 1, MT8188_MDP_COMP_VPP1_SOUT, MDP_MM_SUBSYS_0},
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{2, 8, 0}
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},
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};
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static const struct mdp_comp_data mt8195_mdp_comp_data[MDP_MAX_COMP_COUNT] = {
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[MDP_COMP_WPEI] = {
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{MDP_COMP_TYPE_WPEI, 0, MT8195_MDP_COMP_WPEI, MDP_MM_SUBSYS_0},
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@ -1046,6 +1299,15 @@ static const struct mdp_pipe_info mt8183_pipe_info[] = {
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[MDP_PIPE_RDMA0] = {MDP_PIPE_RDMA0, MDP_MM_SUBSYS_0, 3}
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};
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static const struct mdp_pipe_info mt8188_pipe_info[] = {
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[MDP_PIPE_WPEI] = {MDP_PIPE_WPEI, MDP_MM_SUBSYS_0, 0},
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[MDP_PIPE_RDMA0] = {MDP_PIPE_RDMA0, MDP_MM_SUBSYS_0, 1},
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[MDP_PIPE_RDMA2] = {MDP_PIPE_RDMA2, MDP_MM_SUBSYS_1, 0},
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[MDP_PIPE_RDMA3] = {MDP_PIPE_RDMA3, MDP_MM_SUBSYS_1, 1},
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[MDP_PIPE_VPP1_SOUT] = {MDP_PIPE_VPP1_SOUT, MDP_MM_SUBSYS_0, 2},
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[MDP_PIPE_VPP0_SOUT] = {MDP_PIPE_VPP0_SOUT, MDP_MM_SUBSYS_1, 2},
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};
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static const struct mdp_pipe_info mt8195_pipe_info[] = {
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[MDP_PIPE_WPEI] = {MDP_PIPE_WPEI, MDP_MM_SUBSYS_0, 0},
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[MDP_PIPE_WPEI2] = {MDP_PIPE_WPEI2, MDP_MM_SUBSYS_0, 1},
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@ -1082,6 +1344,24 @@ const struct mtk_mdp_driver_data mt8183_mdp_driver_data = {
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.pp_used = MDP_PP_USED_1,
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};
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const struct mtk_mdp_driver_data mt8188_mdp_driver_data = {
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.mdp_plat_id = MT8188,
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.mdp_con_res = 0x14001000,
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.mdp_probe_infra = mt8188_mdp_probe_infra,
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.mdp_sub_comp_dt_ids = mt8195_sub_comp_dt_ids,
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.mdp_cfg = &mt8195_plat_cfg,
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.mdp_mutex_table_idx = mt8188_mutex_idx,
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.comp_data = mt8188_mdp_comp_data,
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.comp_data_len = ARRAY_SIZE(mt8188_mdp_comp_data),
|
||||
.format = mt8195_formats,
|
||||
.format_len = ARRAY_SIZE(mt8195_formats),
|
||||
.def_limit = &mt8195_mdp_def_limit,
|
||||
.pipe_info = mt8188_pipe_info,
|
||||
.pipe_info_len = ARRAY_SIZE(mt8188_pipe_info),
|
||||
.pp_criteria = &mt8195_mdp_pp_criteria,
|
||||
.pp_used = MDP_PP_USED_2,
|
||||
};
|
||||
|
||||
const struct mtk_mdp_driver_data mt8195_mdp_driver_data = {
|
||||
.mdp_plat_id = MT8195,
|
||||
.mdp_con_res = 0x14001000,
|
||||
|
||||
@ -116,6 +116,7 @@ struct img_frameparam {
|
||||
|
||||
/* Platform config indicator */
|
||||
#define MT8183 8183
|
||||
#define MT8188 8195
|
||||
#define MT8195 8195
|
||||
|
||||
#define CFG_CHECK(plat, p_id) ((plat) == (p_id))
|
||||
|
||||
@ -10,6 +10,7 @@
|
||||
#include <linux/types.h>
|
||||
|
||||
extern const struct mtk_mdp_driver_data mt8183_mdp_driver_data;
|
||||
extern const struct mtk_mdp_driver_data mt8188_mdp_driver_data;
|
||||
extern const struct mtk_mdp_driver_data mt8195_mdp_driver_data;
|
||||
|
||||
struct mdp_dev;
|
||||
|
||||
@ -21,6 +21,9 @@ static const struct of_device_id mdp_of_ids[] = {
|
||||
{ .compatible = "mediatek,mt8183-mdp3-rdma",
|
||||
.data = &mt8183_mdp_driver_data,
|
||||
},
|
||||
{ .compatible = "mediatek,mt8188-mdp3-rdma",
|
||||
.data = &mt8188_mdp_driver_data,
|
||||
},
|
||||
{ .compatible = "mediatek,mt8195-mdp3-rdma",
|
||||
.data = &mt8195_mdp_driver_data,
|
||||
},
|
||||
|
||||
Loading…
Reference in New Issue
Block a user