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arm64: tegra: Fixup SYSRAM references
The json-schema bindings for SRAM expect the nodes to be called "sram" rather than "sysram" or "shmem". Furthermore, place the brackets around the SYSRAM references such that a two-element array is created rather than a two-element array nested in a single-element array. This is not relevant for device tree itself, but allows the nodes to be properly validated against json-schema bindings. Signed-off-by: Thierry Reding <treding@nvidia.com>
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@ -1771,7 +1771,7 @@
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iommus = <&smmu TEGRA186_SID_BPMP>;
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mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
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TEGRA_HSP_DB_MASTER_BPMP>;
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shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
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shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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@ -2467,7 +2467,7 @@
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compatible = "nvidia,tegra186-bpmp";
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mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
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TEGRA_HSP_DB_MASTER_BPMP>;
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shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
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shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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@ -122,20 +122,20 @@
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};
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};
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sysram@40000000 {
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sram@40000000 {
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compatible = "nvidia,tegra234-sysram", "mmio-sram";
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reg = <0x0 0x40000000 0x0 0x50000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x40000000 0x50000>;
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cpu_bpmp_tx: shmem@4e000 {
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cpu_bpmp_tx: sram@4e000 {
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reg = <0x4e000 0x1000>;
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label = "cpu-bpmp-tx";
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pool;
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};
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cpu_bpmp_rx: shmem@4f000 {
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cpu_bpmp_rx: sram@4f000 {
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reg = <0x4f000 0x1000>;
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label = "cpu-bpmp-rx";
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pool;
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@ -146,7 +146,7 @@
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compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp";
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mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
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TEGRA_HSP_DB_MASTER_BPMP>;
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shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
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shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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