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drm/i915: fix PCH eDP SSC support

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Enable SSC on PCH eDP if possible.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[ickle: added a posting read of PCH_DREF_CONTROL before the udelay]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Jesse Barnes 2010-10-07 16:01:16 -07:00 committed by Chris Wilson
parent 5b2adf8971
commit 7f82328268
1 changed files with 15 additions and 3 deletions
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18
drivers/gpu/drm/i915/intel_display.c
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@ -3796,13 +3796,25 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
POSTING_READ(PCH_DREF_CONTROL);
udelay(200);
}
temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
/* Enable CPU source on CPU attached eDP */
if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
if (dev_priv->lvds_use_ssc)
temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
else
temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
} else {
temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
/* Enable SSC on PCH eDP if needed */
if (dev_priv->lvds_use_ssc) {
DRM_ERROR("enabling SSC on PCH\n");
temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
}
}
I915_WRITE(PCH_DREF_CONTROL, temp);
POSTING_READ(PCH_DREF_CONTROL);
udelay(200);
}
}