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MIPS: Add MSA register definitions & access
This patch introduces definitions for the MSA control registers and functions which allow access to both the control & vector registers. If the toolchain being used to build the kernel includes support for MSA then this patch will make use of that support & use MSA instructions directly. However toolchain support for MSA is very new & far from a point where it can be reasonably expected that everyone building the kernel uses a toolchain with support. Thus fallbacks using .word assembler directives are also provided for now as a temporary measure. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6429/ Patchwork: https://patchwork.linux-mips.org/patch/6607/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Paul Burton
Ralf Baechle
parent
02987633df
commit
7f65afb97f
@ -119,6 +119,11 @@ cflags-$(CONFIG_CPU_MICROMIPS) += $(call cc-option,-mmicromips)
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cflags-$(CONFIG_SB1XXX_CORELIS) += $(call cc-option,-mno-sched-prolog) \
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-fno-omit-frame-pointer
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ifeq ($(CONFIG_CPU_HAS_MSA),y)
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toolchain-msa := $(call cc-option-yn,-mhard-float -mfp64 -mmsa)
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cflags-$(toolchain-msa) += -DTOOLCHAIN_SUPPORTS_MSA
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endif
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#
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# CPU-dependent compiler/assembler options for optimization.
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#
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@ -207,4 +207,125 @@
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.word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
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.endm
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#ifdef TOOLCHAIN_SUPPORTS_MSA
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.macro ld_d wd, off, base
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.set push
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.set mips32r2
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.set msa
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ld.d $w\wd, \off(\base)
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.set pop
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.endm
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.macro st_d wd, off, base
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.set push
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.set mips32r2
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.set msa
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st.d $w\wd, \off(\base)
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.set pop
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.endm
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.macro copy_u_w rd, ws, n
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.set push
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.set mips32r2
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.set msa
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copy_u.w \rd, $w\ws[\n]
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.set pop
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.endm
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.macro copy_u_d rd, ws, n
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.set push
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.set mips64r2
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.set msa
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copy_u.d \rd, $w\ws[\n]
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.set pop
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.endm
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.macro insert_w wd, n, rs
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.set push
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.set mips32r2
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.set msa
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insert.w $w\wd[\n], \rs
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.set pop
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.endm
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.macro insert_d wd, n, rs
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.set push
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.set mips64r2
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.set msa
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insert.d $w\wd[\n], \rs
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.set pop
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.endm
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#else
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/*
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* Temporary until all toolchains in use include MSA support.
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*/
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.macro cfcmsa rd, cs
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.set push
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.set noat
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.word 0x787e0059 | (\cs << 11)
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move \rd, $1
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.set pop
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.endm
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.macro ctcmsa cd, rs
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.set push
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.set noat
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move $1, \rs
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.word 0x783e0819 | (\cd << 6)
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.set pop
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.endm
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.macro ld_d wd, off, base
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.set push
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.set noat
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add $1, \base, \off
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.word 0x78000823 | (\wd << 6)
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.set pop
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.endm
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.macro st_d wd, off, base
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.set push
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.set noat
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add $1, \base, \off
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.word 0x78000827 | (\wd << 6)
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.set pop
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.endm
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.macro copy_u_w rd, ws, n
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.set push
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.set noat
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.word 0x78f00059 | (\n << 16) | (\ws << 11)
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/* move triggers an assembler bug... */
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or \rd, $1, zero
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.set pop
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.endm
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.macro copy_u_d rd, ws, n
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.set push
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.set noat
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.word 0x78f80059 | (\n << 16) | (\ws << 11)
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/* move triggers an assembler bug... */
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or \rd, $1, zero
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.set pop
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.endm
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.macro insert_w wd, n, rs
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.set push
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.set noat
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/* move triggers an assembler bug... */
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or $1, \rs, zero
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.word 0x79300819 | (\n << 16) | (\wd << 6)
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.set pop
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.endm
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.macro insert_d wd, n, rs
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.set push
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.set noat
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/* move triggers an assembler bug... */
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or $1, \rs, zero
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.word 0x79380819 | (\n << 16) | (\wd << 6)
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.set pop
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.endm
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#endif
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#endif /* _ASM_ASMMACRO_H */
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@ -1904,6 +1904,7 @@ change_c0_##name(unsigned int change, unsigned int newbits) \
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__BUILD_SET_C0(status)
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__BUILD_SET_C0(cause)
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__BUILD_SET_C0(config)
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__BUILD_SET_C0(config5)
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__BUILD_SET_C0(intcontrol)
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__BUILD_SET_C0(intctl)
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__BUILD_SET_C0(srsmap)
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175
arch/mips/include/asm/msa.h
Normal file
175
arch/mips/include/asm/msa.h
Normal file
@ -0,0 +1,175 @@
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/*
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* Copyright (C) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef _ASM_MSA_H
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#define _ASM_MSA_H
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#include <asm/mipsregs.h>
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static inline void enable_msa(void)
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{
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if (cpu_has_msa) {
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set_c0_config5(MIPS_CONF5_MSAEN);
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enable_fpu_hazard();
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}
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}
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static inline void disable_msa(void)
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{
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if (cpu_has_msa) {
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clear_c0_config5(MIPS_CONF5_MSAEN);
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disable_fpu_hazard();
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}
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}
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static inline int is_msa_enabled(void)
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{
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if (!cpu_has_msa)
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return 0;
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return read_c0_config5() & MIPS_CONF5_MSAEN;
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}
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#ifdef TOOLCHAIN_SUPPORTS_MSA
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#define __BUILD_MSA_CTL_REG(name, cs) \
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static inline unsigned int read_msa_##name(void) \
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{ \
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unsigned int reg; \
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__asm__ __volatile__( \
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" .set push\n" \
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" .set msa\n" \
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" cfcmsa %0, $" #cs "\n" \
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" .set pop\n" \
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: "=r"(reg)); \
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return reg; \
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} \
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\
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static inline void write_msa_##name(unsigned int val) \
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{ \
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__asm__ __volatile__( \
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" .set push\n" \
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" .set msa\n" \
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" cfcmsa $" #cs ", %0\n" \
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" .set pop\n" \
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: : "r"(val)); \
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}
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#else /* !TOOLCHAIN_SUPPORTS_MSA */
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/*
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* Define functions using .word for the c[ft]cmsa instructions in order to
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* allow compilation with toolchains that do not support MSA. Once all
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* toolchains in use support MSA these can be removed.
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*/
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#define __BUILD_MSA_CTL_REG(name, cs) \
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static inline unsigned int read_msa_##name(void) \
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{ \
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unsigned int reg; \
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__asm__ __volatile__( \
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" .set push\n" \
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" .set noat\n" \
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" .word 0x787e0059 | (" #cs " << 11)\n" \
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" move %0, $1\n" \
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" .set pop\n" \
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: "=r"(reg)); \
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return reg; \
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} \
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\
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static inline void write_msa_##name(unsigned int val) \
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{ \
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__asm__ __volatile__( \
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" .set push\n" \
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" .set noat\n" \
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" move $1, %0\n" \
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" .word 0x783e0819 | (" #cs " << 6)\n" \
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" .set pop\n" \
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: : "r"(val)); \
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}
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#endif /* !TOOLCHAIN_SUPPORTS_MSA */
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#define MSA_IR 0
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#define MSA_CSR 1
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#define MSA_ACCESS 2
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#define MSA_SAVE 3
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#define MSA_MODIFY 4
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#define MSA_REQUEST 5
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#define MSA_MAP 6
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#define MSA_UNMAP 7
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__BUILD_MSA_CTL_REG(ir, 0)
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__BUILD_MSA_CTL_REG(csr, 1)
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__BUILD_MSA_CTL_REG(access, 2)
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__BUILD_MSA_CTL_REG(save, 3)
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__BUILD_MSA_CTL_REG(modify, 4)
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__BUILD_MSA_CTL_REG(request, 5)
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__BUILD_MSA_CTL_REG(map, 6)
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__BUILD_MSA_CTL_REG(unmap, 7)
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/* MSA Implementation Register (MSAIR) */
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#define MSA_IR_REVB 0
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#define MSA_IR_REVF (_ULCAST_(0xff) << MSA_IR_REVB)
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#define MSA_IR_PROCB 8
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#define MSA_IR_PROCF (_ULCAST_(0xff) << MSA_IR_PROCB)
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#define MSA_IR_WRPB 16
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#define MSA_IR_WRPF (_ULCAST_(0x1) << MSA_IR_WRPB)
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/* MSA Control & Status Register (MSACSR) */
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#define MSA_CSR_RMB 0
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#define MSA_CSR_RMF (_ULCAST_(0x3) << MSA_CSR_RMB)
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#define MSA_CSR_RM_NEAREST 0
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#define MSA_CSR_RM_TO_ZERO 1
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#define MSA_CSR_RM_TO_POS 2
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#define MSA_CSR_RM_TO_NEG 3
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#define MSA_CSR_FLAGSB 2
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#define MSA_CSR_FLAGSF (_ULCAST_(0x1f) << MSA_CSR_FLAGSB)
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#define MSA_CSR_FLAGS_IB 2
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#define MSA_CSR_FLAGS_IF (_ULCAST_(0x1) << MSA_CSR_FLAGS_IB)
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#define MSA_CSR_FLAGS_UB 3
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#define MSA_CSR_FLAGS_UF (_ULCAST_(0x1) << MSA_CSR_FLAGS_UB)
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#define MSA_CSR_FLAGS_OB 4
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#define MSA_CSR_FLAGS_OF (_ULCAST_(0x1) << MSA_CSR_FLAGS_OB)
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#define MSA_CSR_FLAGS_ZB 5
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#define MSA_CSR_FLAGS_ZF (_ULCAST_(0x1) << MSA_CSR_FLAGS_ZB)
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#define MSA_CSR_FLAGS_VB 6
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#define MSA_CSR_FLAGS_VF (_ULCAST_(0x1) << MSA_CSR_FLAGS_VB)
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#define MSA_CSR_ENABLESB 7
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#define MSA_CSR_ENABLESF (_ULCAST_(0x1f) << MSA_CSR_ENABLESB)
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#define MSA_CSR_ENABLES_IB 7
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#define MSA_CSR_ENABLES_IF (_ULCAST_(0x1) << MSA_CSR_ENABLES_IB)
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#define MSA_CSR_ENABLES_UB 8
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#define MSA_CSR_ENABLES_UF (_ULCAST_(0x1) << MSA_CSR_ENABLES_UB)
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#define MSA_CSR_ENABLES_OB 9
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#define MSA_CSR_ENABLES_OF (_ULCAST_(0x1) << MSA_CSR_ENABLES_OB)
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#define MSA_CSR_ENABLES_ZB 10
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#define MSA_CSR_ENABLES_ZF (_ULCAST_(0x1) << MSA_CSR_ENABLES_ZB)
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#define MSA_CSR_ENABLES_VB 11
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#define MSA_CSR_ENABLES_VF (_ULCAST_(0x1) << MSA_CSR_ENABLES_VB)
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#define MSA_CSR_CAUSEB 12
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#define MSA_CSR_CAUSEF (_ULCAST_(0x3f) << MSA_CSR_CAUSEB)
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#define MSA_CSR_CAUSE_IB 12
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#define MSA_CSR_CAUSE_IF (_ULCAST_(0x1) << MSA_CSR_CAUSE_IB)
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#define MSA_CSR_CAUSE_UB 13
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#define MSA_CSR_CAUSE_UF (_ULCAST_(0x1) << MSA_CSR_CAUSE_UB)
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#define MSA_CSR_CAUSE_OB 14
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#define MSA_CSR_CAUSE_OF (_ULCAST_(0x1) << MSA_CSR_CAUSE_OB)
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#define MSA_CSR_CAUSE_ZB 15
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#define MSA_CSR_CAUSE_ZF (_ULCAST_(0x1) << MSA_CSR_CAUSE_ZB)
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#define MSA_CSR_CAUSE_VB 16
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#define MSA_CSR_CAUSE_VF (_ULCAST_(0x1) << MSA_CSR_CAUSE_VB)
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#define MSA_CSR_CAUSE_EB 17
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#define MSA_CSR_CAUSE_EF (_ULCAST_(0x1) << MSA_CSR_CAUSE_EB)
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#define MSA_CSR_NXB 18
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#define MSA_CSR_NXF (_ULCAST_(0x1) << MSA_CSR_NXB)
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#define MSA_CSR_FSB 24
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#define MSA_CSR_FSF (_ULCAST_(0x1) << MSA_CSR_FSB)
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#endif /* _ASM_MSA_H */
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