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[media] v4l: vsp1: Add support for the R-Car Gen3 VSP2
Add DT compatible strings for the VSP2 instances found in the R-Car Gen3 SoCs and support them in the vsp1 driver. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
This commit is contained in:
Laurent Pinchart
Mauro Carvalho Chehab
parent
7b4baddca6
commit
7f2d50f8da
@ -1,24 +1,26 @@
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* Renesas VSP1 Video Processing Engine
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* Renesas VSP Video Processing Engine
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The VSP1 is a video processing engine that supports up-/down-scaling, alpha
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The VSP is a video processing engine that supports up-/down-scaling, alpha
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blending, color space conversion and various other image processing features.
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It can be found in the Renesas R-Car second generation SoCs.
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Required properties:
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- compatible: Must contain "renesas,vsp1"
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- compatible: Must contain one of the following values
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- "renesas,vsp1" for the R-Car Gen2 VSP1
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- "renesas,vsp2" for the R-Car Gen3 VSP2
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- reg: Base address and length of the registers block for the VSP1.
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- interrupts: VSP1 interrupt specifier.
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- clocks: A phandle + clock-specifier pair for the VSP1 functional clock.
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- reg: Base address and length of the registers block for the VSP.
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- interrupts: VSP interrupt specifier.
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- clocks: A phandle + clock-specifier pair for the VSP functional clock.
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- renesas,#rpf: Number of Read Pixel Formatter (RPF) modules in the VSP1.
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- renesas,#wpf: Number of Write Pixel Formatter (WPF) modules in the VSP1.
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- renesas,#rpf: Number of Read Pixel Formatter (RPF) modules in the VSP.
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- renesas,#wpf: Number of Write Pixel Formatter (WPF) modules in the VSP.
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Optional properties:
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- renesas,#uds: Number of Up Down Scaler (UDS) modules in the VSP1. Defaults
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- renesas,#uds: Number of Up Down Scaler (UDS) modules in the VSP. Defaults
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to 0 if not present.
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- renesas,has-lif: Boolean, indicates that the LCD Interface (LIF) module is
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available.
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@ -579,6 +579,7 @@ static int vsp1_probe(struct platform_device *pdev)
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struct vsp1_device *vsp1;
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struct resource *irq;
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struct resource *io;
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u32 version;
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int ret;
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vsp1 = devm_kzalloc(&pdev->dev, sizeof(*vsp1), GFP_KERNEL);
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@ -619,6 +620,29 @@ static int vsp1_probe(struct platform_device *pdev)
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return ret;
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}
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/* Configure device parameters based on the version register. */
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ret = clk_prepare_enable(vsp1->clock);
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if (ret < 0)
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return ret;
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version = vsp1_read(vsp1, VI6_IP_VERSION);
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clk_disable_unprepare(vsp1->clock);
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dev_dbg(&pdev->dev, "IP version 0x%08x\n", version);
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switch (version & VI6_IP_VERSION_MODEL_MASK) {
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case VI6_IP_VERSION_MODEL_VSPD_GEN3:
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vsp1->pdata.num_bru_inputs = 5;
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vsp1->pdata.uapi = false;
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break;
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case VI6_IP_VERSION_MODEL_VSPI_GEN3:
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case VI6_IP_VERSION_MODEL_VSPBD_GEN3:
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case VI6_IP_VERSION_MODEL_VSPBC_GEN3:
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vsp1->pdata.features &= ~VSP1_HAS_BRU;
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break;
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}
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/* Instanciate entities */
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ret = vsp1_create_entities(vsp1);
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if (ret < 0) {
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@ -642,6 +666,7 @@ static int vsp1_remove(struct platform_device *pdev)
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static const struct of_device_id vsp1_of_match[] = {
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{ .compatible = "renesas,vsp1" },
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{ .compatible = "renesas,vsp2" },
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{ },
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};
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@ -165,7 +165,8 @@ int vsp1_entity_link_setup(struct media_entity *entity,
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static const struct vsp1_route vsp1_routes[] = {
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{ VSP1_ENTITY_BRU, 0, VI6_DPR_BRU_ROUTE,
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{ VI6_DPR_NODE_BRU_IN(0), VI6_DPR_NODE_BRU_IN(1),
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VI6_DPR_NODE_BRU_IN(2), VI6_DPR_NODE_BRU_IN(3), } },
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VI6_DPR_NODE_BRU_IN(2), VI6_DPR_NODE_BRU_IN(3),
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VI6_DPR_NODE_BRU_IN(4) } },
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{ VSP1_ENTITY_HSI, 0, VI6_DPR_HSI_ROUTE, { VI6_DPR_NODE_HSI, } },
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{ VSP1_ENTITY_HST, 0, VI6_DPR_HST_ROUTE, { VI6_DPR_NODE_HST, } },
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{ VSP1_ENTITY_LIF, 0, 0, { VI6_DPR_NODE_LIF, } },
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@ -322,7 +322,7 @@
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#define VI6_DPR_NODE_SRU 16
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#define VI6_DPR_NODE_UDS(n) (17 + (n))
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#define VI6_DPR_NODE_LUT 22
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#define VI6_DPR_NODE_BRU_IN(n) (23 + (n))
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#define VI6_DPR_NODE_BRU_IN(n) (((n) <= 3) ? 23 + (n) : 49)
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#define VI6_DPR_NODE_BRU_OUT 27
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#define VI6_DPR_NODE_CLU 29
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#define VI6_DPR_NODE_HST 30
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@ -504,12 +504,12 @@
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#define VI6_BRU_VIRRPF_COL_BCB_MASK (0xff << 0)
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#define VI6_BRU_VIRRPF_COL_BCB_SHIFT 0
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#define VI6_BRU_CTRL(n) (0x2c10 + (n) * 8)
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#define VI6_BRU_CTRL(n) (0x2c10 + (n) * 8 + ((n) <= 3 ? 0 : 4))
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#define VI6_BRU_CTRL_RBC (1 << 31)
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#define VI6_BRU_CTRL_DSTSEL_BRUIN(n) ((n) << 20)
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#define VI6_BRU_CTRL_DSTSEL_BRUIN(n) (((n) <= 3 ? (n) : (n)+1) << 20)
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#define VI6_BRU_CTRL_DSTSEL_VRPF (4 << 20)
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#define VI6_BRU_CTRL_DSTSEL_MASK (7 << 20)
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#define VI6_BRU_CTRL_SRCSEL_BRUIN(n) ((n) << 16)
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#define VI6_BRU_CTRL_SRCSEL_BRUIN(n) (((n) <= 3 ? (n) : (n)+1) << 16)
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#define VI6_BRU_CTRL_SRCSEL_VRPF (4 << 16)
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#define VI6_BRU_CTRL_SRCSEL_MASK (7 << 16)
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#define VI6_BRU_CTRL_CROP(rop) ((rop) << 4)
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@ -517,7 +517,7 @@
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#define VI6_BRU_CTRL_AROP(rop) ((rop) << 0)
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#define VI6_BRU_CTRL_AROP_MASK (0xf << 0)
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#define VI6_BRU_BLD(n) (0x2c14 + (n) * 8)
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#define VI6_BRU_BLD(n) (0x2c14 + (n) * 8 + ((n) <= 3 ? 0 : 4))
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#define VI6_BRU_BLD_CBES (1 << 31)
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#define VI6_BRU_BLD_CCMDX_DST_A (0 << 28)
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#define VI6_BRU_BLD_CCMDX_255_DST_A (1 << 28)
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@ -551,7 +551,7 @@
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#define VI6_BRU_BLD_COEFY_SHIFT 0
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#define VI6_BRU_ROP 0x2c30
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#define VI6_BRU_ROP_DSTSEL_BRUIN(n) ((n) << 20)
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#define VI6_BRU_ROP_DSTSEL_BRUIN(n) (((n) <= 3 ? (n) : (n)+1) << 20)
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#define VI6_BRU_ROP_DSTSEL_VRPF (4 << 20)
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#define VI6_BRU_ROP_DSTSEL_MASK (7 << 20)
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#define VI6_BRU_ROP_CROP(rop) ((rop) << 4)
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@ -624,6 +624,24 @@
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#define VI6_SECURITY_CTRL0 0x3d00
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#define VI6_SECURITY_CTRL1 0x3d04
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/* -----------------------------------------------------------------------------
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* IP Version Registers
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*/
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#define VI6_IP_VERSION 0x3f00
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#define VI6_IP_VERSION_MODEL_MASK (0xff << 8)
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#define VI6_IP_VERSION_MODEL_VSPS_H2 (0x09 << 8)
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#define VI6_IP_VERSION_MODEL_VSPR_H2 (0x0a << 8)
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#define VI6_IP_VERSION_MODEL_VSPD_GEN2 (0x0b << 8)
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#define VI6_IP_VERSION_MODEL_VSPS_M2 (0x0c << 8)
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#define VI6_IP_VERSION_MODEL_VSPI_GEN3 (0x14 << 8)
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#define VI6_IP_VERSION_MODEL_VSPBD_GEN3 (0x15 << 8)
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#define VI6_IP_VERSION_MODEL_VSPBC_GEN3 (0x16 << 8)
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#define VI6_IP_VERSION_MODEL_VSPD_GEN3 (0x17 << 8)
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#define VI6_IP_VERSION_SOC_MASK (0xff << 0)
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#define VI6_IP_VERSION_SOC_H (0x01 << 0)
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#define VI6_IP_VERSION_SOC_M (0x02 << 0)
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/* -----------------------------------------------------------------------------
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* RPF CLUT Registers
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*/
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