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riscv: dts: fu740: fix cache-controller interrupts

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The order of interrupt numbers is incorrect.

The order for FU740 is: DirError, DataError, DataFail, DirFail

From SiFive FU740-C000 Manual:
19 - L2 Cache DirError
20 - L2 Cache DirFail
21 - L2 Cache DataError
22 - L2 Cache DataFail

Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
This commit is contained in:
David Abdurachmanov 2021-06-12 17:43:57 -07:00 committed by Palmer Dabbelt
parent 3a02764c37
commit 7ede12b01b
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1 changed files with 1 additions and 1 deletions
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arch/riscv/boot/dts/sifive/fu740-c000.dtsi
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@ -273,7 +273,7 @@
cache-size = <2097152>;
cache-unified;
interrupt-parent = <&plic0>;
interrupts = <19 20 21 22>;
interrupts = <19 21 22 20>;
reg = <0x0 0x2010000 0x0 0x1000>;
};
gpio: gpio@10060000 {