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riscv: dts: microchip: add qspi compatible fallback

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The "hard" QSPI peripheral on PolarFire SoC is derived from version 2
of the FPGA IP core. The original binding had no fallback etc, so this
device tree is valid as is. There was also no functional driver for the
QSPI IP, so no device with a devicetree from a previous mainline
release will regress.

Link: https://lore.kernel.org/linux-spi/7c9f0d96-2882-964a-cd1f-916ddb3f0410@linaro.org/
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Conor Dooley 2022-08-10 09:59:15 +01:00
parent 69dac8e431
commit 7eac0081a8
1 changed files with 1 additions and 1 deletions
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2
arch/riscv/boot/dts/microchip/mpfs.dtsi
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@ -330,7 +330,7 @@
};
qspi: spi@21000000 {
compatible = "microchip,mpfs-qspi";
compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x21000000 0x0 0x1000>;