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net: enetc: use dedicated TX rings for XDP
It is possible for one CPU to perform TX hashing (see netdev_pick_tx) between the 8 ENETC TX rings, and the TX hashing to select TX queue 1. At the same time, it is possible for the other CPU to already use TX ring 1 for XDP (either XDP_TX or XDP_REDIRECT). Since there is no mutual exclusion between XDP and the network stack, we run into an issue because the ENETC TX procedure is not reentrant. The obvious approach would be to just make XDP take the lock of the network stack's TX queue corresponding to the ring it's about to enqueue in. For XDP_REDIRECT, this is quite straightforward, a lock at the beginning and end of enetc_xdp_xmit() should do the trick. But for XDP_TX, it's a bit more complicated. For one, we do TX batching all by ourselves for frames with the XDP_TX verdict. This is something we would like to keep the way it is, for performance reasons. But batching means that the network stack's lock should be kept from the first enqueued XDP_TX frame and until we ring the doorbell. That is mostly fine, except for cases when in the same NAPI loop we have mixed XDP_TX and XDP_REDIRECT frames. So if enetc_xdp_xmit() gets called while we are holding the lock from the RX NAPI, then bam, deadlock. The naive answer could be 'just flush the XDP_TX frames first, then release the network stack's TX queue lock, then call xdp_do_flush_map()'. But even xdp_do_redirect() is capable of flushing the batched XDP_REDIRECT frames, so unless we unlock/relock the TX queue around xdp_do_redirect(), there simply isn't any clean way to protect XDP_TX from concurrent network stack .ndo_start_xmit() on another CPU. So we need to take a different approach, and that is to reserve two rings for the sole use of XDP. We leave TX rings 0..ndev->real_num_tx_queues-1 to be handled by the network stack, and we pick them from the end of the priv->tx_ring array. We make an effort to keep the mapping done by enetc_alloc_msix() which decides which CPU handles the TX completions of which TX ring in its NAPI poll. So the XDP TX ring of CPU 0 is handled by TX ring 6, and the XDP TX ring of CPU 1 is handled by TX ring 7. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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ee3e875f10
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@ -9,6 +9,26 @@
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#include <linux/ptp_classify.h>
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#include <net/pkt_sched.h>
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static int enetc_num_stack_tx_queues(struct enetc_ndev_priv *priv)
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{
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int num_tx_rings = priv->num_tx_rings;
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int i;
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for (i = 0; i < priv->num_rx_rings; i++)
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if (priv->rx_ring[i]->xdp.prog)
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return num_tx_rings - num_possible_cpus();
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return num_tx_rings;
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}
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static struct enetc_bdr *enetc_rx_ring_from_xdp_tx_ring(struct enetc_ndev_priv *priv,
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struct enetc_bdr *tx_ring)
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{
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int index = &priv->tx_ring[tx_ring->index] - priv->xdp_tx_ring;
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return priv->rx_ring[index];
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}
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static struct sk_buff *enetc_tx_swbd_get_skb(struct enetc_tx_swbd *tx_swbd)
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{
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if (tx_swbd->is_xdp_tx || tx_swbd->is_xdp_redirect)
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@ -468,7 +488,6 @@ static void enetc_recycle_xdp_tx_buff(struct enetc_bdr *tx_ring,
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struct enetc_tx_swbd *tx_swbd)
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{
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struct enetc_ndev_priv *priv = netdev_priv(tx_ring->ndev);
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struct enetc_bdr *rx_ring = priv->rx_ring[tx_ring->index];
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struct enetc_rx_swbd rx_swbd = {
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.dma = tx_swbd->dma,
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.page = tx_swbd->page,
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@ -476,6 +495,9 @@ static void enetc_recycle_xdp_tx_buff(struct enetc_bdr *tx_ring,
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.dir = tx_swbd->dir,
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.len = tx_swbd->len,
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};
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struct enetc_bdr *rx_ring;
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rx_ring = enetc_rx_ring_from_xdp_tx_ring(priv, tx_ring);
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if (likely(enetc_swbd_unused(rx_ring))) {
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enetc_reuse_page(rx_ring, &rx_swbd);
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@ -1059,7 +1081,7 @@ int enetc_xdp_xmit(struct net_device *ndev, int num_frames,
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int xdp_tx_bd_cnt, i, k;
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int xdp_tx_frm_cnt = 0;
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tx_ring = priv->tx_ring[smp_processor_id()];
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tx_ring = priv->xdp_tx_ring[smp_processor_id()];
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prefetchw(ENETC_TXBD(*tx_ring, tx_ring->next_to_use));
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@ -1221,8 +1243,8 @@ static int enetc_clean_rx_ring_xdp(struct enetc_bdr *rx_ring,
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int xdp_tx_bd_cnt, xdp_tx_frm_cnt = 0, xdp_redirect_frm_cnt = 0;
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struct enetc_tx_swbd xdp_tx_arr[ENETC_MAX_SKB_FRAGS] = {0};
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struct enetc_ndev_priv *priv = netdev_priv(rx_ring->ndev);
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struct enetc_bdr *tx_ring = priv->tx_ring[rx_ring->index];
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int rx_frm_cnt = 0, rx_byte_cnt = 0;
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struct enetc_bdr *tx_ring;
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int cleaned_cnt, i;
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u32 xdp_act;
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@ -1280,6 +1302,7 @@ static int enetc_clean_rx_ring_xdp(struct enetc_bdr *rx_ring,
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napi_gro_receive(napi, skb);
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break;
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case XDP_TX:
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tx_ring = priv->xdp_tx_ring[rx_ring->index];
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xdp_tx_bd_cnt = enetc_rx_swbd_to_xdp_tx_swbd(xdp_tx_arr,
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rx_ring,
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orig_i, i);
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@ -2022,6 +2045,7 @@ void enetc_start(struct net_device *ndev)
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int enetc_open(struct net_device *ndev)
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{
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struct enetc_ndev_priv *priv = netdev_priv(ndev);
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int num_stack_tx_queues;
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int err;
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err = enetc_setup_irqs(priv);
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@ -2040,7 +2064,9 @@ int enetc_open(struct net_device *ndev)
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if (err)
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goto err_alloc_rx;
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err = netif_set_real_num_tx_queues(ndev, priv->num_tx_rings);
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num_stack_tx_queues = enetc_num_stack_tx_queues(priv);
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err = netif_set_real_num_tx_queues(ndev, num_stack_tx_queues);
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if (err)
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goto err_set_queues;
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@ -2113,15 +2139,17 @@ static int enetc_setup_tc_mqprio(struct net_device *ndev, void *type_data)
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struct enetc_ndev_priv *priv = netdev_priv(ndev);
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struct tc_mqprio_qopt *mqprio = type_data;
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struct enetc_bdr *tx_ring;
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int num_stack_tx_queues;
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u8 num_tc;
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int i;
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num_stack_tx_queues = enetc_num_stack_tx_queues(priv);
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mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
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num_tc = mqprio->num_tc;
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if (!num_tc) {
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netdev_reset_tc(ndev);
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netif_set_real_num_tx_queues(ndev, priv->num_tx_rings);
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netif_set_real_num_tx_queues(ndev, num_stack_tx_queues);
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/* Reset all ring priorities to 0 */
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for (i = 0; i < priv->num_tx_rings; i++) {
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@ -2133,7 +2161,7 @@ static int enetc_setup_tc_mqprio(struct net_device *ndev, void *type_data)
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}
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/* Check if we have enough BD rings available to accommodate all TCs */
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if (num_tc > priv->num_tx_rings) {
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if (num_tc > num_stack_tx_queues) {
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netdev_err(ndev, "Max %d traffic classes supported\n",
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priv->num_tx_rings);
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return -EINVAL;
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@ -2421,8 +2449,9 @@ int enetc_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
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int enetc_alloc_msix(struct enetc_ndev_priv *priv)
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{
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struct pci_dev *pdev = priv->si->pdev;
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int v_tx_rings;
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int first_xdp_tx_ring;
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int i, n, err, nvec;
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int v_tx_rings;
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nvec = ENETC_BDR_INT_BASE_IDX + priv->bdr_int_num;
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/* allocate MSIX for both messaging and Rx/Tx interrupts */
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@ -2497,6 +2526,9 @@ int enetc_alloc_msix(struct enetc_ndev_priv *priv)
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}
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}
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first_xdp_tx_ring = priv->num_tx_rings - num_possible_cpus();
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priv->xdp_tx_ring = &priv->tx_ring[first_xdp_tx_ring];
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return 0;
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fail:
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@ -317,6 +317,7 @@ struct enetc_ndev_priv {
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u32 speed; /* store speed for compare update pspeed */
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struct enetc_bdr **xdp_tx_ring;
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struct enetc_bdr *tx_ring[16];
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struct enetc_bdr *rx_ring[16];
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