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Merge branch 'pci/pm'
- Reduce wait time for secondary bus to be ready to speed up resume (Mika Westerberg) - Avoid putting EloPOS E2/S2/H2 (as well as Elo i2) PCIe Ports in D3cold (Ondrej Zary) - Call _REG when transitioning D-states so AML that uses the PCI config space OpRegion works, which fixes some ASMedia GPIO controllers (Mario Limonciello) * pci/pm: PCI/ACPI: Call _REG when transitioning D-states PCI/ACPI: Validate acpi_pci_set_power_state() parameter PCI/PM: Avoid putting EloPOS E2/S2/H2 PCIe Ports in D3cold PCI/PM: Shorten pci_bridge_wait_for_secondary_bus() wait time for slow links
This commit is contained in:
Bjorn Helgaas
commit
7e229f0e05
@ -1043,6 +1043,16 @@ bool acpi_pci_bridge_d3(struct pci_dev *dev)
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return false;
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}
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static void acpi_pci_config_space_access(struct pci_dev *dev, bool enable)
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{
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int val = enable ? ACPI_REG_CONNECT : ACPI_REG_DISCONNECT;
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int ret = acpi_evaluate_reg(ACPI_HANDLE(&dev->dev),
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ACPI_ADR_SPACE_PCI_CONFIG, val);
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if (ret)
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pci_dbg(dev, "ACPI _REG %s evaluation failed (%d)\n",
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enable ? "connect" : "disconnect", ret);
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}
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int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
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{
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struct acpi_device *adev = ACPI_COMPANION(&dev->dev);
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@ -1053,32 +1063,49 @@ int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
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[PCI_D3hot] = ACPI_STATE_D3_HOT,
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[PCI_D3cold] = ACPI_STATE_D3_COLD,
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};
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int error = -EINVAL;
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int error;
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/* If the ACPI device has _EJ0, ignore the device */
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if (!adev || acpi_has_method(adev->handle, "_EJ0"))
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return -ENODEV;
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switch (state) {
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case PCI_D3cold:
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if (dev_pm_qos_flags(&dev->dev, PM_QOS_FLAG_NO_POWER_OFF) ==
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PM_QOS_FLAGS_ALL) {
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error = -EBUSY;
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break;
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}
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fallthrough;
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case PCI_D0:
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case PCI_D1:
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case PCI_D2:
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case PCI_D3hot:
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error = acpi_device_set_power(adev, state_conv[state]);
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case PCI_D3cold:
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break;
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default:
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return -EINVAL;
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}
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if (!error)
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pci_dbg(dev, "power state changed by ACPI to %s\n",
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acpi_power_state_string(adev->power.state));
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if (state == PCI_D3cold) {
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if (dev_pm_qos_flags(&dev->dev, PM_QOS_FLAG_NO_POWER_OFF) ==
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PM_QOS_FLAGS_ALL)
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return -EBUSY;
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return error;
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/* Notify AML lack of PCI config space availability */
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acpi_pci_config_space_access(dev, false);
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}
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error = acpi_device_set_power(adev, state_conv[state]);
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if (error)
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return error;
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pci_dbg(dev, "power state changed by ACPI to %s\n",
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acpi_power_state_string(adev->power.state));
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/*
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* Notify AML of PCI config space availability. Config space is
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* accessible in all states except D3cold; the only transitions
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* that change availability are transitions to D3cold and from
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* D3cold to D0.
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*/
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if (state == PCI_D0)
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acpi_pci_config_space_access(dev, true);
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return 0;
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}
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pci_power_t acpi_pci_get_power_state(struct pci_dev *dev)
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@ -64,6 +64,13 @@ struct pci_pme_device {
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#define PME_TIMEOUT 1000 /* How long between PME checks */
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/*
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* Following exit from Conventional Reset, devices must be ready within 1 sec
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* (PCIe r6.0 sec 6.6.1). A D3cold to D0 transition implies a Conventional
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* Reset (PCIe r6.0 sec 5.8).
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*/
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#define PCI_RESET_WAIT 1000 /* msec */
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/*
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* Devices may extend the 1 sec period through Request Retry Status
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* completions (PCIe r6.0 sec 2.3.1). The spec does not provide an upper
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@ -2968,13 +2975,13 @@ static const struct dmi_system_id bridge_d3_blacklist[] = {
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{
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/*
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* Downstream device is not accessible after putting a root port
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* into D3cold and back into D0 on Elo i2.
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* into D3cold and back into D0 on Elo Continental Z2 board
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*/
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.ident = "Elo i2",
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.ident = "Elo Continental Z2",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Elo Touch Solutions"),
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DMI_MATCH(DMI_PRODUCT_NAME, "Elo i2"),
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DMI_MATCH(DMI_PRODUCT_VERSION, "RevB"),
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DMI_MATCH(DMI_BOARD_VENDOR, "Elo Touch Solutions"),
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DMI_MATCH(DMI_BOARD_NAME, "Geminilake"),
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DMI_MATCH(DMI_BOARD_VERSION, "Continental Z2"),
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},
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},
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#endif
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@ -5102,11 +5109,9 @@ int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type)
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*
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* However, 100 ms is the minimum and the PCIe spec says the
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* software must allow at least 1s before it can determine that the
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* device that did not respond is a broken device. There is
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* evidence that 100 ms is not always enough, for example certain
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* Titan Ridge xHCI controller does not always respond to
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* configuration requests if we only wait for 100 ms (see
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* https://bugzilla.kernel.org/show_bug.cgi?id=203885).
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* device that did not respond is a broken device. Also device can
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* take longer than that to respond if it indicates so through Request
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* Retry Status completions.
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*
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* Therefore we wait for 100 ms and check for the device presence
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* until the timeout expires.
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@ -5115,16 +5120,36 @@ int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type)
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return 0;
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if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) {
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u16 status;
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pci_dbg(dev, "waiting %d ms for downstream link\n", delay);
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msleep(delay);
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} else {
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pci_dbg(dev, "waiting %d ms for downstream link, after activation\n",
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delay);
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if (!pcie_wait_for_link_delay(dev, true, delay)) {
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/* Did not train, no need to wait any further */
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pci_info(dev, "Data Link Layer Link Active not set in 1000 msec\n");
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if (!pci_dev_wait(child, reset_type, PCI_RESET_WAIT - delay))
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return 0;
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/*
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* If the port supports active link reporting we now check
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* whether the link is active and if not bail out early with
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* the assumption that the device is not present anymore.
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*/
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if (!dev->link_active_reporting)
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return -ENOTTY;
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}
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pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &status);
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if (!(status & PCI_EXP_LNKSTA_DLLLA))
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return -ENOTTY;
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return pci_dev_wait(child, reset_type,
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PCIE_RESET_READY_POLL_MS - PCI_RESET_WAIT);
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}
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pci_dbg(dev, "waiting %d ms for downstream link, after activation\n",
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delay);
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if (!pcie_wait_for_link_delay(dev, true, delay)) {
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/* Did not train, no need to wait any further */
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pci_info(dev, "Data Link Layer Link Active not set in 1000 msec\n");
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return -ENOTTY;
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}
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return pci_dev_wait(child, reset_type,
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@ -66,13 +66,6 @@ struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
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#define PCI_PM_D3HOT_WAIT 10 /* msec */
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#define PCI_PM_D3COLD_WAIT 100 /* msec */
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/*
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* Following exit from Conventional Reset, devices must be ready within 1 sec
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* (PCIe r6.0 sec 6.6.1). A D3cold to D0 transition implies a Conventional
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* Reset (PCIe r6.0 sec 5.8).
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*/
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#define PCI_RESET_WAIT 1000 /* msec */
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void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
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void pci_refresh_power_state(struct pci_dev *dev);
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int pci_power_up(struct pci_dev *dev);
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