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perf vendor events: Move JSON/events to appropriate files for power10 platform
Move some of the power10 JSON/events to appropriate files.
Fixes: 32daa5d789 ("perf vendor events: Initial JSON/events list for power10 platform")
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
Cc: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Cc: Disha Goel <disgoel@linux.ibm.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Kajol Jain <kjain@linux.ibm.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: linuxppc-dev@lists.ozlabs.org
Link: https://lore.kernel.org/r/20230814112803.1508296-4-kjain@linux.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Kajol Jain
Arnaldo Carvalho de Melo
parent
4836b9a85e
commit
7d473f475b
@ -1,54 +1,9 @@
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[
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{
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"EventCode": "0x1003C",
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"EventName": "PM_EXEC_STALL_DMISS_L2L3",
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"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from either the local L2 or local L3."
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},
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{
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"EventCode": "0x1E054",
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"EventName": "PM_EXEC_STALL_DMISS_L21_L31",
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"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from another core's L2 or L3 on the same chip."
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},
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{
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"EventCode": "0x34054",
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"EventName": "PM_EXEC_STALL_DMISS_L2L3_NOCONFLICT",
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"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local L2 or local L3, without a dispatch conflict."
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},
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{
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"EventCode": "0x34056",
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"EventName": "PM_EXEC_STALL_LOAD_FINISH",
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"BriefDescription": "Cycles in which the oldest instruction in the pipeline was finishing a load after its data was reloaded from a data source beyond the local L1; cycles in which the LSU was processing an L1-hit; cycles in which the next-to-finish (NTF) instruction merged with another load in the LMQ; cycles in which the NTF instruction is waiting for a data reload for a load miss, but the data comes back with a non-NTF instruction."
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},
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{
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"EventCode": "0x3006C",
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"EventName": "PM_RUN_CYC_SMT2_MODE",
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"BriefDescription": "Cycles when this thread's run latch is set and the core is in SMT2 mode."
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},
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{
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"EventCode": "0x300F4",
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"EventName": "PM_RUN_INST_CMPL_CONC",
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"BriefDescription": "PowerPC instruction completed by this thread when all threads in the core had the run-latch set."
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},
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{
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"EventCode": "0x4C016",
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"EventName": "PM_EXEC_STALL_DMISS_L2L3_CONFLICT",
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"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local L2 or local L3, with a dispatch conflict."
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},
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{
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"EventCode": "0x4D014",
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"EventName": "PM_EXEC_STALL_LOAD",
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"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a load instruction executing in the Load Store Unit."
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},
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{
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"EventCode": "0x4D016",
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"EventName": "PM_EXEC_STALL_PTESYNC",
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"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a PTESYNC instruction executing in the Load Store Unit."
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},
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{
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"EventCode": "0x401EA",
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"EventName": "PM_THRESH_EXC_128",
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"BriefDescription": "Threshold counter exceeded a value of 128."
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},
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{
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"EventCode": "0x400F6",
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"EventName": "PM_BR_MPRED_CMPL",
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@ -0,0 +1,67 @@
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[
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{
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"EventCode": "0x100F4",
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"EventName": "PM_FLOP_CMPL",
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"BriefDescription": "Floating Point Operations Completed. Includes any type. It counts once for each 1, 2, 4 or 8 flop instruction. Use PM_1|2|4|8_FLOP_CMPL events to count flops."
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},
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{
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"EventCode": "0x45050",
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"EventName": "PM_1FLOP_CMPL",
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"BriefDescription": "One floating point instruction completed (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg)."
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},
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{
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"EventCode": "0x45052",
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"EventName": "PM_4FLOP_CMPL",
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"BriefDescription": "Four floating point instruction completed (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg)."
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},
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{
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"EventCode": "0x45054",
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"EventName": "PM_FMA_CMPL",
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"BriefDescription": "Two floating point instruction completed (FMA class of instructions: fmadd, fnmadd, fmsub, fnmsub). Scalar instructions only."
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},
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{
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"EventCode": "0x45056",
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"EventName": "PM_SCALAR_FLOP_CMPL",
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"BriefDescription": "Scalar floating point instruction completed."
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},
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{
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"EventCode": "0x4505A",
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"EventName": "PM_SP_FLOP_CMPL",
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"BriefDescription": "Single Precision floating point instruction completed."
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},
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{
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"EventCode": "0x4505C",
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"EventName": "PM_MATH_FLOP_CMPL",
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"BriefDescription": "Math floating point instruction completed."
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},
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{
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"EventCode": "0x4D052",
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"EventName": "PM_2FLOP_CMPL",
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"BriefDescription": "Double Precision vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg completed."
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},
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{
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"EventCode": "0x4D054",
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"EventName": "PM_8FLOP_CMPL",
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"BriefDescription": "Four Double Precision vector instruction completed."
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},
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{
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"EventCode": "0x4D056",
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"EventName": "PM_NON_FMA_FLOP_CMPL",
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"BriefDescription": "Non FMA instruction completed."
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},
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{
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"EventCode": "0x4D058",
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"EventName": "PM_VECTOR_FLOP_CMPL",
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"BriefDescription": "Vector floating point instruction completed."
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},
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{
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"EventCode": "0x4D05A",
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"EventName": "PM_NON_MATH_FLOP_CMPL",
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"BriefDescription": "Non Math instruction completed."
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},
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{
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"EventCode": "0x4D05C",
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"EventName": "PM_DPP_FLOP_CMPL",
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"BriefDescription": "Double-Precision or Quad-Precision instruction completed."
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}
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]
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@ -1,64 +1,9 @@
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[
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{
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"EventCode": "0x10004",
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"EventName": "PM_EXEC_STALL_TRANSLATION",
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"BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered a TLB miss or ERAT miss and waited for it to resolve."
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},
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{
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"EventCode": "0x10006",
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"EventName": "PM_DISP_STALL_HELD_OTHER_CYC",
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"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch for any other reason."
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},
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{
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"EventCode": "0x10010",
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"EventName": "PM_PMC4_OVERFLOW",
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"BriefDescription": "The event selected for PMC4 caused the event counter to overflow."
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},
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{
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"EventCode": "0x10020",
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"EventName": "PM_PMC4_REWIND",
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"BriefDescription": "The speculative event selected for PMC4 rewinds and the counter for PMC4 is not charged."
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},
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{
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"EventCode": "0x10038",
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"EventName": "PM_DISP_STALL_TRANSLATION",
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"BriefDescription": "Cycles when dispatch was stalled for this thread because the MMU was handling a translation miss."
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},
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{
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"EventCode": "0x1003A",
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"EventName": "PM_DISP_STALL_BR_MPRED_IC_L2",
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"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L2 after suffering a branch mispredict."
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},
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{
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"EventCode": "0x1D05E",
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"EventName": "PM_DISP_STALL_HELD_HALT_CYC",
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"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch because of power management."
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},
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{
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"EventCode": "0x1E050",
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"EventName": "PM_DISP_STALL_HELD_STF_MAPPER_CYC",
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"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch because the STF mapper/SRB was full. Includes GPR (count, link, tar), VSR, VMR, FPR."
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},
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{
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"EventCode": "0x1F054",
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"EventName": "PM_DTLB_HIT",
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"BriefDescription": "The PTE required by the instruction was resident in the TLB (data TLB access). When MMCR1[16]=0 this event counts only demand hits. When MMCR1[16]=1 this event includes demand and prefetch. Applies to both HPT and RPT."
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},
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{
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"EventCode": "0x10064",
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"EventName": "PM_DISP_STALL_IC_L2",
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"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L2."
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},
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{
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"EventCode": "0x101E8",
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"EventName": "PM_THRESH_EXC_256",
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"BriefDescription": "Threshold counter exceeded a count of 256."
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},
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{
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"EventCode": "0x101EC",
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"EventName": "PM_THRESH_MET",
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"BriefDescription": "Threshold exceeded."
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},
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{
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"EventCode": "0x100F2",
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"EventName": "PM_1PLUS_PPC_CMPL",
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@ -69,56 +14,6 @@
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"EventName": "PM_IERAT_MISS",
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"BriefDescription": "IERAT Reloaded to satisfy an IERAT miss. All page sizes are counted by this event. This event only counts instruction demand access."
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},
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{
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"EventCode": "0x100F8",
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"EventName": "PM_DISP_STALL_CYC",
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"BriefDescription": "Cycles the ICT has no itags assigned to this thread (no instructions were dispatched during these cycles)."
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},
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{
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"EventCode": "0x20006",
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"EventName": "PM_DISP_STALL_HELD_ISSQ_FULL_CYC",
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"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch due to Issue queue full. Includes issue queue and branch queue."
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},
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{
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"EventCode": "0x20114",
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"EventName": "PM_MRK_L2_RC_DISP",
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"BriefDescription": "Marked instruction RC dispatched in L2."
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},
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{
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"EventCode": "0x2C010",
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"EventName": "PM_EXEC_STALL_LSU",
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"BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the Load Store Unit. This does not include simple fixed point instructions."
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},
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{
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"EventCode": "0x2C016",
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"EventName": "PM_DISP_STALL_IERAT_ONLY_MISS",
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"BriefDescription": "Cycles when dispatch was stalled while waiting to resolve an instruction ERAT miss."
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},
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{
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"EventCode": "0x2C01E",
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"EventName": "PM_DISP_STALL_BR_MPRED_IC_L3",
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"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L3 after suffering a branch mispredict."
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},
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{
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"EventCode": "0x2D01A",
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"EventName": "PM_DISP_STALL_IC_MISS",
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"BriefDescription": "Cycles when dispatch was stalled for this thread due to an instruction cache miss."
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},
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{
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"EventCode": "0x2E018",
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"EventName": "PM_DISP_STALL_FETCH",
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"BriefDescription": "Cycles when dispatch was stalled for this thread because Fetch was being held."
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},
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{
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"EventCode": "0x2E01A",
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"EventName": "PM_DISP_STALL_HELD_XVFC_MAPPER_CYC",
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"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch because the XVFC mapper/SRB was full."
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},
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{
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"EventCode": "0x2C142",
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"EventName": "PM_MRK_XFER_FROM_SRC_PMC2",
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"BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[15:27]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
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},
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{
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"EventCode": "0x24050",
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"EventName": "PM_IOPS_DISP",
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@ -134,11 +29,6 @@
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"EventName": "PM_BR_TAKEN_CMPL",
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"BriefDescription": "Branch Taken instruction completed."
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},
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{
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"EventCode": "0x30004",
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"EventName": "PM_DISP_STALL_FLUSH",
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"BriefDescription": "Cycles when dispatch was stalled because of a flush that happened to an instruction(s) that was not yet next-to-complete (NTC). PM_EXEC_STALL_NTC_FLUSH only includes instructions that were flushed after becoming NTC."
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},
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{
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"EventCode": "0x3000A",
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"EventName": "PM_DISP_STALL_ITLB_MISS",
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@ -149,56 +39,16 @@
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"EventName": "PM_FLUSH_COMPLETION",
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"BriefDescription": "The instruction that was next to complete (oldest in the pipeline) did not complete because it suffered a flush."
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},
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{
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"EventCode": "0x30014",
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"EventName": "PM_EXEC_STALL_STORE",
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"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a store instruction executing in the Load Store Unit."
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},
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{
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"EventCode": "0x30018",
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"EventName": "PM_DISP_STALL_HELD_SCOREBOARD_CYC",
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"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch while waiting on the Scoreboard. This event combines VSCR and FPSCR together."
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},
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{
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"EventCode": "0x30026",
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"EventName": "PM_EXEC_STALL_STORE_MISS",
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"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a store whose cache line was not resident in the L1 and was waiting for allocation of the missing line into the L1."
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},
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{
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"EventCode": "0x3012A",
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"EventName": "PM_MRK_L2_RC_DONE",
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"BriefDescription": "L2 RC machine completed the transaction for the marked instruction."
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},
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{
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"EventCode": "0x3F046",
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"EventName": "PM_ITLB_HIT_1G",
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"BriefDescription": "Instruction TLB hit (IERAT reload) page size 1G, which implies Radix Page Table translation is in use. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches."
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},
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{
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"EventCode": "0x34058",
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"EventName": "PM_DISP_STALL_BR_MPRED_ICMISS",
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"BriefDescription": "Cycles when dispatch was stalled after a mispredicted branch resulted in an instruction cache miss."
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},
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{
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"EventCode": "0x3D05C",
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"EventName": "PM_DISP_STALL_HELD_RENAME_CYC",
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"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch because the mapper/SRB was full. Includes GPR (count, link, tar), VSR, VMR, FPR and XVFC."
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},
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{
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"EventCode": "0x3E052",
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"EventName": "PM_DISP_STALL_IC_L3",
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"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L3."
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},
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{
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"EventCode": "0x3E054",
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"EventName": "PM_LD_MISS_L1",
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"BriefDescription": "Load missed L1, counted at finish time. LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load."
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},
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{
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"EventCode": "0x301EA",
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"EventName": "PM_THRESH_EXC_1024",
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"BriefDescription": "Threshold counter exceeded a value of 1024."
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},
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{
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"EventCode": "0x300FA",
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"EventName": "PM_INST_FROM_L3MISS",
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@ -209,36 +59,6 @@
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"EventName": "PM_ISSUE_KILL",
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"BriefDescription": "Cycles in which an instruction or group of instructions were cancelled after being issued. This event increments once per occurrence, regardless of how many instructions are included in the issue group."
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},
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{
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"EventCode": "0x40116",
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"EventName": "PM_MRK_LARX_FIN",
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"BriefDescription": "Marked load and reserve instruction (LARX) finished. LARX and STCX are instructions used to acquire a lock."
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},
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{
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"EventCode": "0x4C010",
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"EventName": "PM_DISP_STALL_BR_MPRED_IC_L3MISS",
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"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from sources beyond the local L3 after suffering a mispredicted branch."
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},
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{
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"EventCode": "0x4D01E",
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"EventName": "PM_DISP_STALL_BR_MPRED",
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"BriefDescription": "Cycles when dispatch was stalled for this thread due to a mispredicted branch."
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},
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{
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"EventCode": "0x4E010",
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"EventName": "PM_DISP_STALL_IC_L3MISS",
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"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from any source beyond the local L3."
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},
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{
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"EventCode": "0x4E01A",
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"EventName": "PM_DISP_STALL_HELD_CYC",
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"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch for any reason."
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},
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{
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"EventCode": "0x4003C",
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"EventName": "PM_DISP_STALL_HELD_SYNC_CYC",
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"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch because of a synchronizing instruction that requires the ICT to be empty before dispatch."
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},
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{
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"EventCode": "0x44056",
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"EventName": "PM_VECTOR_ST_CMPL",
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@ -1,14 +1,29 @@
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[
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{
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"EventCode": "0x1002C",
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"EventName": "PM_LD_PREFETCH_CACHE_LINE_MISS",
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"BriefDescription": "The L1 cache was reloaded with a line that fulfills a prefetch request."
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},
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{
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"EventCode": "0x10132",
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"EventName": "PM_MRK_INST_ISSUED",
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"BriefDescription": "Marked instruction issued. Note that stores always get issued twice, the address gets issued to the LSU and the data gets issued to the VSU. Also, issues can sometimes get killed/cancelled and cause multiple sequential issues for the same instruction."
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},
|
||||
{
|
||||
"EventCode": "0x10134",
|
||||
"EventName": "PM_MRK_ST_DONE_L2",
|
||||
"BriefDescription": "Marked store completed in L2."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x1C142",
|
||||
"EventName": "PM_MRK_XFER_FROM_SRC_PMC1",
|
||||
"BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x1C144",
|
||||
"EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC1",
|
||||
"BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[0:12]."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x1F150",
|
||||
"EventName": "PM_MRK_ST_L2_CYC",
|
||||
"BriefDescription": "Cycles from L2 RC dispatch to L2 RC completion."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x101E0",
|
||||
"EventName": "PM_MRK_INST_DISP",
|
||||
@ -20,9 +35,39 @@
|
||||
"BriefDescription": "Marked Branch Taken instruction completed."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2C01C",
|
||||
"EventName": "PM_EXEC_STALL_DMISS_OFF_CHIP",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a remote chip."
|
||||
"EventCode": "0x101E4",
|
||||
"EventName": "PM_MRK_L1_ICACHE_MISS",
|
||||
"BriefDescription": "Marked instruction suffered an instruction cache miss."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x101EA",
|
||||
"EventName": "PM_MRK_L1_RELOAD_VALID",
|
||||
"BriefDescription": "Marked demand reload."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x20114",
|
||||
"EventName": "PM_MRK_L2_RC_DISP",
|
||||
"BriefDescription": "Marked instruction RC dispatched in L2."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2011C",
|
||||
"EventName": "PM_MRK_NTF_CYC",
|
||||
"BriefDescription": "Cycles in which the marked instruction is the oldest in the pipeline (next-to-finish or next-to-complete)."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x20130",
|
||||
"EventName": "PM_MRK_INST_DECODED",
|
||||
"BriefDescription": "An instruction was marked at decode time. Random Instruction Sampling (RIS) only."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x20132",
|
||||
"EventName": "PM_MRK_DFU_ISSUE",
|
||||
"BriefDescription": "The marked instruction was a decimal floating point operation issued to the VSU. Measured at issue time."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x20134",
|
||||
"EventName": "PM_MRK_FXU_ISSUE",
|
||||
"BriefDescription": "The marked instruction was a fixed point operation issued to the VSU. Measured at issue time."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x20138",
|
||||
@ -34,6 +79,16 @@
|
||||
"EventName": "PM_MRK_BRU_FIN",
|
||||
"BriefDescription": "Marked Branch instruction finished."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2013C",
|
||||
"EventName": "PM_MRK_FX_LSU_FIN",
|
||||
"BriefDescription": "The marked instruction was simple fixed point that was issued to the store unit. Measured at finish time."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2C142",
|
||||
"EventName": "PM_MRK_XFER_FROM_SRC_PMC2",
|
||||
"BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[15:27]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2C144",
|
||||
"EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC2",
|
||||
@ -55,15 +110,50 @@
|
||||
"BriefDescription": "A marked branch completed. All branches are included."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x200FD",
|
||||
"EventName": "PM_L1_ICACHE_MISS",
|
||||
"BriefDescription": "Demand instruction cache miss."
|
||||
"EventCode": "0x2D154",
|
||||
"EventName": "PM_MRK_DERAT_MISS_64K",
|
||||
"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x201E0",
|
||||
"EventName": "PM_MRK_DATA_FROM_MEMORY",
|
||||
"BriefDescription": "The processor's data cache was reloaded from local, remote, or distant memory due to a demand miss for a marked load."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x201E2",
|
||||
"EventName": "PM_MRK_LD_MISS_L1",
|
||||
"BriefDescription": "Marked demand data load miss counted at finish time."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x201E4",
|
||||
"EventName": "PM_MRK_DATA_FROM_L3MISS",
|
||||
"BriefDescription": "The processor's data cache was reloaded from a source other than the local core's L1, L2, or L3 due to a demand miss for a marked load."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x3012A",
|
||||
"EventName": "PM_MRK_L2_RC_DONE",
|
||||
"BriefDescription": "L2 RC machine completed the transaction for the marked instruction."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x30132",
|
||||
"EventName": "PM_MRK_VSU_FIN",
|
||||
"BriefDescription": "VSU marked instruction finished. Excludes simple FX instructions issued to the Store Unit."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x34146",
|
||||
"EventName": "PM_MRK_LD_CMPL",
|
||||
"BriefDescription": "Marked load instruction completed."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x3C142",
|
||||
"EventName": "PM_MRK_XFER_FROM_SRC_PMC3",
|
||||
"BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x3C144",
|
||||
"EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC3",
|
||||
"BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[30:42]."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x3E158",
|
||||
"EventName": "PM_MRK_STCX_FAIL",
|
||||
@ -75,9 +165,19 @@
|
||||
"BriefDescription": "Marked store instruction finished."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x30068",
|
||||
"EventName": "PM_L1_ICACHE_RELOADED_PREF",
|
||||
"BriefDescription": "Counts all instruction cache prefetch reloads (includes demand turned into prefetch)."
|
||||
"EventCode": "0x3F150",
|
||||
"EventName": "PM_MRK_ST_DRAIN_CYC",
|
||||
"BriefDescription": "Cycles in which the marked store drained from the core to the L2."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x30162",
|
||||
"EventName": "PM_MRK_ISSUE_DEPENDENT_LOAD",
|
||||
"BriefDescription": "The marked instruction was dependent on a load. It is eligible for issue kill."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x301E2",
|
||||
"EventName": "PM_MRK_ST_CMPL",
|
||||
"BriefDescription": "Marked store completed and sent to nest. Note that this count excludes cache-inhibited stores."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x301E4",
|
||||
@ -85,39 +185,44 @@
|
||||
"BriefDescription": "Marked Branch Mispredicted. Includes direction and target."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x300F6",
|
||||
"EventName": "PM_LD_DEMAND_MISS_L1",
|
||||
"BriefDescription": "The L1 cache was reloaded with a line that fulfills a demand miss request. Counted at reload time, before finish."
|
||||
"EventCode": "0x40116",
|
||||
"EventName": "PM_MRK_LARX_FIN",
|
||||
"BriefDescription": "Marked load and reserve instruction (LARX) finished. LARX and STCX are instructions used to acquire a lock."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x300FE",
|
||||
"EventName": "PM_DATA_FROM_L3MISS",
|
||||
"BriefDescription": "The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss."
|
||||
"EventCode": "0x40132",
|
||||
"EventName": "PM_MRK_LSU_FIN",
|
||||
"BriefDescription": "LSU marked instruction finish."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x40012",
|
||||
"EventName": "PM_L1_ICACHE_RELOADED_ALL",
|
||||
"BriefDescription": "Counts all instruction cache reloads includes demand, prefetch, prefetch turned into demand and demand turned into prefetch."
|
||||
"EventCode": "0x44146",
|
||||
"EventName": "PM_MRK_STCX_CORE_CYC",
|
||||
"BriefDescription": "Cycles spent in the core portion of a marked STCX instruction. It starts counting when the instruction is decoded and stops counting when it drains into the L2."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x40134",
|
||||
"EventName": "PM_MRK_INST_TIMEO",
|
||||
"BriefDescription": "Marked instruction finish timeout (instruction was lost)."
|
||||
"EventCode": "0x4C142",
|
||||
"EventName": "PM_MRK_XFER_FROM_SRC_PMC4",
|
||||
"BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[45:57]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4505A",
|
||||
"EventName": "PM_SP_FLOP_CMPL",
|
||||
"BriefDescription": "Single Precision floating point instruction completed."
|
||||
"EventCode": "0x4C144",
|
||||
"EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC4",
|
||||
"BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[45:57]."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4D058",
|
||||
"EventName": "PM_VECTOR_FLOP_CMPL",
|
||||
"BriefDescription": "Vector floating point instruction completed."
|
||||
"EventCode": "0x4C15E",
|
||||
"EventName": "PM_MRK_DTLB_MISS_64K",
|
||||
"BriefDescription": "Marked Data TLB reload (after a miss) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4D05A",
|
||||
"EventName": "PM_NON_MATH_FLOP_CMPL",
|
||||
"BriefDescription": "Non Math instruction completed."
|
||||
"EventCode": "0x4E15E",
|
||||
"EventName": "PM_MRK_INST_FLUSHED",
|
||||
"BriefDescription": "The marked instruction was flushed."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x40164",
|
||||
"EventName": "PM_MRK_DERAT_MISS_2M",
|
||||
"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 2M for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x401E0",
|
||||
@ -125,8 +230,13 @@
|
||||
"BriefDescription": "Marked instruction completed."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x400FE",
|
||||
"EventName": "PM_DATA_FROM_MEMORY",
|
||||
"BriefDescription": "The processor's data cache was reloaded from local, remote, or distant memory due to a demand miss."
|
||||
"EventCode": "0x401E6",
|
||||
"EventName": "PM_MRK_INST_FROM_L3MISS",
|
||||
"BriefDescription": "The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x401E8",
|
||||
"EventName": "PM_MRK_DATA_FROM_L2MISS",
|
||||
"BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction."
|
||||
}
|
||||
]
|
||||
|
||||
@ -1,24 +1,9 @@
|
||||
[
|
||||
{
|
||||
"EventCode": "0x1000A",
|
||||
"EventName": "PM_PMC3_REWIND",
|
||||
"BriefDescription": "The speculative event selected for PMC3 rewinds and the counter for PMC3 is not charged."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x1C040",
|
||||
"EventName": "PM_XFER_FROM_SRC_PMC1",
|
||||
"BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x1C142",
|
||||
"EventName": "PM_MRK_XFER_FROM_SRC_PMC1",
|
||||
"BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x1C144",
|
||||
"EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC1",
|
||||
"BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[0:12]."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x1C056",
|
||||
"EventName": "PM_DERAT_MISS_4K",
|
||||
@ -34,26 +19,11 @@
|
||||
"EventName": "PM_DTLB_MISS_2M",
|
||||
"BriefDescription": "Data TLB reload (after a miss) page size 2M. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x1E056",
|
||||
"EventName": "PM_EXEC_STALL_STORE_PIPE",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the store unit. This does not include cycles spent handling store misses, PTESYNC instructions or TLBIE instructions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x1F150",
|
||||
"EventName": "PM_MRK_ST_L2_CYC",
|
||||
"BriefDescription": "Cycles from L2 RC dispatch to L2 RC completion."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x10062",
|
||||
"EventName": "PM_LD_L3MISS_PEND_CYC",
|
||||
"BriefDescription": "Cycles in which an L3 miss was pending for this thread."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x20010",
|
||||
"EventName": "PM_PMC1_OVERFLOW",
|
||||
"BriefDescription": "The event selected for PMC1 caused the event counter to overflow."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2001A",
|
||||
"EventName": "PM_ITLB_HIT",
|
||||
@ -79,36 +49,16 @@
|
||||
"EventName": "PM_DTLB_MISS_4K",
|
||||
"BriefDescription": "Data TLB reload (after a miss) page size 4K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2D154",
|
||||
"EventName": "PM_MRK_DERAT_MISS_64K",
|
||||
"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x200F6",
|
||||
"EventName": "PM_DERAT_MISS",
|
||||
"BriefDescription": "DERAT Reloaded to satisfy a DERAT miss. All page sizes are counted by this event. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x30016",
|
||||
"EventName": "PM_EXEC_STALL_DERAT_DTLB_MISS",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered a TLB miss and waited for it resolve."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x3C040",
|
||||
"EventName": "PM_XFER_FROM_SRC_PMC3",
|
||||
"BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x3C142",
|
||||
"EventName": "PM_MRK_XFER_FROM_SRC_PMC3",
|
||||
"BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x3C144",
|
||||
"EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC3",
|
||||
"BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[30:42]."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x3C054",
|
||||
"EventName": "PM_DERAT_MISS_16M",
|
||||
@ -124,21 +74,11 @@
|
||||
"EventName": "PM_LARX_FIN",
|
||||
"BriefDescription": "Load and reserve instruction (LARX) finished. LARX and STCX are instructions used to acquire a lock."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x301E2",
|
||||
"EventName": "PM_MRK_ST_CMPL",
|
||||
"BriefDescription": "Marked store completed and sent to nest. Note that this count excludes cache-inhibited stores."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x300FC",
|
||||
"EventName": "PM_DTLB_MISS",
|
||||
"BriefDescription": "The DPTEG required for the load/store instruction in execution was missing from the TLB. This event only counts for demand misses."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4D02C",
|
||||
"EventName": "PM_PMC1_REWIND",
|
||||
"BriefDescription": "The speculative event selected for PMC1 rewinds and the counter for PMC1 is not charged."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4003E",
|
||||
"EventName": "PM_LD_CMPL",
|
||||
@ -149,16 +89,6 @@
|
||||
"EventName": "PM_XFER_FROM_SRC_PMC4",
|
||||
"BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[45:57]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4C142",
|
||||
"EventName": "PM_MRK_XFER_FROM_SRC_PMC4",
|
||||
"BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[45:57]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4C144",
|
||||
"EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC4",
|
||||
"BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[45:57]."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4C056",
|
||||
"EventName": "PM_DTLB_MISS_16M",
|
||||
@ -168,20 +98,5 @@
|
||||
"EventCode": "0x4C05A",
|
||||
"EventName": "PM_DTLB_MISS_1G",
|
||||
"BriefDescription": "Data TLB reload (after a miss) page size 1G. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4C15E",
|
||||
"EventName": "PM_MRK_DTLB_MISS_64K",
|
||||
"BriefDescription": "Marked Data TLB reload (after a miss) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4D056",
|
||||
"EventName": "PM_NON_FMA_FLOP_CMPL",
|
||||
"BriefDescription": "Non FMA instruction completed."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x40164",
|
||||
"EventName": "PM_MRK_DERAT_MISS_2M",
|
||||
"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 2M for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
|
||||
}
|
||||
]
|
||||
|
||||
@ -1,23 +1,8 @@
|
||||
[
|
||||
{
|
||||
"EventCode": "0x10016",
|
||||
"EventName": "PM_VSU0_ISSUE",
|
||||
"BriefDescription": "VSU instruction issued to VSU pipe 0."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x1001C",
|
||||
"EventName": "PM_ULTRAVISOR_INST_CMPL",
|
||||
"BriefDescription": "PowerPC instruction completed while the thread was in ultravisor state."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x100F0",
|
||||
"EventName": "PM_CYC",
|
||||
"BriefDescription": "Processor cycles."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x10134",
|
||||
"EventName": "PM_MRK_ST_DONE_L2",
|
||||
"BriefDescription": "Marked store completed in L2."
|
||||
"EventCode": "0x1002C",
|
||||
"EventName": "PM_LD_PREFETCH_CACHE_LINE_MISS",
|
||||
"BriefDescription": "The L1 cache was reloaded with a line that fulfills a prefetch request."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x1505E",
|
||||
@ -34,36 +19,11 @@
|
||||
"EventName": "PM_ADJUNCT_CYC",
|
||||
"BriefDescription": "Cycles in which the thread is in Adjunct state. MSR[S HV PR] bits = 011."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x101E4",
|
||||
"EventName": "PM_MRK_L1_ICACHE_MISS",
|
||||
"BriefDescription": "Marked instruction suffered an instruction cache miss."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x101EA",
|
||||
"EventName": "PM_MRK_L1_RELOAD_VALID",
|
||||
"BriefDescription": "Marked demand reload."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x100F4",
|
||||
"EventName": "PM_FLOP_CMPL",
|
||||
"BriefDescription": "Floating Point Operations Completed. Includes any type. It counts once for each 1, 2, 4 or 8 flop instruction. Use PM_1|2|4|8_FLOP_CMPL events to count flops."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x100FA",
|
||||
"EventName": "PM_RUN_LATCH_ANY_THREAD_CYC",
|
||||
"BriefDescription": "Cycles when at least one thread has the run latch set."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x100FC",
|
||||
"EventName": "PM_LD_REF_L1",
|
||||
"BriefDescription": "All L1 D cache load references counted at finish, gated by reject. In P9 and earlier this event counted only cacheable loads but in P10 both cacheable and non-cacheable loads are included."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2000C",
|
||||
"EventName": "PM_RUN_LATCH_ALL_THREADS_CYC",
|
||||
"BriefDescription": "Cycles when the run latch is set for all threads."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2E010",
|
||||
"EventName": "PM_ADJUNCT_INST_CMPL",
|
||||
@ -74,26 +34,6 @@
|
||||
"EventName": "PM_STCX_FIN",
|
||||
"BriefDescription": "Conditional store instruction (STCX) finished. LARX and STCX are instructions used to acquire a lock."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x20130",
|
||||
"EventName": "PM_MRK_INST_DECODED",
|
||||
"BriefDescription": "An instruction was marked at decode time. Random Instruction Sampling (RIS) only."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x20132",
|
||||
"EventName": "PM_MRK_DFU_ISSUE",
|
||||
"BriefDescription": "The marked instruction was a decimal floating point operation issued to the VSU. Measured at issue time."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x20134",
|
||||
"EventName": "PM_MRK_FXU_ISSUE",
|
||||
"BriefDescription": "The marked instruction was a fixed point operation issued to the VSU. Measured at issue time."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2505C",
|
||||
"EventName": "PM_VSU_ISSUE",
|
||||
"BriefDescription": "At least one VSU instruction was issued to one of the VSU pipes. Up to 4 per cycle. Includes fixed point operations."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2F054",
|
||||
"EventName": "PM_DISP_SS1_2_INSTR_CYC",
|
||||
@ -104,40 +44,15 @@
|
||||
"EventName": "PM_DISP_SS1_4_INSTR_CYC",
|
||||
"BriefDescription": "Cycles in which Superslice 1 dispatches either 3 or 4 instructions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2006C",
|
||||
"EventName": "PM_RUN_CYC_SMT4_MODE",
|
||||
"BriefDescription": "Cycles when this thread's run latch is set and the core is in SMT4 mode."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x201E0",
|
||||
"EventName": "PM_MRK_DATA_FROM_MEMORY",
|
||||
"BriefDescription": "The processor's data cache was reloaded from local, remote, or distant memory due to a demand miss for a marked load."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x201E4",
|
||||
"EventName": "PM_MRK_DATA_FROM_L3MISS",
|
||||
"BriefDescription": "The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x201E8",
|
||||
"EventName": "PM_THRESH_EXC_512",
|
||||
"BriefDescription": "Threshold counter exceeded a value of 512."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x200F2",
|
||||
"EventName": "PM_INST_DISP",
|
||||
"BriefDescription": "PowerPC instruction dispatched."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x30132",
|
||||
"EventName": "PM_MRK_VSU_FIN",
|
||||
"BriefDescription": "VSU marked instruction finished. Excludes simple FX instructions issued to the Store Unit."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x30038",
|
||||
"EventName": "PM_EXEC_STALL_DMISS_LMEM",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local memory, local OpenCAPI cache, or local OpenCAPI memory."
|
||||
"EventCode": "0x200FD",
|
||||
"EventName": "PM_L1_ICACHE_MISS",
|
||||
"BriefDescription": "Demand instruction cache miss."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x3F04A",
|
||||
@ -149,11 +64,6 @@
|
||||
"EventName": "PM_PRIVILEGED_INST_CMPL",
|
||||
"BriefDescription": "PowerPC instruction completed while the thread was in Privileged state."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x3F150",
|
||||
"EventName": "PM_MRK_ST_DRAIN_CYC",
|
||||
"BriefDescription": "Cycles in which the marked store drained from the core to the L2."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x3F054",
|
||||
"EventName": "PM_DISP_SS0_4_INSTR_CYC",
|
||||
@ -165,103 +75,43 @@
|
||||
"BriefDescription": "Cycles in which Superslice 0 dispatches either 5, 6, 7 or 8 instructions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x30162",
|
||||
"EventName": "PM_MRK_ISSUE_DEPENDENT_LOAD",
|
||||
"BriefDescription": "The marked instruction was dependent on a load. It is eligible for issue kill."
|
||||
"EventCode": "0x30068",
|
||||
"EventName": "PM_L1_ICACHE_RELOADED_PREF",
|
||||
"BriefDescription": "Counts all instruction cache prefetch reloads (includes demand turned into prefetch)."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x40114",
|
||||
"EventName": "PM_MRK_START_PROBE_NOP_DISP",
|
||||
"BriefDescription": "Marked Start probe nop dispatched. Instruction AND R0,R0,R0."
|
||||
"EventCode": "0x300F6",
|
||||
"EventName": "PM_LD_DEMAND_MISS_L1",
|
||||
"BriefDescription": "The L1 cache was reloaded with a line that fulfills a demand miss request. Counted at reload time, before finish."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4001C",
|
||||
"EventName": "PM_VSU_FIN",
|
||||
"BriefDescription": "VSU instruction finished."
|
||||
"EventCode": "0x300FE",
|
||||
"EventName": "PM_DATA_FROM_L3MISS",
|
||||
"BriefDescription": "The processor's data cache was reloaded from a source other than the local core's L1, L2, or L3 due to a demand miss."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4C01A",
|
||||
"EventName": "PM_EXEC_STALL_DMISS_OFF_NODE",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a distant chip."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4D012",
|
||||
"EventName": "PM_PMC3_SAVED",
|
||||
"BriefDescription": "The conditions for the speculative event selected for PMC3 are met and PMC3 is charged."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4D022",
|
||||
"EventName": "PM_HYPERVISOR_INST_CMPL",
|
||||
"BriefDescription": "PowerPC instruction completed while the thread was in hypervisor state."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4D026",
|
||||
"EventName": "PM_ULTRAVISOR_CYC",
|
||||
"BriefDescription": "Cycles when the thread is in Ultravisor state. MSR[S HV PR]=110."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4D028",
|
||||
"EventName": "PM_PRIVILEGED_CYC",
|
||||
"BriefDescription": "Cycles when the thread is in Privileged state. MSR[S HV PR]=x00."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x40030",
|
||||
"EventName": "PM_INST_FIN",
|
||||
"BriefDescription": "Instruction finished."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x44146",
|
||||
"EventName": "PM_MRK_STCX_CORE_CYC",
|
||||
"BriefDescription": "Cycles spent in the core portion of a marked STCX instruction. It starts counting when the instruction is decoded and stops counting when it drains into the L2."
|
||||
"EventCode": "0x40012",
|
||||
"EventName": "PM_L1_ICACHE_RELOADED_ALL",
|
||||
"BriefDescription": "Counts all instruction cache reloads includes demand, prefetch, prefetch turned into demand and demand turned into prefetch."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x44054",
|
||||
"EventName": "PM_VECTOR_LD_CMPL",
|
||||
"BriefDescription": "Vector load instruction completed."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x45054",
|
||||
"EventName": "PM_FMA_CMPL",
|
||||
"BriefDescription": "Two floating point instruction completed (FMA class of instructions: fmadd, fnmadd, fmsub, fnmsub). Scalar instructions only."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x45056",
|
||||
"EventName": "PM_SCALAR_FLOP_CMPL",
|
||||
"BriefDescription": "Scalar floating point instruction completed."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4505C",
|
||||
"EventName": "PM_MATH_FLOP_CMPL",
|
||||
"BriefDescription": "Math floating point instruction completed."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4D05E",
|
||||
"EventName": "PM_BR_CMPL",
|
||||
"BriefDescription": "A branch completed. All branches are included."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4E15E",
|
||||
"EventName": "PM_MRK_INST_FLUSHED",
|
||||
"BriefDescription": "The marked instruction was flushed."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x401E6",
|
||||
"EventName": "PM_MRK_INST_FROM_L3MISS",
|
||||
"BriefDescription": "The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x401E8",
|
||||
"EventName": "PM_MRK_DATA_FROM_L2MISS",
|
||||
"BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x400F0",
|
||||
"EventName": "PM_LD_DEMAND_MISS_L1_FIN",
|
||||
"BriefDescription": "Load missed L1, counted at finish time."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x500FA",
|
||||
"EventName": "PM_RUN_INST_CMPL",
|
||||
"BriefDescription": "PowerPC instruction completed while the run latch is set."
|
||||
"EventCode": "0x400FE",
|
||||
"EventName": "PM_DATA_FROM_MEMORY",
|
||||
"BriefDescription": "The processor's data cache was reloaded from local, remote, or distant memory due to a demand miss."
|
||||
}
|
||||
]
|
||||
|
||||
@ -1,8 +1,13 @@
|
||||
[
|
||||
{
|
||||
"EventCode": "0x100FE",
|
||||
"EventName": "PM_INST_CMPL",
|
||||
"BriefDescription": "PowerPC instruction completed."
|
||||
"EventCode": "0x10004",
|
||||
"EventName": "PM_EXEC_STALL_TRANSLATION",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered a TLB miss or ERAT miss and waited for it to resolve."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x10006",
|
||||
"EventName": "PM_DISP_STALL_HELD_OTHER_CYC",
|
||||
"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch for any other reason."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x1000C",
|
||||
@ -30,14 +35,19 @@
|
||||
"BriefDescription": "Cycles in which an instruction reload is pending to satisfy a demand miss."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x10022",
|
||||
"EventName": "PM_PMC2_SAVED",
|
||||
"BriefDescription": "The conditions for the speculative event selected for PMC2 are met and PMC2 is charged."
|
||||
"EventCode": "0x10038",
|
||||
"EventName": "PM_DISP_STALL_TRANSLATION",
|
||||
"BriefDescription": "Cycles when dispatch was stalled for this thread because the MMU was handling a translation miss."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x10024",
|
||||
"EventName": "PM_PMC5_OVERFLOW",
|
||||
"BriefDescription": "The event selected for PMC5 caused the event counter to overflow."
|
||||
"EventCode": "0x1003A",
|
||||
"EventName": "PM_DISP_STALL_BR_MPRED_IC_L2",
|
||||
"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L2 after suffering a branch mispredict."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x1003C",
|
||||
"EventName": "PM_EXEC_STALL_DMISS_L2L3",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from either the local L2 or local L3."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x10058",
|
||||
@ -54,11 +64,36 @@
|
||||
"EventName": "PM_DERAT_MISS_2M",
|
||||
"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 2M. Implies radix translation. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x1D05E",
|
||||
"EventName": "PM_DISP_STALL_HELD_HALT_CYC",
|
||||
"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch because of power management."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x1E050",
|
||||
"EventName": "PM_DISP_STALL_HELD_STF_MAPPER_CYC",
|
||||
"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch because the STF mapper/SRB was full. Includes GPR (count, link, tar), VSR, VMR, FPR."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x1E054",
|
||||
"EventName": "PM_EXEC_STALL_DMISS_L21_L31",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from another core's L2 or L3 on the same chip."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x1E056",
|
||||
"EventName": "PM_EXEC_STALL_STORE_PIPE",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the store unit. This does not include cycles spent handling store misses, PTESYNC instructions or TLBIE instructions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x1E05A",
|
||||
"EventName": "PM_CMPL_STALL_LWSYNC",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a lwsync waiting to complete."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x10064",
|
||||
"EventName": "PM_DISP_STALL_IC_L2",
|
||||
"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L2."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x10068",
|
||||
"EventName": "PM_BR_FIN",
|
||||
@ -70,9 +105,9 @@
|
||||
"BriefDescription": "Simple fixed point instruction issued to the store unit. Measured at finish time."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x1006C",
|
||||
"EventName": "PM_RUN_CYC_ST_MODE",
|
||||
"BriefDescription": "Cycles when the run latch is set and the core is in ST mode."
|
||||
"EventCode": "0x100F8",
|
||||
"EventName": "PM_DISP_STALL_CYC",
|
||||
"BriefDescription": "Cycles the ICT has no itags assigned to this thread (no instructions were dispatched during these cycles)."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x20004",
|
||||
@ -80,94 +115,144 @@
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was dispatched but not issued yet."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2000A",
|
||||
"EventName": "PM_HYPERVISOR_CYC",
|
||||
"BriefDescription": "Cycles when the thread is in Hypervisor state. MSR[S HV PR]=010."
|
||||
"EventCode": "0x20006",
|
||||
"EventName": "PM_DISP_STALL_HELD_ISSQ_FULL_CYC",
|
||||
"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch due to Issue queue full. Includes issue queue and branch queue."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2000E",
|
||||
"EventName": "PM_LSU_LD1_FIN",
|
||||
"BriefDescription": "LSU Finished an internal operation in LD1 port."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2C010",
|
||||
"EventName": "PM_EXEC_STALL_LSU",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the Load Store Unit. This does not include simple fixed point instructions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2C014",
|
||||
"EventName": "PM_CMPL_STALL_SPECIAL",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline required special handling before completing."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2C016",
|
||||
"EventName": "PM_DISP_STALL_IERAT_ONLY_MISS",
|
||||
"BriefDescription": "Cycles when dispatch was stalled while waiting to resolve an instruction ERAT miss."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2C018",
|
||||
"EventName": "PM_EXEC_STALL_DMISS_L3MISS",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a source beyond the local L2 or local L3."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2C01C",
|
||||
"EventName": "PM_EXEC_STALL_DMISS_OFF_CHIP",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a remote chip."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2C01E",
|
||||
"EventName": "PM_DISP_STALL_BR_MPRED_IC_L3",
|
||||
"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L3 after suffering a branch mispredict."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2D010",
|
||||
"EventName": "PM_LSU_ST1_FIN",
|
||||
"BriefDescription": "LSU Finished an internal operation in ST1 port."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x10016",
|
||||
"EventName": "PM_VSU0_ISSUE",
|
||||
"BriefDescription": "VSU instruction issued to VSU pipe 0."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2D012",
|
||||
"EventName": "PM_VSU1_ISSUE",
|
||||
"BriefDescription": "VSU instruction issued to VSU pipe 1."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2505C",
|
||||
"EventName": "PM_VSU_ISSUE",
|
||||
"BriefDescription": "At least one VSU instruction was issued to one of the VSU pipes. Up to 4 per cycle. Includes fixed point operations."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4001C",
|
||||
"EventName": "PM_VSU_FIN",
|
||||
"BriefDescription": "VSU instruction finished."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2D018",
|
||||
"EventName": "PM_EXEC_STALL_VSU",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the VSU (includes FXU, VSU, CRU)."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2D01A",
|
||||
"EventName": "PM_DISP_STALL_IC_MISS",
|
||||
"BriefDescription": "Cycles when dispatch was stalled for this thread due to an instruction cache miss."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2D01C",
|
||||
"EventName": "PM_CMPL_STALL_STCX",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a stcx waiting for resolution from the nest before completing."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2E018",
|
||||
"EventName": "PM_DISP_STALL_FETCH",
|
||||
"BriefDescription": "Cycles when dispatch was stalled for this thread because Fetch was being held."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2E01A",
|
||||
"EventName": "PM_DISP_STALL_HELD_XVFC_MAPPER_CYC",
|
||||
"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch because the XVFC mapper/SRB was full."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2E01C",
|
||||
"EventName": "PM_EXEC_STALL_TLBIE",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a TLBIE instruction executing in the Load Store Unit."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2E01E",
|
||||
"EventName": "PM_EXEC_STALL_NTC_FLUSH",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in any unit before it was flushed. Note that if the flush of the oldest instruction happens after finish, the cycles from dispatch to issue will be included in PM_DISP_STALL and the cycles from issue to finish will be included in PM_EXEC_STALL and its corresponding children. This event will also count cycles when the previous next-to-finish (NTF) instruction is still completing and the new NTF instruction is stalled at dispatch."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2013C",
|
||||
"EventName": "PM_MRK_FX_LSU_FIN",
|
||||
"BriefDescription": "The marked instruction was simple fixed point that was issued to the store unit. Measured at finish time."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2405A",
|
||||
"EventName": "PM_NTC_FIN",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline (NTC) finishes. Note that instructions can finish out of order, therefore not all the instructions that finish have a Next-to-complete status."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x201E2",
|
||||
"EventName": "PM_MRK_LD_MISS_L1",
|
||||
"BriefDescription": "Marked demand data load miss counted at finish time."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x200F4",
|
||||
"EventName": "PM_RUN_CYC",
|
||||
"BriefDescription": "Processor cycles gated by the run latch."
|
||||
"EventCode": "0x30004",
|
||||
"EventName": "PM_DISP_STALL_FLUSH",
|
||||
"BriefDescription": "Cycles when dispatch was stalled because of a flush that happened to an instruction(s) that was not yet next-to-complete (NTC). PM_EXEC_STALL_NTC_FLUSH only includes instructions that were flushed after becoming NTC."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x30008",
|
||||
"EventName": "PM_EXEC_STALL",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting to finish in one of the execution units (BRU, LSU, VSU). Only cycles between issue and finish are counted in this category."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x30014",
|
||||
"EventName": "PM_EXEC_STALL_STORE",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a store instruction executing in the Load Store Unit."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x30016",
|
||||
"EventName": "PM_EXEC_STALL_DERAT_DTLB_MISS",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered a TLB miss and waited for it resolve."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x30018",
|
||||
"EventName": "PM_DISP_STALL_HELD_SCOREBOARD_CYC",
|
||||
"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch while waiting on the Scoreboard. This event combines VSCR and FPSCR together."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x3001A",
|
||||
"EventName": "PM_LSU_ST2_FIN",
|
||||
"BriefDescription": "LSU Finished an internal operation in ST2 port."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x30020",
|
||||
"EventName": "PM_PMC2_REWIND",
|
||||
"BriefDescription": "The speculative event selected for PMC2 rewinds and the counter for PMC2 is not charged."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x30022",
|
||||
"EventName": "PM_PMC4_SAVED",
|
||||
"BriefDescription": "The conditions for the speculative event selected for PMC4 are met and PMC4 is charged."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x30024",
|
||||
"EventName": "PM_PMC6_OVERFLOW",
|
||||
"BriefDescription": "The event selected for PMC6 caused the event counter to overflow."
|
||||
"EventCode": "0x30026",
|
||||
"EventName": "PM_EXEC_STALL_STORE_MISS",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a store whose cache line was not resident in the L1 and was waiting for allocation of the missing line into the L1."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x30028",
|
||||
@ -179,6 +264,11 @@
|
||||
"EventName": "PM_EXEC_STALL_SIMPLE_FX",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a simple fixed point instruction executing in the Load Store Unit."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x30038",
|
||||
"EventName": "PM_EXEC_STALL_DMISS_LMEM",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local memory, local OpenCAPI cache, or local OpenCAPI memory."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x3003A",
|
||||
"EventName": "PM_CMPL_STALL_EXCEPTION",
|
||||
@ -194,6 +284,31 @@
|
||||
"EventName": "PM_TLBIE_FIN",
|
||||
"BriefDescription": "TLBIE instruction finished in the LSU. Two TLBIEs can finish each cycle. All will be counted."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x34054",
|
||||
"EventName": "PM_EXEC_STALL_DMISS_L2L3_NOCONFLICT",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local L2 or local L3, without a dispatch conflict."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x34056",
|
||||
"EventName": "PM_EXEC_STALL_LOAD_FINISH",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was finishing a load after its data was reloaded from a data source beyond the local L1; cycles in which the LSU was processing an L1-hit; cycles in which the next-to-finish (NTF) instruction merged with another load in the LMQ; cycles in which the NTF instruction is waiting for a data reload for a load miss, but the data comes back with a non-NTF instruction."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x34058",
|
||||
"EventName": "PM_DISP_STALL_BR_MPRED_ICMISS",
|
||||
"BriefDescription": "Cycles when dispatch was stalled after a mispredicted branch resulted in an instruction cache miss."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x3D05C",
|
||||
"EventName": "PM_DISP_STALL_HELD_RENAME_CYC",
|
||||
"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch because the mapper/SRB was full. Includes GPR (count, link, tar), VSR, VMR, FPR and XVFC."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x3E052",
|
||||
"EventName": "PM_DISP_STALL_IC_L3",
|
||||
"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L3."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x30066",
|
||||
"EventName": "PM_LSU_FIN",
|
||||
@ -210,25 +325,45 @@
|
||||
"BriefDescription": "Cycles in which both instructions in the ICT entry pair show as finished. These are the cycles between finish and completion for the oldest pair of instructions in the pipeline."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x40010",
|
||||
"EventName": "PM_PMC3_OVERFLOW",
|
||||
"BriefDescription": "The event selected for PMC3 caused the event counter to overflow."
|
||||
"EventCode": "0x4C010",
|
||||
"EventName": "PM_DISP_STALL_BR_MPRED_IC_L3MISS",
|
||||
"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from sources beyond the local L3 after suffering a mispredicted branch."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4C012",
|
||||
"EventName": "PM_EXEC_STALL_DERAT_ONLY_MISS",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered an ERAT miss and waited for it resolve."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4C016",
|
||||
"EventName": "PM_EXEC_STALL_DMISS_L2L3_CONFLICT",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local L2 or local L3, with a dispatch conflict."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4C018",
|
||||
"EventName": "PM_CMPL_STALL",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline cannot complete because the thread was blocked for any reason."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4C01A",
|
||||
"EventName": "PM_EXEC_STALL_DMISS_OFF_NODE",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a distant chip."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4C01E",
|
||||
"EventName": "PM_LSU_ST3_FIN",
|
||||
"BriefDescription": "LSU Finished an internal operation in ST3 port."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4D014",
|
||||
"EventName": "PM_EXEC_STALL_LOAD",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a load instruction executing in the Load Store Unit."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4D016",
|
||||
"EventName": "PM_EXEC_STALL_PTESYNC",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a PTESYNC instruction executing in the Load Store Unit."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4D018",
|
||||
"EventName": "PM_EXEC_STALL_BRU",
|
||||
@ -244,31 +379,41 @@
|
||||
"EventName": "PM_EXEC_STALL_TLBIEL",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a TLBIEL instruction executing in the Load Store Unit. TLBIEL instructions have lower overhead than TLBIE instructions because they don't get set to the nest."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4D01E",
|
||||
"EventName": "PM_DISP_STALL_BR_MPRED",
|
||||
"BriefDescription": "Cycles when dispatch was stalled for this thread due to a mispredicted branch."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4E010",
|
||||
"EventName": "PM_DISP_STALL_IC_L3MISS",
|
||||
"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from any source beyond the local L3."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4E012",
|
||||
"EventName": "PM_EXEC_STALL_UNKNOWN",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline completed without an ntf_type pulse. The ntf_pulse was missed by the ISU because the next-to-finish (NTF) instruction finishes and completions came too close together."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4E01A",
|
||||
"EventName": "PM_DISP_STALL_HELD_CYC",
|
||||
"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch for any reason."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4D020",
|
||||
"EventName": "PM_VSU3_ISSUE",
|
||||
"BriefDescription": "VSU instruction was issued to VSU pipe 3."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x40132",
|
||||
"EventName": "PM_MRK_LSU_FIN",
|
||||
"BriefDescription": "LSU marked instruction finish."
|
||||
"EventCode": "0x4003C",
|
||||
"EventName": "PM_DISP_STALL_HELD_SYNC_CYC",
|
||||
"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch because of a synchronizing instruction that requires the ICT to be empty before dispatch."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x45058",
|
||||
"EventName": "PM_IC_MISS_CMPL",
|
||||
"BriefDescription": "Non-speculative instruction cache miss, counted at completion."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4D052",
|
||||
"EventName": "PM_2FLOP_CMPL",
|
||||
"BriefDescription": "Double Precision vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg completed."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x400F2",
|
||||
"EventName": "PM_1PLUS_PPC_DISP",
|
||||
|
||||
@ -1,22 +1,197 @@
|
||||
[
|
||||
{
|
||||
"EventCode": "0x100FE",
|
||||
"EventName": "PM_INST_CMPL",
|
||||
"BriefDescription": "PowerPC instruction completed."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x1000A",
|
||||
"EventName": "PM_PMC3_REWIND",
|
||||
"BriefDescription": "The speculative event selected for PMC3 rewinds and the counter for PMC3 is not charged."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x10010",
|
||||
"EventName": "PM_PMC4_OVERFLOW",
|
||||
"BriefDescription": "The event selected for PMC4 caused the event counter to overflow."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x1001C",
|
||||
"EventName": "PM_ULTRAVISOR_INST_CMPL",
|
||||
"BriefDescription": "PowerPC instruction completed while the thread was in ultravisor state."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x100F0",
|
||||
"EventName": "PM_CYC",
|
||||
"BriefDescription": "Processor cycles."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x10020",
|
||||
"EventName": "PM_PMC4_REWIND",
|
||||
"BriefDescription": "The speculative event selected for PMC4 rewinds and the counter for PMC4 is not charged."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x10022",
|
||||
"EventName": "PM_PMC2_SAVED",
|
||||
"BriefDescription": "The conditions for the speculative event selected for PMC2 are met and PMC2 is charged."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x10024",
|
||||
"EventName": "PM_PMC5_OVERFLOW",
|
||||
"BriefDescription": "The event selected for PMC5 caused the event counter to overflow."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x1F15E",
|
||||
"EventName": "PM_MRK_START_PROBE_NOP_CMPL",
|
||||
"BriefDescription": "Marked Start probe nop (AND R0,R0,R0) completed."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x1006C",
|
||||
"EventName": "PM_RUN_CYC_ST_MODE",
|
||||
"BriefDescription": "Cycles when the run latch is set and the core is in ST mode."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x101E8",
|
||||
"EventName": "PM_THRESH_EXC_256",
|
||||
"BriefDescription": "Threshold counter exceeded a count of 256."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x101EC",
|
||||
"EventName": "PM_THRESH_MET",
|
||||
"BriefDescription": "Threshold exceeded."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x100FA",
|
||||
"EventName": "PM_RUN_LATCH_ANY_THREAD_CYC",
|
||||
"BriefDescription": "Cycles when at least one thread has the run latch set."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2000A",
|
||||
"EventName": "PM_HYPERVISOR_CYC",
|
||||
"BriefDescription": "Cycles when the thread is in Hypervisor state. MSR[S HV PR]=010."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2000C",
|
||||
"EventName": "PM_RUN_LATCH_ALL_THREADS_CYC",
|
||||
"BriefDescription": "Cycles when the run latch is set for all threads."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x20010",
|
||||
"EventName": "PM_PMC1_OVERFLOW",
|
||||
"BriefDescription": "The event selected for PMC1 caused the event counter to overflow."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2006C",
|
||||
"EventName": "PM_RUN_CYC_SMT4_MODE",
|
||||
"BriefDescription": "Cycles when this thread's run latch is set and the core is in SMT4 mode."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x201E6",
|
||||
"EventName": "PM_THRESH_EXC_32",
|
||||
"BriefDescription": "Threshold counter exceeded a value of 32."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x201E8",
|
||||
"EventName": "PM_THRESH_EXC_512",
|
||||
"BriefDescription": "Threshold counter exceeded a value of 512."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x200F4",
|
||||
"EventName": "PM_RUN_CYC",
|
||||
"BriefDescription": "Processor cycles gated by the run latch."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x30010",
|
||||
"EventName": "PM_PMC2_OVERFLOW",
|
||||
"BriefDescription": "The event selected for PMC2 caused the event counter to overflow."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x30020",
|
||||
"EventName": "PM_PMC2_REWIND",
|
||||
"BriefDescription": "The speculative event selected for PMC2 rewinds and the counter for PMC2 is not charged."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x30022",
|
||||
"EventName": "PM_PMC4_SAVED",
|
||||
"BriefDescription": "The conditions for the speculative event selected for PMC4 are met and PMC4 is charged."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x30024",
|
||||
"EventName": "PM_PMC6_OVERFLOW",
|
||||
"BriefDescription": "The event selected for PMC6 caused the event counter to overflow."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x3006C",
|
||||
"EventName": "PM_RUN_CYC_SMT2_MODE",
|
||||
"BriefDescription": "Cycles when this thread's run latch is set and the core is in SMT2 mode."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x301E8",
|
||||
"EventName": "PM_THRESH_EXC_64",
|
||||
"BriefDescription": "Threshold counter exceeded a value of 64."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x45050",
|
||||
"EventName": "PM_1FLOP_CMPL",
|
||||
"BriefDescription": "One floating point instruction completed (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg)."
|
||||
"EventCode": "0x301EA",
|
||||
"EventName": "PM_THRESH_EXC_1024",
|
||||
"BriefDescription": "Threshold counter exceeded a value of 1024."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x45052",
|
||||
"EventName": "PM_4FLOP_CMPL",
|
||||
"BriefDescription": "Four floating point instruction completed (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg)."
|
||||
"EventCode": "0x40010",
|
||||
"EventName": "PM_PMC3_OVERFLOW",
|
||||
"BriefDescription": "The event selected for PMC3 caused the event counter to overflow."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4D054",
|
||||
"EventName": "PM_8FLOP_CMPL",
|
||||
"BriefDescription": "Four Double Precision vector instruction completed."
|
||||
"EventCode": "0x40114",
|
||||
"EventName": "PM_MRK_START_PROBE_NOP_DISP",
|
||||
"BriefDescription": "Marked Start probe nop dispatched. Instruction AND R0,R0,R0."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4D010",
|
||||
"EventName": "PM_PMC1_SAVED",
|
||||
"BriefDescription": "The conditions for the speculative event selected for PMC1 are met and PMC1 is charged."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4D012",
|
||||
"EventName": "PM_PMC3_SAVED",
|
||||
"BriefDescription": "The conditions for the speculative event selected for PMC3 are met and PMC3 is charged."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4D022",
|
||||
"EventName": "PM_HYPERVISOR_INST_CMPL",
|
||||
"BriefDescription": "PowerPC instruction completed while the thread was in hypervisor state."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4D026",
|
||||
"EventName": "PM_ULTRAVISOR_CYC",
|
||||
"BriefDescription": "Cycles when the thread is in Ultravisor state. MSR[S HV PR]=110."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4D028",
|
||||
"EventName": "PM_PRIVILEGED_CYC",
|
||||
"BriefDescription": "Cycles when the thread is in Privileged state. MSR[S HV PR]=x00."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4D02C",
|
||||
"EventName": "PM_PMC1_REWIND",
|
||||
"BriefDescription": "The speculative event selected for PMC1 rewinds and the counter for PMC1 is not charged."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x40030",
|
||||
"EventName": "PM_INST_FIN",
|
||||
"BriefDescription": "Instruction finished."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x40134",
|
||||
"EventName": "PM_MRK_INST_TIMEO",
|
||||
"BriefDescription": "Marked instruction finish timeout (instruction was lost)."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x401EA",
|
||||
"EventName": "PM_THRESH_EXC_128",
|
||||
"BriefDescription": "Threshold counter exceeded a value of 128."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x400FA",
|
||||
"EventName": "PM_RUN_INST_CMPL",
|
||||
"BriefDescription": "PowerPC instruction completed while the run latch is set."
|
||||
}
|
||||
]
|
||||
|
||||
@ -1,29 +1,9 @@
|
||||
[
|
||||
{
|
||||
"EventCode": "0x1F15E",
|
||||
"EventName": "PM_MRK_START_PROBE_NOP_CMPL",
|
||||
"BriefDescription": "Marked Start probe nop (AND R0,R0,R0) completed."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x20018",
|
||||
"EventName": "PM_ST_FWD",
|
||||
"BriefDescription": "Store forwards that finished."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2011C",
|
||||
"EventName": "PM_MRK_NTF_CYC",
|
||||
"BriefDescription": "Cycles in which the marked instruction is the oldest in the pipeline (next-to-finish or next-to-complete)."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2E01C",
|
||||
"EventName": "PM_EXEC_STALL_TLBIE",
|
||||
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a TLBIE instruction executing in the Load Store Unit."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x201E6",
|
||||
"EventName": "PM_THRESH_EXC_32",
|
||||
"BriefDescription": "Threshold counter exceeded a value of 32."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x200F0",
|
||||
"EventName": "PM_ST_CMPL",
|
||||
@ -33,20 +13,5 @@
|
||||
"EventCode": "0x200FE",
|
||||
"EventName": "PM_DATA_FROM_L2MISS",
|
||||
"BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x30010",
|
||||
"EventName": "PM_PMC2_OVERFLOW",
|
||||
"BriefDescription": "The event selected for PMC2 caused the event counter to overflow."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4D010",
|
||||
"EventName": "PM_PMC1_SAVED",
|
||||
"BriefDescription": "The conditions for the speculative event selected for PMC1 are met and PMC1 is charged."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4D05C",
|
||||
"EventName": "PM_DPP_FLOP_CMPL",
|
||||
"BriefDescription": "Double-Precision or Quad-Precision instruction completed."
|
||||
}
|
||||
]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user