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ARM: dts: imx: Add TDA19971 HDMI Receiver to GW54xx
The GW54xx has a front-panel microHDMI connector routed to a TDA19971 which is connected the the IPU CSI when using IMX6Q. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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3117e851ce
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@ -12,10 +12,30 @@
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/dts-v1/;
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#include "imx6q.dtsi"
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#include "imx6qdl-gw54xx.dtsi"
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#include <dt-bindings/media/tda1997x.h>
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/ {
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model = "Gateworks Ventana i.MX6 Dual/Quad GW54XX";
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compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q";
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sound-digital {
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compatible = "simple-audio-card";
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simple-audio-card,name = "tda1997x-audio";
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simple-audio-card,dai-link@0 {
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format = "i2s";
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cpu {
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sound-dai = <&ssi2>;
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};
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codec {
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bitclock-master;
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frame-master;
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sound-dai = <&hdmi_receiver>;
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};
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};
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};
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};
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&i2c3 {
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@ -35,6 +55,61 @@
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};
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};
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};
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hdmi_receiver: hdmi-receiver@48 {
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compatible = "nxp,tda19971";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_tda1997x>;
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reg = <0x48>;
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interrupt-parent = <&gpio1>;
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interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
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DOVDD-supply = <®_3p3v>;
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AVDD-supply = <&sw4_reg>;
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DVDD-supply = <&sw4_reg>;
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#sound-dai-cells = <0>;
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nxp,audout-format = "i2s";
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nxp,audout-layout = <0>;
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nxp,audout-width = <16>;
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nxp,audout-mclk-fs = <128>;
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/*
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* The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
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* and Y[11:4] across 16bits in the same cycle
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* which we map to VP[15:08]<->CSI_DATA[19:12]
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*/
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nxp,vidout-portcfg =
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/*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/
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< TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
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/*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/
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< TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
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/*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/
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< TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
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/*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/
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< TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
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port {
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tda1997x_to_ipu1_csi0_mux: endpoint {
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remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
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bus-width = <16>;
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hsync-active = <1>;
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vsync-active = <1>;
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data-active = <1>;
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};
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};
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};
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};
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&ipu1_csi0_from_ipu1_csi0_mux {
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bus-width = <16>;
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};
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&ipu1_csi0_mux_from_parallel_sensor {
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remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>;
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bus-width = <16>;
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};
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&ipu1_csi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ipu1_csi0>;
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};
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&ipu2_csi1_from_ipu2_csi1_mux {
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@ -63,6 +138,30 @@
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>;
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};
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pinctrl_ipu1_csi0: ipu1_csi0grp {
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fsl,pins = <
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MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x1b0b0
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MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x1b0b0
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MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x1b0b0
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MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x1b0b0
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MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0
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MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0
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MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0
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MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0
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MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
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MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
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MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
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MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
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MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
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MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
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MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
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MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
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MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
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MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
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MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
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>;
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};
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pinctrl_ipu2_csi1: ipu2_csi1grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0
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@ -78,4 +177,10 @@
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MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0
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>;
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};
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pinctrl_tda1997x: tda1997xgrp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
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>;
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};
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};
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@ -10,6 +10,7 @@
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/sound/fsl-imx-audmux.h>
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/ {
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/* these are used by bootloader for disabling nodes */
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@ -115,12 +116,12 @@
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};
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};
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sound {
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sound-analog {
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compatible = "fsl,imx6q-ventana-sgtl5000",
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"fsl,imx-audio-sgtl5000";
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model = "sgtl5000-audio";
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ssi-controller = <&ssi1>;
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audio-codec = <&codec>;
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audio-codec = <&sgtl5000>;
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audio-routing =
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"MIC_IN", "Mic Jack",
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"Mic Jack", "Mic Bias",
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@ -134,6 +135,25 @@
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */
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status = "okay";
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ssi2 {
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fsl,audmux-port = <1>;
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fsl,port-config = <
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(IMX_AUDMUX_V2_PTCR_TFSDIR |
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IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */
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IMX_AUDMUX_V2_PTCR_TCLKDIR |
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IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */
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IMX_AUDMUX_V2_PTCR_SYN)
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IMX_AUDMUX_V2_PDCR_RXDSEL(4)
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>;
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};
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aud5 {
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fsl,audmux-port = <4>;
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fsl,port-config = <
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IMX_AUDMUX_V2_PTCR_SYN
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IMX_AUDMUX_V2_PDCR_RXDSEL(1)>;
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};
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};
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&can1 {
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@ -332,7 +352,7 @@
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "okay";
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codec: sgtl5000@a {
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sgtl5000: audio-codec@a {
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compatible = "fsl,sgtl5000";
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reg = <0x0a>;
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clocks = <&clks IMX6QDL_CLK_CKO>;
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@ -476,6 +496,9 @@
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MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
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MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
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MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
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MX6QDL_PAD_EIM_D25__AUD5_RXC 0x130b0
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MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
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MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x130b0
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>;
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};
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