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tg3: Add flag to disable 1G Half Duplex advertisement
Some link partners have issues if the non-standard 1G half duplex is advertised. This patch adds support for an nvram setting to disable the advertisement. Signed-off-by: Nithin Nayak Sujir <nsujir@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -4403,9 +4403,12 @@ static void tg3_phy_copper_begin(struct tg3 *tp)
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if (tg3_flag(tp, WOL_SPEED_100MB))
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adv |= ADVERTISED_100baseT_Half |
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ADVERTISED_100baseT_Full;
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if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK)
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adv |= ADVERTISED_1000baseT_Half |
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ADVERTISED_1000baseT_Full;
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if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) {
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if (!(tp->phy_flags &
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TG3_PHYFLG_DISABLE_1G_HD_ADV))
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adv |= ADVERTISED_1000baseT_Half;
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adv |= ADVERTISED_1000baseT_Full;
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}
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fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
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} else {
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@ -14917,7 +14920,8 @@ static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
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tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
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if (val == NIC_SRAM_DATA_SIG_MAGIC) {
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u32 nic_cfg, led_cfg;
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u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
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u32 cfg2 = 0, cfg4 = 0, cfg5 = 0;
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u32 nic_phy_id, ver, eeprom_phy_id;
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int eeprom_phy_serdes = 0;
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tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
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@ -14934,6 +14938,11 @@ static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
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if (tg3_asic_rev(tp) == ASIC_REV_5785)
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tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
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if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
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tg3_asic_rev(tp) == ASIC_REV_5719 ||
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tg3_asic_rev(tp) == ASIC_REV_5720)
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tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5);
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if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
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NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
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eeprom_phy_serdes = 1;
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@ -15086,6 +15095,9 @@ static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
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tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
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if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
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tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
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if (cfg5 & NIC_SRAM_DISABLE_1G_HALF_ADV)
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tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV;
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}
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done:
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if (tg3_flag(tp, WOL_CAP))
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@ -15181,9 +15193,11 @@ static void tg3_phy_init_link_config(struct tg3 *tp)
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{
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u32 adv = ADVERTISED_Autoneg;
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if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
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adv |= ADVERTISED_1000baseT_Half |
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ADVERTISED_1000baseT_Full;
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if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
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if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV))
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adv |= ADVERTISED_1000baseT_Half;
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adv |= ADVERTISED_1000baseT_Full;
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}
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if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
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adv |= ADVERTISED_100baseT_Half |
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@ -2226,6 +2226,9 @@
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#define NIC_SRAM_CPMUSTAT_SIG 0x0000362c
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#define NIC_SRAM_CPMUSTAT_SIG_MSK 0x0000ffff
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#define NIC_SRAM_DATA_CFG_5 0x00000e0c
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#define NIC_SRAM_DISABLE_1G_HALF_ADV 0x00000002
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#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
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#define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000
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@ -3325,6 +3328,7 @@ struct tg3 {
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#define TG3_PHYFLG_1G_ON_VAUX_OK 0x00080000
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#define TG3_PHYFLG_KEEP_LINK_ON_PWRDN 0x00100000
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#define TG3_PHYFLG_MDIX_STATE 0x00200000
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#define TG3_PHYFLG_DISABLE_1G_HD_ADV 0x00400000
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u32 led_ctrl;
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u32 phy_otp;
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