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Drop remaining legacy platform data for cpsw and edma
With a non-critical clock fix for dm814x ethernet, we can update ti81xx for cpsw ethernet and edma to probe them with ti-sysc interconnect target module driver and device tree data. And we can drop the related remaining platform data for cpsw and edma. -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAl5xBPcRHHRvbnlAYXRv bWlkZS5jb20ACgkQG9Q+yVyrpXOsxhAAvtgT0UIuOSI+W+Pxrp2Vh2+Y9VIpJQ/V VCgiQfTxb99+4djiH63+/8h57V3StRCaE8wug3sFZoSqCnHQmrYWnTgGYKX0AsGv omOk+s7Rjw9aV9DsP1J4Vp4Am18dqL17NPiykht2jUMBenA6t9ltGP93huHau8CP KkF9hc1TC73JeS+kZZXgqXFsWVkWeMFkdYJBetdvaY6hljtnxuIx/3ZDNmX16Vio fB/En0xvCyjt7szLNwhdrvr/eteP4ZNywDrAI8SolvljqvaVf6VemMW/xeKRJOcE hpRmTrN5azh/GR7yIW+NIIauYM0AxuIAQ9NW9pBjRVAF6YZMeBdAVhXXxROC//pp qCzzP6h3QEtG9YlNqhxqTk4EAQ2WeHZCs6kMJHOh2vLn04my3f7o6x7djFP2W9Mk ZKoOMIsMknvPskW7QCb2epmepxW2mFqZ/AOLo3zq7j5KFR+cx9yPbwq9gzY52W94 bPHIIQAk6j+S9KHl+94YB9L6mN6LJRrMzmETBLfmrBimfZceESFvT9lWW4QC38Nr rPVPNkHVnuFb2+kv1g6StKq4drpo2b5KNNc6uVYzwJ+FgVoZoACt5hvEakwUO8Kt U/lNrh2pPtk/Hjet1Us5JypvMOZWF0vHC7DmFSER/2jYJ+KAVm3umxrsMbz/fg2y kvlcO8poZjk= =EDSy -----END PGP SIGNATURE----- Merge tag 'omap-for-v5.7/ti-sysc-drop-pdata-ti81xx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/late Drop remaining legacy platform data for cpsw and edma With a non-critical clock fix for dm814x ethernet, we can update ti81xx for cpsw ethernet and edma to probe them with ti-sysc interconnect target module driver and device tree data. And we can drop the related remaining platform data for cpsw and edma. * tag 'omap-for-v5.7/ti-sysc-drop-pdata-ti81xx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP2+: Drop legacy platform data for ti81xx edma ARM: dts: Configure interconnect target module for ti816x edma ARM: dts: Configure interconnect target module for dm814x tptc3 ARM: dts: Configure interconnect target module for dm814x tptc2 ARM: dts: Configure interconnect target module for dm814x tptc1 ARM: dts: Configure interconnect target module for dm814x tptc0 ARM: dts: Configure interconnect target module for dm814x tpcc ARM: OMAP2+: Drop legacy platform data for dm814x cpsw ARM: dts: Configure interconnect target module for dm814x cpsw clk: ti: Fix dm814x clkctrl for ethernet Link: https://lore.kernel.org/r/pull-1584575307-189595@atomide.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
7c7642383a
@ -362,4 +362,18 @@
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#clock-cells = <2>;
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};
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};
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alwon_ethernet_cm: alwon_ethernet_cm@15d4 {
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compatible = "ti,omap4-cm";
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reg = <0x15d4 0x4>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x15d4 0x4>;
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alwon_ethernet_clkctrl: clk@0 {
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compatible = "ti,clkctrl";
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reg = <0 0x4>;
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#clock-cells = <2>;
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};
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};
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};
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@ -4,6 +4,8 @@
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* kind, whether express or implied.
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*/
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#include <dt-bindings/bus/ti-sysc.h>
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#include <dt-bindings/clock/dm814.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/dm814x.h>
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@ -519,53 +521,123 @@
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reg = <0x47810000 0x1000>;
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};
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edma: edma@49000000 {
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compatible = "ti,edma3-tpcc";
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ti,hwmods = "tpcc";
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reg = <0x49000000 0x10000>;
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reg-names = "edma3_cc";
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interrupts = <12 13 14>;
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interrupt-names = "edma3_ccint", "edma3_mperr",
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"edma3_ccerrint";
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dma-requests = <64>;
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#dma-cells = <2>;
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target-module@49000000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x49000000 0x4>;
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reg-names = "rev";
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clocks = <&alwon_clkctrl DM814_TPCC_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x49000000 0x10000>;
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ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
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<&edma_tptc2 3>, <&edma_tptc3 0>;
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edma: dma@0 {
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compatible = "ti,edma3-tpcc";
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reg = <0 0x10000>;
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reg-names = "edma3_cc";
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interrupts = <12 13 14>;
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interrupt-names = "edma3_ccint", "edma3_mperr",
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"edma3_ccerrint";
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dma-requests = <64>;
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#dma-cells = <2>;
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ti,edma-memcpy-channels = <20 21>;
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ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
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<&edma_tptc2 3>, <&edma_tptc3 0>;
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ti,edma-memcpy-channels = <20 21>;
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};
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};
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edma_tptc0: tptc@49800000 {
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compatible = "ti,edma3-tptc";
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ti,hwmods = "tptc0";
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reg = <0x49800000 0x100000>;
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interrupts = <112>;
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interrupt-names = "edma3_tcerrint";
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target-module@49800000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x49800000 0x4>,
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<0x49800010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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ti,sysc-midle = <SYSC_IDLE_FORCE>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_SMART>;
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clocks = <&alwon_clkctrl DM814_TPTC0_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x49800000 0x100000>;
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edma_tptc0: dma@0 {
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compatible = "ti,edma3-tptc";
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reg = <0 0x100000>;
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interrupts = <112>;
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interrupt-names = "edma3_tcerrint";
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};
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};
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edma_tptc1: tptc@49900000 {
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compatible = "ti,edma3-tptc";
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ti,hwmods = "tptc1";
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reg = <0x49900000 0x100000>;
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interrupts = <113>;
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interrupt-names = "edma3_tcerrint";
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target-module@49900000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x49900000 0x4>,
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<0x49900010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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ti,sysc-midle = <SYSC_IDLE_FORCE>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_SMART>;
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clocks = <&alwon_clkctrl DM814_TPTC1_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x49900000 0x100000>;
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edma_tptc1: dma@0 {
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compatible = "ti,edma3-tptc";
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reg = <0 0x100000>;
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interrupts = <113>;
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interrupt-names = "edma3_tcerrint";
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};
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};
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edma_tptc2: tptc@49a00000 {
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compatible = "ti,edma3-tptc";
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ti,hwmods = "tptc2";
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reg = <0x49a00000 0x100000>;
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interrupts = <114>;
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interrupt-names = "edma3_tcerrint";
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target-module@49a00000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x49a00000 0x4>,
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<0x49a00010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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ti,sysc-midle = <SYSC_IDLE_FORCE>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_SMART>;
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clocks = <&alwon_clkctrl DM814_TPTC2_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x49a00000 0x100000>;
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edma_tptc2: dma@0 {
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compatible = "ti,edma3-tptc";
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reg = <0 0x100000>;
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interrupts = <114>;
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interrupt-names = "edma3_tcerrint";
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};
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};
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edma_tptc3: tptc@49b00000 {
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compatible = "ti,edma3-tptc";
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ti,hwmods = "tptc3";
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reg = <0x49b00000 0x100000>;
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interrupts = <115>;
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interrupt-names = "edma3_tcerrint";
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target-module@49b00000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x49b00000 0x4>,
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<0x49b00010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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ti,sysc-midle = <SYSC_IDLE_FORCE>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_SMART>;
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clocks = <&alwon_clkctrl DM814_TPTC3_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x49b00000 0x100000>;
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edma_tptc3: dma@0 {
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compatible = "ti,edma3-tptc";
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reg = <0 0x100000>;
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interrupts = <115>;
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interrupt-names = "edma3_tcerrint";
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};
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};
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/* See TRM "Table 1-318. L4HS Instance Summary" */
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@ -574,57 +646,73 @@
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x4a000000 0x1b4040>;
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};
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/* REVISIT: Move to live under l4hs once driver is fixed */
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mac: ethernet@4a100000 {
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compatible = "ti,cpsw";
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ti,hwmods = "cpgmac0";
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clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
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clock-names = "fck", "cpts";
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cpdma_channels = <8>;
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ale_entries = <1024>;
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bd_ram_size = <0x2000>;
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mac_control = <0x20>;
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slaves = <2>;
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active_slave = <0>;
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cpts_clock_mult = <0x80000000>;
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cpts_clock_shift = <29>;
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reg = <0x4a100000 0x800
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0x4a100900 0x100>;
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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/*
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* c0_rx_thresh_pend
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* c0_rx_pend
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* c0_tx_pend
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* c0_misc_pend
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*/
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interrupts = <40 41 42 43>;
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ranges;
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syscon = <&scm_conf>;
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davinci_mdio: mdio@4a100800 {
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compatible = "ti,davinci_mdio";
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target-module@100000 {
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compatible = "ti,sysc-omap4-simple", "ti,sysc";
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reg = <0x100900 0x4>,
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<0x100908 0x4>,
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<0x100904 0x4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-mask = <0>;
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ti,sysc-midle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>;
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ti,syss-mask = <1>;
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clocks = <&alwon_ethernet_clkctrl DM814_ETHERNET_CPGMAC0_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "davinci_mdio";
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bus_freq = <1000000>;
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reg = <0x4a100800 0x100>;
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};
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#size-cells = <1>;
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ranges = <0 0x100000 0x8000>;
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cpsw_emac0: slave@4a100200 {
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/* Filled in by U-Boot */
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mac-address = [ 00 00 00 00 00 00 ];
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phys = <&phy_gmii_sel 1>;
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mac: ethernet@0 {
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compatible = "ti,cpsw";
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clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
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clock-names = "fck", "cpts";
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cpdma_channels = <8>;
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ale_entries = <1024>;
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bd_ram_size = <0x2000>;
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mac_control = <0x20>;
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slaves = <2>;
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active_slave = <0>;
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cpts_clock_mult = <0x80000000>;
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cpts_clock_shift = <29>;
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reg = <0 0x800>,
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<0x900 0x100>;
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#address-cells = <1>;
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#size-cells = <1>;
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/*
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* c0_rx_thresh_pend
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* c0_rx_pend
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* c0_tx_pend
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* c0_misc_pend
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*/
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interrupts = <40 41 42 43>;
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ranges = <0 0 0x8000>;
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syscon = <&scm_conf>;
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};
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davinci_mdio: mdio@800 {
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compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
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clocks = <&alwon_ethernet_clkctrl DM814_ETHERNET_CPGMAC0_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <0>;
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bus_freq = <1000000>;
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reg = <0x800 0x100>;
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};
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cpsw_emac1: slave@4a100300 {
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/* Filled in by U-Boot */
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mac-address = [ 00 00 00 00 00 00 ];
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phys = <&phy_gmii_sel 2>;
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cpsw_emac0: slave@200 {
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/* Filled in by U-Boot */
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mac-address = [ 00 00 00 00 00 00 ];
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phys = <&phy_gmii_sel 1>;
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};
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cpsw_emac1: slave@300 {
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/* Filled in by U-Boot */
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mac-address = [ 00 00 00 00 00 00 ];
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phys = <&phy_gmii_sel 2>;
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};
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};
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};
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};
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@ -4,6 +4,8 @@
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* kind, whether express or implied.
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*/
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#include <dt-bindings/bus/ti-sysc.h>
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#include <dt-bindings/clock/dm816.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/omap.h>
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@ -138,13 +140,123 @@
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};
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};
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edma: edma@49000000 {
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compatible = "ti,edma3";
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ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3";
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reg = <0x49000000 0x10000>,
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<0x44e10f90 0x40>;
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interrupts = <12 13 14>;
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#dma-cells = <1>;
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target-module@49000000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x49000000 0x4>;
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reg-names = "rev";
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clocks = <&alwon_clkctrl DM816_TPCC_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x49000000 0x10000>;
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edma: dma@0 {
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compatible = "ti,edma3-tpcc";
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reg = <0 0x10000>;
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reg-names = "edma3_cc";
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interrupts = <12 13 14>;
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interrupt-names = "edma3_ccint", "edma3_mperr",
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"edma3_ccerrint";
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dma-requests = <64>;
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#dma-cells = <2>;
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ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
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<&edma_tptc2 3>, <&edma_tptc3 0>;
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ti,edma-memcpy-channels = <20 21>;
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};
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||||
};
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target-module@49800000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x49800000 0x4>,
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<0x49800010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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ti,sysc-midle = <SYSC_IDLE_FORCE>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_SMART>;
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clocks = <&alwon_clkctrl DM816_TPTC0_CLKCTRL 0>;
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clock-names = "fck";
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||||
#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x49800000 0x100000>;
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edma_tptc0: dma@0 {
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compatible = "ti,edma3-tptc";
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reg = <0 0x100000>;
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||||
interrupts = <112>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
};
|
||||
};
|
||||
|
||||
target-module@49900000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x49900000 0x4>,
|
||||
<0x49900010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&alwon_clkctrl DM816_TPTC1_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x49900000 0x100000>;
|
||||
|
||||
edma_tptc1: dma@0 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
reg = <0 0x100000>;
|
||||
interrupts = <113>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
};
|
||||
};
|
||||
|
||||
target-module@49a00000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x49a00000 0x4>,
|
||||
<0x49a00010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&alwon_clkctrl DM816_TPTC2_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x49a00000 0x100000>;
|
||||
|
||||
edma_tptc2: dma@0 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
reg = <0 0x100000>;
|
||||
interrupts = <114>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
};
|
||||
};
|
||||
|
||||
target-module@49b00000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x49b00000 0x4>,
|
||||
<0x49b00010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&alwon_clkctrl DM816_TPTC3_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x49b00000 0x100000>;
|
||||
|
||||
edma_tptc3: dma@0 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
reg = <0 0x100000>;
|
||||
interrupts = <115>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
};
|
||||
};
|
||||
|
||||
elm: elm@48080000 {
|
||||
@ -185,7 +297,7 @@
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <100>;
|
||||
dmas = <&edma 52>;
|
||||
dmas = <&edma 52 0>;
|
||||
dma-names = "rxtx";
|
||||
gpmc,num-cs = <6>;
|
||||
gpmc,num-waitpins = <2>;
|
||||
@ -202,7 +314,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <70>;
|
||||
dmas = <&edma 58 &edma 59>;
|
||||
dmas = <&edma 58 0 &edma 59 0>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
@ -213,7 +325,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <71>;
|
||||
dmas = <&edma 60 &edma 61>;
|
||||
dmas = <&edma 60 0 &edma 61 0>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
@ -311,10 +423,10 @@
|
||||
interrupts = <65>;
|
||||
ti,spi-num-cs = <4>;
|
||||
ti,hwmods = "mcspi1";
|
||||
dmas = <&edma 16 &edma 17
|
||||
&edma 18 &edma 19
|
||||
&edma 20 &edma 21
|
||||
&edma 22 &edma 23>;
|
||||
dmas = <&edma 16 0 &edma 17 0
|
||||
&edma 18 0 &edma 19 0
|
||||
&edma 20 0 &edma 21 0
|
||||
&edma 22 0 &edma 23 0>;
|
||||
dma-names = "tx0", "rx0", "tx1", "rx1",
|
||||
"tx2", "rx2", "tx3", "rx3";
|
||||
};
|
||||
@ -324,7 +436,7 @@
|
||||
reg = <0x48060000 0x11000>;
|
||||
ti,hwmods = "mmc1";
|
||||
interrupts = <64>;
|
||||
dmas = <&edma 24 &edma 25>;
|
||||
dmas = <&edma 24 0 &edma 25 0>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
@ -392,7 +504,7 @@
|
||||
reg = <0x48020000 0x2000>;
|
||||
clock-frequency = <48000000>;
|
||||
interrupts = <72>;
|
||||
dmas = <&edma 26 &edma 27>;
|
||||
dmas = <&edma 26 0 &edma 27 0>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
@ -402,7 +514,7 @@
|
||||
reg = <0x48022000 0x2000>;
|
||||
clock-frequency = <48000000>;
|
||||
interrupts = <73>;
|
||||
dmas = <&edma 28 &edma 29>;
|
||||
dmas = <&edma 28 0 &edma 29 0>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
@ -412,7 +524,7 @@
|
||||
reg = <0x48024000 0x2000>;
|
||||
clock-frequency = <48000000>;
|
||||
interrupts = <74>;
|
||||
dmas = <&edma 30 &edma 31>;
|
||||
dmas = <&edma 30 0 &edma 31 0>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
|
||||
@ -12,12 +12,12 @@
|
||||
|
||||
/* Compared to dm814x, dra62x has different offsets for Ethernet */
|
||||
&mac {
|
||||
reg = <0x4a100000 0x800
|
||||
0x4a101200 0x100>;
|
||||
reg = <0 0x800>,
|
||||
<0x1200 0x100>;
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
reg = <0x4a101000 0x100>;
|
||||
reg = <0x1000 0x100>;
|
||||
};
|
||||
|
||||
#include "dra62x-clocks.dtsi"
|
||||
|
||||
@ -129,13 +129,6 @@ static struct omap_hwmod dm81xx_alwon_l3_med_hwmod = {
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
static struct omap_hwmod dm81xx_alwon_l3_fast_hwmod = {
|
||||
.name = "l3_fast",
|
||||
.clkdm_name = "alwon_l3_fast_clkdm",
|
||||
.class = &l3_hwmod_class,
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
/*
|
||||
* L4 standard peripherals, see TRM table 1-12 for devices using this.
|
||||
* See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock.
|
||||
@ -867,62 +860,6 @@ static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = {
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
/* CPSW on dm814x */
|
||||
static struct omap_hwmod_class_sysconfig dm814x_cpgmac_sysc = {
|
||||
.rev_offs = 0x0,
|
||||
.sysc_offs = 0x8,
|
||||
.syss_offs = 0x4,
|
||||
.sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
|
||||
SYSS_HAS_RESET_STATUS,
|
||||
.idlemodes = SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
|
||||
MSTANDBY_NO,
|
||||
.sysc_fields = &omap_hwmod_sysc_type3,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class dm814x_cpgmac0_hwmod_class = {
|
||||
.name = "cpgmac0",
|
||||
.sysc = &dm814x_cpgmac_sysc,
|
||||
};
|
||||
|
||||
static struct omap_hwmod dm814x_cpgmac0_hwmod = {
|
||||
.name = "cpgmac0",
|
||||
.class = &dm814x_cpgmac0_hwmod_class,
|
||||
.clkdm_name = "alwon_ethernet_clkdm",
|
||||
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
|
||||
.main_clk = "cpsw_125mhz_gclk",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class dm814x_mdio_hwmod_class = {
|
||||
.name = "davinci_mdio",
|
||||
};
|
||||
|
||||
static struct omap_hwmod dm814x_mdio_hwmod = {
|
||||
.name = "davinci_mdio",
|
||||
.class = &dm814x_mdio_hwmod_class,
|
||||
.clkdm_name = "alwon_ethernet_clkdm",
|
||||
.main_clk = "cpsw_125mhz_gclk",
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if dm814x_l4_hs__cpgmac0 = {
|
||||
.master = &dm81xx_l4_hs_hwmod,
|
||||
.slave = &dm814x_cpgmac0_hwmod,
|
||||
.clk = "cpsw_125mhz_gclk",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if dm814x_cpgmac0__mdio = {
|
||||
.master = &dm814x_cpgmac0_hwmod,
|
||||
.slave = &dm814x_mdio_hwmod,
|
||||
.user = OCP_USER_MPU,
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
/* EMAC Ethernet */
|
||||
static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = {
|
||||
.rev_offs = 0x0,
|
||||
@ -1321,154 +1258,6 @@ static struct omap_hwmod_ocp_if dm81xx_l4_ls__spinbox = {
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class dm81xx_tpcc_hwmod_class = {
|
||||
.name = "tpcc",
|
||||
};
|
||||
|
||||
static struct omap_hwmod dm81xx_tpcc_hwmod = {
|
||||
.name = "tpcc",
|
||||
.class = &dm81xx_tpcc_hwmod_class,
|
||||
.clkdm_name = "alwon_l3s_clkdm",
|
||||
.main_clk = "sysclk4_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DM81XX_CM_ALWON_TPCC_CLKCTRL,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tpcc = {
|
||||
.master = &dm81xx_alwon_l3_fast_hwmod,
|
||||
.slave = &dm81xx_tpcc_hwmod,
|
||||
.clk = "sysclk4_ck",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class dm81xx_tptc0_hwmod_class = {
|
||||
.name = "tptc0",
|
||||
};
|
||||
|
||||
static struct omap_hwmod dm81xx_tptc0_hwmod = {
|
||||
.name = "tptc0",
|
||||
.class = &dm81xx_tptc0_hwmod_class,
|
||||
.clkdm_name = "alwon_l3s_clkdm",
|
||||
.main_clk = "sysclk4_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DM81XX_CM_ALWON_TPTC0_CLKCTRL,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc0 = {
|
||||
.master = &dm81xx_alwon_l3_fast_hwmod,
|
||||
.slave = &dm81xx_tptc0_hwmod,
|
||||
.clk = "sysclk4_ck",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if dm81xx_tptc0__alwon_l3_fast = {
|
||||
.master = &dm81xx_tptc0_hwmod,
|
||||
.slave = &dm81xx_alwon_l3_fast_hwmod,
|
||||
.clk = "sysclk4_ck",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class dm81xx_tptc1_hwmod_class = {
|
||||
.name = "tptc1",
|
||||
};
|
||||
|
||||
static struct omap_hwmod dm81xx_tptc1_hwmod = {
|
||||
.name = "tptc1",
|
||||
.class = &dm81xx_tptc1_hwmod_class,
|
||||
.clkdm_name = "alwon_l3s_clkdm",
|
||||
.main_clk = "sysclk4_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DM81XX_CM_ALWON_TPTC1_CLKCTRL,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc1 = {
|
||||
.master = &dm81xx_alwon_l3_fast_hwmod,
|
||||
.slave = &dm81xx_tptc1_hwmod,
|
||||
.clk = "sysclk4_ck",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if dm81xx_tptc1__alwon_l3_fast = {
|
||||
.master = &dm81xx_tptc1_hwmod,
|
||||
.slave = &dm81xx_alwon_l3_fast_hwmod,
|
||||
.clk = "sysclk4_ck",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class dm81xx_tptc2_hwmod_class = {
|
||||
.name = "tptc2",
|
||||
};
|
||||
|
||||
static struct omap_hwmod dm81xx_tptc2_hwmod = {
|
||||
.name = "tptc2",
|
||||
.class = &dm81xx_tptc2_hwmod_class,
|
||||
.clkdm_name = "alwon_l3s_clkdm",
|
||||
.main_clk = "sysclk4_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DM81XX_CM_ALWON_TPTC2_CLKCTRL,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc2 = {
|
||||
.master = &dm81xx_alwon_l3_fast_hwmod,
|
||||
.slave = &dm81xx_tptc2_hwmod,
|
||||
.clk = "sysclk4_ck",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if dm81xx_tptc2__alwon_l3_fast = {
|
||||
.master = &dm81xx_tptc2_hwmod,
|
||||
.slave = &dm81xx_alwon_l3_fast_hwmod,
|
||||
.clk = "sysclk4_ck",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class dm81xx_tptc3_hwmod_class = {
|
||||
.name = "tptc3",
|
||||
};
|
||||
|
||||
static struct omap_hwmod dm81xx_tptc3_hwmod = {
|
||||
.name = "tptc3",
|
||||
.class = &dm81xx_tptc3_hwmod_class,
|
||||
.clkdm_name = "alwon_l3s_clkdm",
|
||||
.main_clk = "sysclk4_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DM81XX_CM_ALWON_TPTC3_CLKCTRL,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc3 = {
|
||||
.master = &dm81xx_alwon_l3_fast_hwmod,
|
||||
.slave = &dm81xx_tptc3_hwmod,
|
||||
.clk = "sysclk4_ck",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = {
|
||||
.master = &dm81xx_tptc3_hwmod,
|
||||
.slave = &dm81xx_alwon_l3_fast_hwmod,
|
||||
.clk = "sysclk4_ck",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
/*
|
||||
* REVISIT: Test and enable the following once clocks work:
|
||||
* dm81xx_l4_ls__mailbox
|
||||
@ -1499,19 +1288,8 @@ static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
|
||||
&dm814x_l4_ls__mmc1,
|
||||
&dm814x_l4_ls__mmc2,
|
||||
&ti81xx_l4_ls__rtc,
|
||||
&dm81xx_alwon_l3_fast__tpcc,
|
||||
&dm81xx_alwon_l3_fast__tptc0,
|
||||
&dm81xx_alwon_l3_fast__tptc1,
|
||||
&dm81xx_alwon_l3_fast__tptc2,
|
||||
&dm81xx_alwon_l3_fast__tptc3,
|
||||
&dm81xx_tptc0__alwon_l3_fast,
|
||||
&dm81xx_tptc1__alwon_l3_fast,
|
||||
&dm81xx_tptc2__alwon_l3_fast,
|
||||
&dm81xx_tptc3__alwon_l3_fast,
|
||||
&dm814x_l4_ls__timer1,
|
||||
&dm814x_l4_ls__timer2,
|
||||
&dm814x_l4_hs__cpgmac0,
|
||||
&dm814x_cpgmac0__mdio,
|
||||
&dm81xx_alwon_l3_slow__gpmc,
|
||||
&dm814x_default_l3_slow__usbss,
|
||||
&dm814x_alwon_l3_med__mmc3,
|
||||
@ -1554,15 +1332,6 @@ static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
|
||||
&dm81xx_emac0__mdio,
|
||||
&dm816x_l4_hs__emac1,
|
||||
&dm81xx_l4_hs__sata,
|
||||
&dm81xx_alwon_l3_fast__tpcc,
|
||||
&dm81xx_alwon_l3_fast__tptc0,
|
||||
&dm81xx_alwon_l3_fast__tptc1,
|
||||
&dm81xx_alwon_l3_fast__tptc2,
|
||||
&dm81xx_alwon_l3_fast__tptc3,
|
||||
&dm81xx_tptc0__alwon_l3_fast,
|
||||
&dm81xx_tptc1__alwon_l3_fast,
|
||||
&dm81xx_tptc2__alwon_l3_fast,
|
||||
&dm81xx_tptc3__alwon_l3_fast,
|
||||
&dm81xx_alwon_l3_slow__gpmc,
|
||||
&dm816x_default_l3_slow__usbss,
|
||||
NULL,
|
||||
|
||||
@ -25,7 +25,6 @@ static const struct omap_clkctrl_reg_data dm814_alwon_clkctrl_regs[] __initconst
|
||||
{ DM814_WD_TIMER_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
|
||||
{ DM814_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
|
||||
{ DM814_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
|
||||
{ DM814_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
|
||||
{ DM814_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "mpu_ck" },
|
||||
{ DM814_RTC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
|
||||
{ DM814_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
|
||||
@ -39,9 +38,15 @@ static const struct omap_clkctrl_reg_data dm814_alwon_clkctrl_regs[] __initconst
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
static const struct
|
||||
omap_clkctrl_reg_data dm814_alwon_ethernet_clkctrl_regs[] __initconst = {
|
||||
{ 0, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
|
||||
};
|
||||
|
||||
const struct omap_clkctrl_data dm814_clkctrl_data[] __initconst = {
|
||||
{ 0x48180500, dm814_default_clkctrl_regs },
|
||||
{ 0x48181400, dm814_alwon_clkctrl_regs },
|
||||
{ 0x481815d4, dm814_alwon_ethernet_clkctrl_regs },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
|
||||
@ -34,4 +34,9 @@
|
||||
#define DM814_MMC2_CLKCTRL DM814_CLKCTRL_INDEX(0x220)
|
||||
#define DM814_MMC3_CLKCTRL DM814_CLKCTRL_INDEX(0x224)
|
||||
|
||||
/* alwon_ethernet clocks */
|
||||
#define DM814_ETHERNET_CLKCTRL_OFFSET 0x1d4
|
||||
#define DM814_ETHERNET_CLKCTRL_INDEX(offset) ((offset) - DM814_ETHERNET_CLKCTRL_OFFSET)
|
||||
#define DM814_ETHERNET_CPGMAC0_CLKCTRL DM814_ETHERNET_CLKCTRL_INDEX(0x1d4)
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user