mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-29 23:24:11 +08:00
clk: meson: meson8b: Make the video clock trees mutable
Switch from the "_ro" clock op variants to the mutable ones for all video clocks. This will allow the VPU driver to change the clocks as needed for the different video output modes. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20210713232510.3057750-6-martin.blumenstingl@googlemail.com
This commit is contained in:
Martin Blumenstingl
Jerome Brunet
parent
040e165bef
commit
7bcf9ef6b9
@ -207,7 +207,7 @@ static struct clk_regmap meson8b_hdmi_pll_dco = {
|
||||
.hw.init = &(struct clk_init_data){
|
||||
/* sometimes also called "HPLL" or "HPLL PLL" */
|
||||
.name = "hdmi_pll_dco",
|
||||
.ops = &meson_clk_pll_ro_ops,
|
||||
.ops = &meson_clk_pll_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&hdmi_pll_dco_in.hw
|
||||
},
|
||||
@ -224,7 +224,7 @@ static struct clk_regmap meson8b_hdmi_pll_lvds_out = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "hdmi_pll_lvds_out",
|
||||
.ops = &clk_regmap_divider_ro_ops,
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_hdmi_pll_dco.hw
|
||||
},
|
||||
@ -242,7 +242,7 @@ static struct clk_regmap meson8b_hdmi_pll_hdmi_out = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "hdmi_pll_hdmi_out",
|
||||
.ops = &clk_regmap_divider_ro_ops,
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_hdmi_pll_dco.hw
|
||||
},
|
||||
@ -1104,7 +1104,7 @@ static struct clk_regmap meson8b_vid_pll_lvds_en = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vid_pll_lvds_en",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_hdmi_pll_lvds_out.hw
|
||||
},
|
||||
@ -1121,7 +1121,7 @@ static struct clk_regmap meson8b_vid_pll_in_sel = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vid_pll_in_sel",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
/*
|
||||
* TODO: depending on the SoC there is also a second parent:
|
||||
* Meson8: unknown
|
||||
@ -1143,7 +1143,7 @@ static struct clk_regmap meson8b_vid_pll_in_en = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vid_pll_in_en",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vid_pll_in_sel.hw
|
||||
},
|
||||
@ -1160,7 +1160,7 @@ static struct clk_regmap meson8b_vid_pll_pre_div = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vid_pll_pre_div",
|
||||
.ops = &clk_regmap_divider_ro_ops,
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vid_pll_in_en.hw
|
||||
},
|
||||
@ -1177,7 +1177,7 @@ static struct clk_regmap meson8b_vid_pll_post_div = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vid_pll_post_div",
|
||||
.ops = &clk_regmap_divider_ro_ops,
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vid_pll_pre_div.hw
|
||||
},
|
||||
@ -1194,7 +1194,7 @@ static struct clk_regmap meson8b_vid_pll = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vid_pll",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
/* TODO: parent 0x2 is vid_pll_pre_div_mult7_div2 */
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vid_pll_pre_div.hw,
|
||||
@ -1213,7 +1213,7 @@ static struct clk_regmap meson8b_vid_pll_final_div = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vid_pll_final_div",
|
||||
.ops = &clk_regmap_divider_ro_ops,
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vid_pll.hw
|
||||
},
|
||||
@ -1240,7 +1240,7 @@ static struct clk_regmap meson8b_vclk_in_sel = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk_in_sel",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_hws = meson8b_vclk_mux_parent_hws,
|
||||
.num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
@ -1254,7 +1254,7 @@ static struct clk_regmap meson8b_vclk_in_en = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk_in_en",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk_in_sel.hw
|
||||
},
|
||||
@ -1270,7 +1270,7 @@ static struct clk_regmap meson8b_vclk_en = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk_en",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk_in_en.hw
|
||||
},
|
||||
@ -1286,7 +1286,7 @@ static struct clk_regmap meson8b_vclk_div1_gate = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk_div1_en",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk_en.hw
|
||||
},
|
||||
@ -1316,7 +1316,7 @@ static struct clk_regmap meson8b_vclk_div2_div_gate = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk_div2_en",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk_div2_div.hw
|
||||
},
|
||||
@ -1346,7 +1346,7 @@ static struct clk_regmap meson8b_vclk_div4_div_gate = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk_div4_en",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk_div4_div.hw
|
||||
},
|
||||
@ -1376,7 +1376,7 @@ static struct clk_regmap meson8b_vclk_div6_div_gate = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk_div6_en",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk_div6_div.hw
|
||||
},
|
||||
@ -1406,7 +1406,7 @@ static struct clk_regmap meson8b_vclk_div12_div_gate = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk_div12_en",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk_div12_div.hw
|
||||
},
|
||||
@ -1423,7 +1423,7 @@ static struct clk_regmap meson8b_vclk2_in_sel = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk2_in_sel",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_hws = meson8b_vclk_mux_parent_hws,
|
||||
.num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
@ -1437,7 +1437,7 @@ static struct clk_regmap meson8b_vclk2_clk_in_en = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk2_in_en",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk2_in_sel.hw
|
||||
},
|
||||
@ -1453,7 +1453,7 @@ static struct clk_regmap meson8b_vclk2_clk_en = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk2_en",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk2_clk_in_en.hw
|
||||
},
|
||||
@ -1469,7 +1469,7 @@ static struct clk_regmap meson8b_vclk2_div1_gate = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk2_div1_en",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk2_clk_en.hw
|
||||
},
|
||||
@ -1499,7 +1499,7 @@ static struct clk_regmap meson8b_vclk2_div2_div_gate = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk2_div2_en",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk2_div2_div.hw
|
||||
},
|
||||
@ -1529,7 +1529,7 @@ static struct clk_regmap meson8b_vclk2_div4_div_gate = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk2_div4_en",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk2_div4_div.hw
|
||||
},
|
||||
@ -1559,7 +1559,7 @@ static struct clk_regmap meson8b_vclk2_div6_div_gate = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk2_div6_en",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk2_div6_div.hw
|
||||
},
|
||||
@ -1589,7 +1589,7 @@ static struct clk_regmap meson8b_vclk2_div12_div_gate = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk2_div12_en",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk2_div12_div.hw
|
||||
},
|
||||
@ -1614,7 +1614,7 @@ static struct clk_regmap meson8b_cts_enct_sel = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cts_enct_sel",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_hws = meson8b_vclk_enc_mux_parent_hws,
|
||||
.num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1628,7 +1628,7 @@ static struct clk_regmap meson8b_cts_enct = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cts_enct",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_cts_enct_sel.hw
|
||||
},
|
||||
@ -1645,7 +1645,7 @@ static struct clk_regmap meson8b_cts_encp_sel = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cts_encp_sel",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_hws = meson8b_vclk_enc_mux_parent_hws,
|
||||
.num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1659,7 +1659,7 @@ static struct clk_regmap meson8b_cts_encp = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cts_encp",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_cts_encp_sel.hw
|
||||
},
|
||||
@ -1676,7 +1676,7 @@ static struct clk_regmap meson8b_cts_enci_sel = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cts_enci_sel",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_hws = meson8b_vclk_enc_mux_parent_hws,
|
||||
.num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1690,7 +1690,7 @@ static struct clk_regmap meson8b_cts_enci = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cts_enci",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_cts_enci_sel.hw
|
||||
},
|
||||
@ -1707,7 +1707,7 @@ static struct clk_regmap meson8b_hdmi_tx_pixel_sel = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "hdmi_tx_pixel_sel",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_hws = meson8b_vclk_enc_mux_parent_hws,
|
||||
.num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1721,7 +1721,7 @@ static struct clk_regmap meson8b_hdmi_tx_pixel = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "hdmi_tx_pixel",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_hdmi_tx_pixel_sel.hw
|
||||
},
|
||||
@ -1746,7 +1746,7 @@ static struct clk_regmap meson8b_cts_encl_sel = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cts_encl_sel",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_hws = meson8b_vclk2_enc_mux_parent_hws,
|
||||
.num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1760,7 +1760,7 @@ static struct clk_regmap meson8b_cts_encl = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cts_encl",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_cts_encl_sel.hw
|
||||
},
|
||||
@ -1777,7 +1777,7 @@ static struct clk_regmap meson8b_cts_vdac0_sel = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cts_vdac0_sel",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_hws = meson8b_vclk2_enc_mux_parent_hws,
|
||||
.num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1791,7 +1791,7 @@ static struct clk_regmap meson8b_cts_vdac0 = {
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cts_vdac0",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_cts_vdac0_sel.hw
|
||||
},
|
||||
|
||||
Loading…
Reference in New Issue
Block a user