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spi: microchip: pci1xxxx: Add suspend and resume support for PCI1XXXX SPI driver
Implement suspend, resume callbacks, store config at suspend and restore config at time of resume Signed-off-by: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com> Link: https://lore.kernel.org/r/20221006050514.115564-3-tharunkumar.pasumarthi@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -57,6 +57,9 @@
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#define SPI_CHIP_SEL_COUNT 7
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#define VENDOR_ID_MCHP 0x1055
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#define SPI_SUSPEND_CONFIG 0x101
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#define SPI_RESUME_CONFIG 0x303
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struct pci1xxxx_spi_internal {
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u8 hw_inst;
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bool spi_xfer_in_progress;
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@ -383,10 +386,85 @@ error:
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return ret;
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}
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static void store_restore_config(struct pci1xxxx_spi *spi_ptr,
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struct pci1xxxx_spi_internal *spi_sub_ptr,
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u8 inst, bool store)
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{
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u32 regval;
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if (store) {
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regval = readl(spi_ptr->reg_base +
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SPI_MST_CTL_REG_OFFSET(spi_sub_ptr->hw_inst));
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regval &= SPI_MST_CTL_DEVSEL_MASK;
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spi_sub_ptr->prev_val.dev_sel = (regval >> 25) & 7;
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regval = readl(spi_ptr->reg_base +
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SPI_PCI_CTRL_REG_OFFSET(spi_sub_ptr->hw_inst));
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regval &= SPI_MSI_VECTOR_SEL_MASK;
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spi_sub_ptr->prev_val.msi_vector_sel = (regval >> 4) & 1;
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} else {
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regval = readl(spi_ptr->reg_base + SPI_MST_CTL_REG_OFFSET(inst));
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regval &= ~SPI_MST_CTL_DEVSEL_MASK;
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regval |= (spi_sub_ptr->prev_val.dev_sel << 25);
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writel(regval,
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spi_ptr->reg_base + SPI_MST_CTL_REG_OFFSET(inst));
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writel((spi_sub_ptr->prev_val.msi_vector_sel << 4),
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spi_ptr->reg_base + SPI_PCI_CTRL_REG_OFFSET(inst));
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}
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}
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static int pci1xxxx_spi_resume(struct device *dev)
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{
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struct pci1xxxx_spi *spi_ptr = dev_get_drvdata(dev);
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struct pci1xxxx_spi_internal *spi_sub_ptr;
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u32 regval = SPI_RESUME_CONFIG;
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u8 iter;
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for (iter = 0; iter < spi_ptr->total_hw_instances; iter++) {
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spi_sub_ptr = spi_ptr->spi_int[iter];
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spi_master_resume(spi_sub_ptr->spi_host);
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writel(regval, spi_ptr->reg_base +
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SPI_MST_EVENT_MASK_REG_OFFSET(iter));
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/* Restore config at resume */
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store_restore_config(spi_ptr, spi_sub_ptr, iter, 0);
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}
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return 0;
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}
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static int pci1xxxx_spi_suspend(struct device *dev)
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{
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struct pci1xxxx_spi *spi_ptr = dev_get_drvdata(dev);
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struct pci1xxxx_spi_internal *spi_sub_ptr;
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u32 reg1 = SPI_SUSPEND_CONFIG;
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u8 iter;
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for (iter = 0; iter < spi_ptr->total_hw_instances; iter++) {
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spi_sub_ptr = spi_ptr->spi_int[iter];
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while (spi_sub_ptr->spi_xfer_in_progress)
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msleep(20);
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/* Store existing config before suspend */
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store_restore_config(spi_ptr, spi_sub_ptr, iter, 1);
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spi_master_suspend(spi_sub_ptr->spi_host);
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writel(reg1, spi_ptr->reg_base +
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SPI_MST_EVENT_MASK_REG_OFFSET(iter));
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}
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return 0;
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}
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static DEFINE_SIMPLE_DEV_PM_OPS(spi_pm_ops, pci1xxxx_spi_suspend,
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pci1xxxx_spi_resume);
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static struct pci_driver pci1xxxx_spi_driver = {
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.name = DRV_NAME,
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.id_table = pci1xxxx_spi_pci_id_table,
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.probe = pci1xxxx_spi_probe,
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.driver = {
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.pm = pm_sleep_ptr(&spi_pm_ops),
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},
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};
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module_pci_driver(pci1xxxx_spi_driver);
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