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ARM: dts: qcom: Add apq8064 CoreSight components

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Add initial set of CoreSight components found on Qualcomm apq8064 based
platforms, including the IFC6410 board.

Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This commit is contained in:
Ivan T. Ivanov 2017-01-11 17:50:21 +02:00 committed by Andy Gross
parent d724d6ba86
commit 7a5c275fd8
1 changed files with 186 additions and 4 deletions
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190
arch/arm/boot/dts/qcom-apq8064.dtsi
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@ -4,6 +4,7 @@
#include <dt-bindings/clock/qcom,gcc-msm8960.h>
#include <dt-bindings/reset/qcom,gcc-msm8960.h>
#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/soc/qcom,gsbi.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@ -32,7 +33,7 @@
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
CPU0: cpu@0 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
@ -43,7 +44,7 @@
cpu-idle-states = <&CPU_SPC>;
};
cpu@1 {
CPU1: cpu@1 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
@ -54,7 +55,7 @@
cpu-idle-states = <&CPU_SPC>;
};
cpu@2 {
CPU2: cpu@2 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
@ -65,7 +66,7 @@
cpu-idle-states = <&CPU_SPC>;
};
cpu@3 {
CPU3: cpu@3 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
@ -1512,6 +1513,187 @@
};
};
};
etb@1a01000 {
compatible = "coresight-etb10", "arm,primecell";
reg = <0x1a01000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
port {
etb_in: endpoint {
slave-mode;
remote-endpoint = <&replicator_out0>;
};
};
};
tpiu@1a03000 {
compatible = "arm,coresight-tpiu", "arm,primecell";
reg = <0x1a03000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
port {
tpiu_in: endpoint {
slave-mode;
remote-endpoint = <&replicator_out1>;
};
};
};
replicator {
compatible = "arm,coresight-replicator";
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
replicator_out0: endpoint {
remote-endpoint = <&etb_in>;
};
};
port@1 {
reg = <1>;
replicator_out1: endpoint {
remote-endpoint = <&tpiu_in>;
};
};
port@2 {
reg = <0>;
replicator_in: endpoint {
slave-mode;
remote-endpoint = <&funnel_out>;
};
};
};
};
funnel@1a04000 {
compatible = "arm,coresight-funnel", "arm,primecell";
reg = <0x1a04000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
ports {
#address-cells = <1>;
#size-cells = <0>;
/*
* Not described input ports:
* 2 - connected to STM component
* 3 - not-connected
* 6 - not-connected
* 7 - not-connected
*/
port@0 {
reg = <0>;
funnel_in0: endpoint {
slave-mode;
remote-endpoint = <&etm0_out>;
};
};
port@1 {
reg = <1>;
funnel_in1: endpoint {
slave-mode;
remote-endpoint = <&etm1_out>;
};
};
port@4 {
reg = <4>;
funnel_in4: endpoint {
slave-mode;
remote-endpoint = <&etm2_out>;
};
};
port@5 {
reg = <5>;
funnel_in5: endpoint {
slave-mode;
remote-endpoint = <&etm3_out>;
};
};
port@8 {
reg = <0>;
funnel_out: endpoint {
remote-endpoint = <&replicator_in>;
};
};
};
};
etm@1a1c000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0x1a1c000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU0>;
port {
etm0_out: endpoint {
remote-endpoint = <&funnel_in0>;
};
};
};
etm@1a1d000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0x1a1d000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU1>;
port {
etm1_out: endpoint {
remote-endpoint = <&funnel_in1>;
};
};
};
etm@1a1e000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0x1a1e000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU2>;
port {
etm2_out: endpoint {
remote-endpoint = <&funnel_in4>;
};
};
};
etm@1a1f000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0x1a1f000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU3>;
port {
etm3_out: endpoint {
remote-endpoint = <&funnel_in5>;
};
};
};
};
};
#include "qcom-apq8064-pins.dtsi"