ARM: ux500: de-globalize <mach/id.h>

This removes the file <mach/id.h> from the global kernel include
scope, making it a pure mach-ux500 detail. All ASIC specifics
needed by drivers shall henceforth be passed from either platform
data or the device tree.

Cc: Rafael J. Wysocki <rjw@sisk.pl>
Acked-by: Samuel Ortiz <sameo@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij 2012-09-19 19:31:19 +02:00
parent b5bbd41784
commit 7a4f26097d
12 changed files with 19 additions and 18 deletions

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@ -13,6 +13,7 @@
#include <mach/hardware.h> #include <mach/hardware.h>
#include "board-mop500.h" #include "board-mop500.h"
#include "id.h"
enum mop500_uib { enum mop500_uib {
STUIB, STUIB,

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@ -10,7 +10,8 @@
#include <asm/cacheflush.h> #include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h> #include <asm/hardware/cache-l2x0.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/id.h>
#include "id.h"
static void __iomem *l2x0_base; static void __iomem *l2x0_base;

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@ -37,7 +37,9 @@
#include "devices-db8500.h" #include "devices-db8500.h"
#include "ste-dma40-db8500.h" #include "ste-dma40-db8500.h"
#include "board-mop500.h" #include "board-mop500.h"
#include "id.h"
/* minimum static i/o mapping required to boot U8500 platforms */ /* minimum static i/o mapping required to boot U8500 platforms */
static struct map_desc u8500_uart_io_desc[] __initdata = { static struct map_desc u8500_uart_io_desc[] __initdata = {

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@ -27,6 +27,7 @@
#include <mach/devices.h> #include <mach/devices.h>
#include "board-mop500.h" #include "board-mop500.h"
#include "id.h"
void __iomem *_PRCMU_BASE; void __iomem *_PRCMU_BASE;

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@ -17,6 +17,8 @@
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/setup.h> #include <mach/setup.h>
#include "id.h"
struct dbx500_asic_id dbx500_id; struct dbx500_asic_id dbx500_id;
static unsigned int ux500_read_asicid(phys_addr_t addr) static unsigned int ux500_read_asicid(phys_addr_t addr)

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@ -39,7 +39,6 @@
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
#include <mach/id.h>
extern void __iomem *_PRCMU_BASE; extern void __iomem *_PRCMU_BASE;
#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)

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@ -21,9 +21,12 @@
#include <asm/hardware/gic.h> #include <asm/hardware/gic.h>
#include <asm/smp_plat.h> #include <asm/smp_plat.h>
#include <asm/smp_scu.h> #include <asm/smp_scu.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/setup.h> #include <mach/setup.h>
#include "id.h"
/* This is called from headsmp.S to wakeup the secondary core */ /* This is called from headsmp.S to wakeup the secondary core */
extern void u8500_secondary_startup(void); extern void u8500_secondary_startup(void);

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@ -17,6 +17,8 @@
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/irqs.h> #include <mach/irqs.h>
#include "id.h"
#ifdef CONFIG_HAVE_ARM_TWD #ifdef CONFIG_HAVE_ARM_TWD
static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer, static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer,
U8500_TWD_BASE, IRQ_LOCALTIMER); U8500_TWD_BASE, IRQ_LOCALTIMER);

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@ -167,9 +167,6 @@ static struct platform_driver db8500_cpufreq_plat_driver = {
static int __init db8500_cpufreq_register(void) static int __init db8500_cpufreq_register(void)
{ {
if (!cpu_is_u8500_family())
return -ENODEV;
pr_info("cpufreq for DB8500 started\n"); pr_info("cpufreq for DB8500 started\n");
return platform_driver_register(&db8500_cpufreq_plat_driver); return platform_driver_register(&db8500_cpufreq_plat_driver);
} }

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@ -36,7 +36,6 @@
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/irqs.h> #include <mach/irqs.h>
#include <mach/db8500-regs.h> #include <mach/db8500-regs.h>
#include <mach/id.h>
#include "dbx500-prcmu-regs.h" #include "dbx500-prcmu-regs.h"
/* Offset for the firmware version within the TCPM */ /* Offset for the firmware version within the TCPM */
@ -216,10 +215,8 @@
#define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1) #define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1)
#define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2) #define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2)
#define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3) #define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3)
#define PRCMU_I2C_WRITE(slave) \ #define PRCMU_I2C_WRITE(slave) (((slave) << 1) | BIT(6))
(((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0)) #define PRCMU_I2C_READ(slave) (((slave) << 1) | BIT(0) | BIT(6))
#define PRCMU_I2C_READ(slave) \
(((slave) << 1) | BIT(0) | (cpu_is_u8500v2() ? BIT(6) : 0))
#define PRCMU_I2C_STOP_EN BIT(3) #define PRCMU_I2C_STOP_EN BIT(3)
/* Mailbox 5 ACKs */ /* Mailbox 5 ACKs */
@ -1049,12 +1046,13 @@ int db8500_prcmu_get_ddr_opp(void)
* *
* This function sets the operating point of the DDR. * This function sets the operating point of the DDR.
*/ */
static bool enable_set_ddr_opp;
int db8500_prcmu_set_ddr_opp(u8 opp) int db8500_prcmu_set_ddr_opp(u8 opp)
{ {
if (opp < DDR_100_OPP || opp > DDR_25_OPP) if (opp < DDR_100_OPP || opp > DDR_25_OPP)
return -EINVAL; return -EINVAL;
/* Changing the DDR OPP can hang the hardware pre-v21 */ /* Changing the DDR OPP can hang the hardware pre-v21 */
if (cpu_is_u8500v20_or_later() && !cpu_is_u8500v20()) if (enable_set_ddr_opp)
writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW); writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW);
return 0; return 0;
@ -2790,6 +2788,7 @@ void __init db8500_prcmu_early_init(void)
pr_err("prcmu: Unsupported chip version\n"); pr_err("prcmu: Unsupported chip version\n");
BUG(); BUG();
} }
tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE);
spin_lock_init(&mb0_transfer.lock); spin_lock_init(&mb0_transfer.lock);
spin_lock_init(&mb0_transfer.dbb_irqs_lock); spin_lock_init(&mb0_transfer.dbb_irqs_lock);
@ -3104,9 +3103,6 @@ static int db8500_prcmu_probe(struct platform_device *pdev)
struct device_node *np = pdev->dev.of_node; struct device_node *np = pdev->dev.of_node;
int irq = 0, err = 0, i; int irq = 0, err = 0, i;
if (ux500_is_svp())
return -ENODEV;
init_prcm_registers(); init_prcm_registers();
/* Clean up the mailbox interrupts after pre-kernel code. */ /* Clean up the mailbox interrupts after pre-kernel code. */
@ -3135,8 +3131,7 @@ static int db8500_prcmu_probe(struct platform_device *pdev)
} }
} }
if (cpu_is_u8500v20_or_later()) prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
db8500_prcmu_update_cpufreq(); db8500_prcmu_update_cpufreq();

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@ -218,8 +218,6 @@ enum ddr_pwrst {
#if defined(CONFIG_UX500_SOC_DB8500) #if defined(CONFIG_UX500_SOC_DB8500)
#include <mach/id.h>
static inline void __init prcmu_early_init(void) static inline void __init prcmu_early_init(void)
{ {
return db8500_prcmu_early_init(); return db8500_prcmu_early_init();