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ARM: ux500: de-globalize <mach/id.h>
This removes the file <mach/id.h> from the global kernel include scope, making it a pure mach-ux500 detail. All ASIC specifics needed by drivers shall henceforth be passed from either platform data or the device tree. Cc: Rafael J. Wysocki <rjw@sisk.pl> Acked-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -13,6 +13,7 @@
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#include <mach/hardware.h>
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#include <mach/hardware.h>
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#include "board-mop500.h"
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#include "board-mop500.h"
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#include "id.h"
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enum mop500_uib {
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enum mop500_uib {
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STUIB,
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STUIB,
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@ -10,7 +10,8 @@
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#include <asm/cacheflush.h>
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#include <asm/cacheflush.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <mach/hardware.h>
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#include <mach/hardware.h>
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#include <mach/id.h>
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#include "id.h"
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static void __iomem *l2x0_base;
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static void __iomem *l2x0_base;
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@ -37,7 +37,9 @@
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#include "devices-db8500.h"
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#include "devices-db8500.h"
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#include "ste-dma40-db8500.h"
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#include "ste-dma40-db8500.h"
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#include "board-mop500.h"
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#include "board-mop500.h"
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#include "id.h"
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/* minimum static i/o mapping required to boot U8500 platforms */
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/* minimum static i/o mapping required to boot U8500 platforms */
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static struct map_desc u8500_uart_io_desc[] __initdata = {
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static struct map_desc u8500_uart_io_desc[] __initdata = {
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@ -27,6 +27,7 @@
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#include <mach/devices.h>
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#include <mach/devices.h>
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#include "board-mop500.h"
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#include "board-mop500.h"
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#include "id.h"
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void __iomem *_PRCMU_BASE;
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void __iomem *_PRCMU_BASE;
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@ -17,6 +17,8 @@
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#include <mach/hardware.h>
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#include <mach/hardware.h>
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#include <mach/setup.h>
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#include <mach/setup.h>
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#include "id.h"
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struct dbx500_asic_id dbx500_id;
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struct dbx500_asic_id dbx500_id;
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static unsigned int ux500_read_asicid(phys_addr_t addr)
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static unsigned int ux500_read_asicid(phys_addr_t addr)
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@ -39,7 +39,6 @@
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLY__
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#include <mach/id.h>
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extern void __iomem *_PRCMU_BASE;
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extern void __iomem *_PRCMU_BASE;
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#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
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#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
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@ -21,9 +21,12 @@
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#include <asm/hardware/gic.h>
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#include <asm/hardware/gic.h>
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#include <asm/smp_plat.h>
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#include <asm/smp_plat.h>
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#include <asm/smp_scu.h>
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#include <asm/smp_scu.h>
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#include <mach/hardware.h>
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#include <mach/hardware.h>
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#include <mach/setup.h>
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#include <mach/setup.h>
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#include "id.h"
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/* This is called from headsmp.S to wakeup the secondary core */
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/* This is called from headsmp.S to wakeup the secondary core */
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extern void u8500_secondary_startup(void);
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extern void u8500_secondary_startup(void);
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@ -17,6 +17,8 @@
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#include <mach/hardware.h>
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#include <mach/hardware.h>
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#include <mach/irqs.h>
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#include <mach/irqs.h>
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#include "id.h"
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#ifdef CONFIG_HAVE_ARM_TWD
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#ifdef CONFIG_HAVE_ARM_TWD
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static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer,
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static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer,
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U8500_TWD_BASE, IRQ_LOCALTIMER);
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U8500_TWD_BASE, IRQ_LOCALTIMER);
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@ -167,9 +167,6 @@ static struct platform_driver db8500_cpufreq_plat_driver = {
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static int __init db8500_cpufreq_register(void)
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static int __init db8500_cpufreq_register(void)
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{
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{
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if (!cpu_is_u8500_family())
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return -ENODEV;
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pr_info("cpufreq for DB8500 started\n");
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pr_info("cpufreq for DB8500 started\n");
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return platform_driver_register(&db8500_cpufreq_plat_driver);
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return platform_driver_register(&db8500_cpufreq_plat_driver);
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}
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}
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@ -36,7 +36,6 @@
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#include <mach/hardware.h>
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#include <mach/hardware.h>
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#include <mach/irqs.h>
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#include <mach/irqs.h>
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#include <mach/db8500-regs.h>
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#include <mach/db8500-regs.h>
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#include <mach/id.h>
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#include "dbx500-prcmu-regs.h"
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#include "dbx500-prcmu-regs.h"
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/* Offset for the firmware version within the TCPM */
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/* Offset for the firmware version within the TCPM */
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@ -216,10 +215,8 @@
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#define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1)
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#define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1)
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#define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2)
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#define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2)
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#define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3)
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#define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3)
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#define PRCMU_I2C_WRITE(slave) \
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#define PRCMU_I2C_WRITE(slave) (((slave) << 1) | BIT(6))
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(((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0))
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#define PRCMU_I2C_READ(slave) (((slave) << 1) | BIT(0) | BIT(6))
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#define PRCMU_I2C_READ(slave) \
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(((slave) << 1) | BIT(0) | (cpu_is_u8500v2() ? BIT(6) : 0))
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#define PRCMU_I2C_STOP_EN BIT(3)
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#define PRCMU_I2C_STOP_EN BIT(3)
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/* Mailbox 5 ACKs */
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/* Mailbox 5 ACKs */
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@ -1049,12 +1046,13 @@ int db8500_prcmu_get_ddr_opp(void)
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*
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*
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* This function sets the operating point of the DDR.
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* This function sets the operating point of the DDR.
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*/
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*/
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static bool enable_set_ddr_opp;
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int db8500_prcmu_set_ddr_opp(u8 opp)
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int db8500_prcmu_set_ddr_opp(u8 opp)
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{
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{
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if (opp < DDR_100_OPP || opp > DDR_25_OPP)
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if (opp < DDR_100_OPP || opp > DDR_25_OPP)
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return -EINVAL;
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return -EINVAL;
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/* Changing the DDR OPP can hang the hardware pre-v21 */
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/* Changing the DDR OPP can hang the hardware pre-v21 */
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if (cpu_is_u8500v20_or_later() && !cpu_is_u8500v20())
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if (enable_set_ddr_opp)
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writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW);
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writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW);
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return 0;
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return 0;
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@ -2790,6 +2788,7 @@ void __init db8500_prcmu_early_init(void)
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pr_err("prcmu: Unsupported chip version\n");
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pr_err("prcmu: Unsupported chip version\n");
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BUG();
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BUG();
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}
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}
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tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE);
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spin_lock_init(&mb0_transfer.lock);
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spin_lock_init(&mb0_transfer.lock);
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spin_lock_init(&mb0_transfer.dbb_irqs_lock);
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spin_lock_init(&mb0_transfer.dbb_irqs_lock);
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@ -3104,9 +3103,6 @@ static int db8500_prcmu_probe(struct platform_device *pdev)
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struct device_node *np = pdev->dev.of_node;
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struct device_node *np = pdev->dev.of_node;
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int irq = 0, err = 0, i;
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int irq = 0, err = 0, i;
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if (ux500_is_svp())
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return -ENODEV;
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init_prcm_registers();
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init_prcm_registers();
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/* Clean up the mailbox interrupts after pre-kernel code. */
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/* Clean up the mailbox interrupts after pre-kernel code. */
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@ -3135,8 +3131,7 @@ static int db8500_prcmu_probe(struct platform_device *pdev)
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}
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}
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}
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}
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if (cpu_is_u8500v20_or_later())
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prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
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prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
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db8500_prcmu_update_cpufreq();
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db8500_prcmu_update_cpufreq();
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@ -218,8 +218,6 @@ enum ddr_pwrst {
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#if defined(CONFIG_UX500_SOC_DB8500)
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#if defined(CONFIG_UX500_SOC_DB8500)
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#include <mach/id.h>
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static inline void __init prcmu_early_init(void)
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static inline void __init prcmu_early_init(void)
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{
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{
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return db8500_prcmu_early_init();
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return db8500_prcmu_early_init();
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