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arm64/sysreg: Generate definitions for SCTLR_EL1
Automatically generate register definitions for SCTLR_EL1. No functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220503170233.507788-13-broonie@kernel.org [catalin.marinas@arm.com: fix the SCTLR_EL1 encoding] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -203,7 +203,6 @@
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#define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
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#define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
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#define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0)
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#define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
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#define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2)
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#define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
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@ -677,43 +676,6 @@
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(SCTLR_EL2_RES1 | ENDIAN_SET_EL2)
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/* SCTLR_EL1 specific flags. */
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#define SCTLR_EL1_EPAN (BIT(57))
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#define SCTLR_EL1_ATA0 (BIT(42))
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#define SCTLR_EL1_TCF_SHIFT 40
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#define SCTLR_EL1_TCF_NONE (UL(0x0))
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#define SCTLR_EL1_TCF_SYNC (UL(0x1))
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#define SCTLR_EL1_TCF_ASYNC (UL(0x2))
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#define SCTLR_EL1_TCF_ASYMM (UL(0x3))
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#define SCTLR_EL1_TCF_MASK (UL(0x3) << SCTLR_EL1_TCF_SHIFT)
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#define SCTLR_EL1_TCF0_SHIFT 38
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#define SCTLR_EL1_TCF0_NONE (UL(0x0))
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#define SCTLR_EL1_TCF0_SYNC (UL(0x1))
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#define SCTLR_EL1_TCF0_ASYNC (UL(0x2))
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#define SCTLR_EL1_TCF0_ASYMM (UL(0x3))
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#define SCTLR_EL1_TCF0_MASK (UL(0x3) << SCTLR_EL1_TCF0_SHIFT)
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#define SCTLR_EL1_BT1 (BIT(36))
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#define SCTLR_EL1_BT0 (BIT(35))
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#define SCTLR_EL1_LSMAOE (BIT(29))
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#define SCTLR_EL1_nTLSMD (BIT(28))
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#define SCTLR_EL1_UCI (BIT(26))
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#define SCTLR_EL1_E0E (BIT(24))
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#define SCTLR_EL1_SPAN (BIT(23))
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#define SCTLR_EL1_EIS (BIT(22))
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#define SCTLR_EL1_TSCXT (BIT(20))
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#define SCTLR_EL1_nTWE (BIT(18))
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#define SCTLR_EL1_nTWI (BIT(16))
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#define SCTLR_EL1_UCT (BIT(15))
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#define SCTLR_EL1_DZE (BIT(14))
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#define SCTLR_EL1_EOS (BIT(11))
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#define SCTLR_EL1_UMA (BIT(9))
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#define SCTLR_EL1_SED (BIT(8))
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#define SCTLR_EL1_ITD (BIT(7))
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#define SCTLR_EL1_CP15BEN (BIT(5))
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#define SCTLR_EL1_SA0 (BIT(4))
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#ifdef CONFIG_CPU_BIG_ENDIAN
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#define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE)
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#else
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@ -114,6 +114,77 @@ EndEnum
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Res0 3:0
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EndSysreg
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Sysreg SCTLR_EL1 3 0 1 0 0
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Field 63 TIDCP
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Field 62 SPINMASK
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Field 61 NMI
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Field 60 EnTP2
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Res0 59:58
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Field 57 EPAN
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Field 56 EnALS
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Field 55 EnAS0
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Field 54 EnASR
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Field 53 TME
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Field 52 TME0
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Field 51 TMT
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Field 50 TMT0
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Field 49:46 TWEDEL
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Field 45 TWEDEn
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Field 44 DSSBS
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Field 43 ATA
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Field 42 ATA0
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Enum 41:40 TCF
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0b00 NONE
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0b01 SYNC
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0b10 ASYNC
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0b11 ASYMM
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EndEnum
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Enum 39:38 TCF0
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0b00 NONE
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0b01 SYNC
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0b10 ASYNC
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0b11 ASYMM
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EndEnum
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Field 37 ITFSB
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Field 36 BT1
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Field 35 BT0
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Res0 34
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Field 33 MSCEn
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Field 32 CMOW
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Field 31 EnIA
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Field 30 EnIB
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Field 29 LSMAOE
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Field 28 nTLSMD
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Field 27 EnDA
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Field 26 UCI
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Field 25 EE
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Field 24 E0E
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Field 23 SPAN
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Field 22 EIS
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Field 21 IESB
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Field 20 TSCXT
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Field 19 WXN
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Field 18 nTWE
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Res0 17
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Field 16 nTWI
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Field 15 UCT
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Field 14 DZE
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Field 13 EnDB
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Field 12 I
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Field 11 EOS
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Field 10 EnRCTX
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Field 9 UMA
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Field 8 SED
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Field 7 ITD
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Field 6 nAA
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Field 5 CP15BEN
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Field 4 SA0
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Field 3 SA
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Field 2 C
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Field 1 A
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Field 0 M
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EndSysreg
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SysregFields TTBRx_EL1
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Field 63:48 ASID
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Field 47:1 BADDR
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