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ARM: SoC support for Tegra platforms for v4.5
Here's a single-SoC topic branch that we've staged separately. Mainly because it was hard to sort the branch contents in a way that fit our existing branches due to some refactorings. The code has been in -next for quite a while, but we staged it in arm-soc a bit late, which is why we've kept it separate from the other updates and are sending it separately here. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJWoqsGAAoJEIwa5zzehBx3/F4QAJo4FEU+KTOhUggDV+KPn9ZD Re1SAKTpKo9elMdDdTZZObHYPf+RXqun50C4pQiSVfyDm9syZaxtWjjZvshwsATq 178fNN+0C/7aenj8Zpq/NrLwBl1N51cSdc1ii3TcN/OA5XDgpmGJTdqMziDiXAkd Nt847qSEhIvAfOtcZR2drk2wBKGCTA/NpGU3HCryPAlO7RnAbJY4Ywj0bU01Lc9y bSJYh1SPaa1PdDCBJjtbk6L8iGl39K5oy0e6ehECEviLBVtWIL0zqh101XGbPVtv vtpVJ40NciiHknCBEiJkYiY9b7BNZYMeuwLarqk7TxyW4Vm5Rl5CFkEot0X/b70J XSxca6KGLzSgmCYDzJtLgtmyBUDoGqNwiPnNVIjrGIt9uOlWeHGb7TUKjBZaJr7G nXiKKU17zhb28hEo8JjIGcuFcOGlwlBhoOKhOYePiXX/iA03M8SEZg3XXyYMiaVz j9PcfOQptc7CyCAyiUQW36cZc1vQlnNxpiZstF0QsJ+Poe1kPlJIVpOarrfFdvh5 wJrS4L5YoIzb5robsNLNJ6XXiRnqvxgO6dEdA3RoI1bMaFsXVRCb03EoxVYqS4RF o+4h0KYQ8gPmAhA/ii/IDHps51TCCDOolAyWLfmYlqXu76IjOlC1LTYxi8RAGZNL xExyC0A3YDfONv6mx07R =LG3u -----END PGP SIGNATURE----- Merge tag 'armsoc-tegra' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC support for Tegra platforms from Olof Johansson: "Here's a single-SoC topic branch that we've staged separately. Mainly because it was hard to sort the branch contents in a way that fit our existing branches due to some refactorings. The code has been in -next for quite a while, but we staged it in arm-soc a bit late, which is why we've kept it separate from the other updates and are sending it separately here" * tag 'armsoc-tegra' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: arm64: tegra: Add NVIDIA Jetson TX1 Developer Kit support arm64: tegra: Add NVIDIA P2597 I/O board support arm64: tegra: Add NVIDIA Jetson TX1 support arm64: tegra: Add NVIDIA P2571 board support arm64: tegra: Add NVIDIA P2371 board support arm64: tegra: Add NVIDIA P2595 I/O board support arm64: tegra: Add NVIDIA P2530 main board support arm64: tegra: Add Tegra210 support arm64: tegra: Add NVIDIA Tegra132 Norrin support arm64: tegra: Add Tegra132 support ARM: tegra: select USB_ULPI from EHCI rather than platform ARM: tegra: Ensure entire dcache is flushed on entering LP0/1 amba: Hide TEGRA_AHB symbol soc/tegra: Add Tegra210 support soc/tegra: Provide per-SoC Kconfig symbols
This commit is contained in:
Linus Torvalds
commit
79d245327f
@ -13,57 +13,5 @@ menuconfig ARCH_TEGRA
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select ARCH_HAS_RESET_CONTROLLER
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select RESET_CONTROLLER
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select SOC_BUS
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select USB_ULPI if USB_PHY
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select USB_ULPI_VIEWPORT if USB_PHY
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help
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This enables support for NVIDIA Tegra based systems.
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if ARCH_TEGRA
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config ARCH_TEGRA_2x_SOC
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bool "Enable support for Tegra20 family"
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select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
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select ARM_ERRATA_720789
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select ARM_ERRATA_754327 if SMP
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select ARM_ERRATA_764369 if SMP
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select PINCTRL_TEGRA20
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select PL310_ERRATA_727915 if CACHE_L2X0
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select PL310_ERRATA_769419 if CACHE_L2X0
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select TEGRA_TIMER
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help
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Support for NVIDIA Tegra AP20 and T20 processors, based on the
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ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
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config ARCH_TEGRA_3x_SOC
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bool "Enable support for Tegra30 family"
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select ARM_ERRATA_754322
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select ARM_ERRATA_764369 if SMP
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select PINCTRL_TEGRA30
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select PL310_ERRATA_769419 if CACHE_L2X0
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select TEGRA_TIMER
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help
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Support for NVIDIA Tegra T30 processor family, based on the
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ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
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config ARCH_TEGRA_114_SOC
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bool "Enable support for Tegra114 family"
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select ARM_ERRATA_798181 if SMP
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select ARM_L1_CACHE_SHIFT_6
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select HAVE_ARM_ARCH_TIMER
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select PINCTRL_TEGRA114
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select TEGRA_TIMER
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help
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Support for NVIDIA Tegra T114 processor family, based on the
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ARM CortexA15MP CPU
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config ARCH_TEGRA_124_SOC
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bool "Enable support for Tegra124 family"
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select ARM_L1_CACHE_SHIFT_6
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select HAVE_ARM_ARCH_TIMER
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select PINCTRL_TEGRA124
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select TEGRA_TIMER
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help
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Support for NVIDIA Tegra T124 processor family, based on the
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ARM CortexA15MP CPU
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endif
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@ -231,8 +231,11 @@ ENDPROC(tegra20_cpu_is_resettable_soon)
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* tegra20_tear_down_core in IRAM
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*/
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ENTRY(tegra20_sleep_core_finish)
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mov r4, r0
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/* Flush, disable the L1 data cache and exit SMP */
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mov r0, #TEGRA_FLUSH_CACHE_ALL
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bl tegra_disable_clean_inv_dcache
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mov r0, r4
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mov32 r3, tegra_shut_off_mmu
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add r3, r3, r0
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@ -242,8 +242,11 @@ ENDPROC(tegra30_cpu_shutdown)
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* tegra30_tear_down_core in IRAM
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*/
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ENTRY(tegra30_sleep_core_finish)
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mov r4, r0
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/* Flush, disable the L1 data cache and exit SMP */
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mov r0, #TEGRA_FLUSH_CACHE_ALL
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bl tegra_disable_clean_inv_dcache
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mov r0, r4
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/*
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* Preload all the address literals that are needed for the
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@ -105,18 +105,6 @@ config ARCH_TEGRA
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help
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This enables support for the NVIDIA Tegra SoC family.
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config ARCH_TEGRA_132_SOC
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bool "NVIDIA Tegra132 SoC"
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depends on ARCH_TEGRA
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select PINCTRL_TEGRA124
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select USB_ULPI if USB_PHY
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select USB_ULPI_VIEWPORT if USB_PHY
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help
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Enable support for NVIDIA Tegra132 SoC, based on the Denver
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ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
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but contains an NVIDIA Denver CPU complex in place of
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Tegra124's "4+1" Cortex-A15 CPU complex.
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config ARCH_SPRD
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bool "Spreadtrum SoC platform"
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help
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@ -9,6 +9,7 @@ dts-dirs += freescale
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dts-dirs += hisilicon
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dts-dirs += marvell
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dts-dirs += mediatek
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dts-dirs += nvidia
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dts-dirs += qcom
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dts-dirs += renesas
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dts-dirs += rockchip
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7
arch/arm64/boot/dts/nvidia/Makefile
Normal file
7
arch/arm64/boot/dts/nvidia/Makefile
Normal file
@ -0,0 +1,7 @@
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dtb-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra132-norrin.dtb
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dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb
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dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb
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dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb
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always := $(dtb-y)
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clean-files := *.dtb
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1130
arch/arm64/boot/dts/nvidia/tegra132-norrin.dts
Normal file
1130
arch/arm64/boot/dts/nvidia/tegra132-norrin.dts
Normal file
File diff suppressed because it is too large
Load Diff
990
arch/arm64/boot/dts/nvidia/tegra132.dtsi
Normal file
990
arch/arm64/boot/dts/nvidia/tegra132.dtsi
Normal file
@ -0,0 +1,990 @@
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#include <dt-bindings/clock/tegra124-car.h>
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#include <dt-bindings/gpio/tegra-gpio.h>
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#include <dt-bindings/memory/tegra124-mc.h>
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#include <dt-bindings/pinctrl/pinctrl-tegra.h>
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#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "nvidia,tegra132", "nvidia,tegra124";
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interrupt-parent = <&lic>;
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#address-cells = <2>;
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#size-cells = <2>;
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pcie-controller@0,01003000 {
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compatible = "nvidia,tegra124-pcie";
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device_type = "pci";
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reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
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0x0 0x01003800 0x0 0x00000800 /* AFI registers */
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0x0 0x02000000 0x0 0x10000000>; /* configuration space */
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reg-names = "pads", "afi", "cs";
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
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interrupt-names = "intr", "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
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0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
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0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
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0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
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0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
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clocks = <&tegra_car TEGRA124_CLK_PCIE>,
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<&tegra_car TEGRA124_CLK_AFI>,
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<&tegra_car TEGRA124_CLK_PLL_E>,
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<&tegra_car TEGRA124_CLK_CML0>;
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clock-names = "pex", "afi", "pll_e", "cml";
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resets = <&tegra_car 70>,
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<&tegra_car 72>,
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<&tegra_car 74>;
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reset-names = "pex", "afi", "pcie_x";
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status = "disabled";
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phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
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phy-names = "pcie";
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pci@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
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reg = <0x000800 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <2>;
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};
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pci@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
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reg = <0x001000 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <1>;
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};
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};
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host1x@0,50000000 {
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compatible = "nvidia,tegra124-host1x", "simple-bus";
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reg = <0x0 0x50000000 0x0 0x00034000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
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<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
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clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
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clock-names = "host1x";
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resets = <&tegra_car 28>;
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reset-names = "host1x";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
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dc@0,54200000 {
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compatible = "nvidia,tegra124-dc";
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reg = <0x0 0x54200000 0x0 0x00040000>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_DISP1>,
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<&tegra_car TEGRA124_CLK_PLL_P>;
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clock-names = "dc", "parent";
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resets = <&tegra_car 27>;
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reset-names = "dc";
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iommus = <&mc TEGRA_SWGROUP_DC>;
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nvidia,head = <0>;
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};
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dc@0,54240000 {
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compatible = "nvidia,tegra124-dc";
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reg = <0x0 0x54240000 0x0 0x00040000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_DISP2>,
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<&tegra_car TEGRA124_CLK_PLL_P>;
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clock-names = "dc", "parent";
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resets = <&tegra_car 26>;
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reset-names = "dc";
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iommus = <&mc TEGRA_SWGROUP_DCB>;
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nvidia,head = <1>;
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};
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hdmi@0,54280000 {
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compatible = "nvidia,tegra124-hdmi";
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reg = <0x0 0x54280000 0x0 0x00040000>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_HDMI>,
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<&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
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clock-names = "hdmi", "parent";
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resets = <&tegra_car 51>;
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reset-names = "hdmi";
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status = "disabled";
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};
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sor@0,54540000 {
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compatible = "nvidia,tegra124-sor";
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reg = <0x0 0x54540000 0x0 0x00040000>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_SOR0>,
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<&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
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<&tegra_car TEGRA124_CLK_PLL_DP>,
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<&tegra_car TEGRA124_CLK_CLK_M>;
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clock-names = "sor", "parent", "dp", "safe";
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resets = <&tegra_car 182>;
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reset-names = "sor";
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status = "disabled";
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};
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dpaux: dpaux@0,545c0000 {
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compatible = "nvidia,tegra124-dpaux";
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reg = <0x0 0x545c0000 0x0 0x00040000>;
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interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
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<&tegra_car TEGRA124_CLK_PLL_DP>;
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clock-names = "dpaux", "parent";
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resets = <&tegra_car 181>;
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reset-names = "dpaux";
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status = "disabled";
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};
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};
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gic: interrupt-controller@0,50041000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x50041000 0x0 0x1000>,
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<0x0 0x50042000 0x0 0x2000>,
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<0x0 0x50044000 0x0 0x2000>,
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<0x0 0x50046000 0x0 0x2000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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interrupt-parent = <&gic>;
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};
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gpu@0,57000000 {
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compatible = "nvidia,gk20a";
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reg = <0x0 0x57000000 0x0 0x01000000>,
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<0x0 0x58000000 0x0 0x01000000>;
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interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "stall", "nonstall";
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clocks = <&tegra_car TEGRA124_CLK_GPU>,
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<&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
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clock-names = "gpu", "pwr";
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resets = <&tegra_car 184>;
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reset-names = "gpu";
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status = "disabled";
|
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};
|
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|
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lic: interrupt-controller@60004000 {
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compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
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reg = <0x0 0x60004000 0x0 0x100>,
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<0x0 0x60004100 0x0 0x100>,
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<0x0 0x60004200 0x0 0x100>,
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<0x0 0x60004300 0x0 0x100>,
|
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<0x0 0x60004400 0x0 0x100>;
|
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interrupt-controller;
|
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#interrupt-cells = <3>;
|
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interrupt-parent = <&gic>;
|
||||
};
|
||||
|
||||
timer@0,60005000 {
|
||||
compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
|
||||
reg = <0x0 0x60005000 0x0 0x400>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_TIMER>;
|
||||
clock-names = "timer";
|
||||
};
|
||||
|
||||
tegra_car: clock@0,60006000 {
|
||||
compatible = "nvidia,tegra132-car";
|
||||
reg = <0x0 0x60006000 0x0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
nvidia,external-memory-controller = <&emc>;
|
||||
};
|
||||
|
||||
flow-controller@0,60007000 {
|
||||
compatible = "nvidia,tegra124-flowctrl";
|
||||
reg = <0x0 0x60007000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
actmon@0,6000c800 {
|
||||
compatible = "nvidia,tegra124-actmon";
|
||||
reg = <0x0 0x6000c800 0x0 0x400>;
|
||||
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
|
||||
<&tegra_car TEGRA124_CLK_EMC>;
|
||||
clock-names = "actmon", "emc";
|
||||
resets = <&tegra_car 119>;
|
||||
reset-names = "actmon";
|
||||
};
|
||||
|
||||
gpio: gpio@0,6000d000 {
|
||||
compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
|
||||
reg = <0x0 0x6000d000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
apbdma: dma@0,60020000 {
|
||||
compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
|
||||
reg = <0x0 0x60020000 0x0 0x1400>;
|
||||
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
|
||||
clock-names = "dma";
|
||||
resets = <&tegra_car 34>;
|
||||
reset-names = "dma";
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
apbmisc@0,70000800 {
|
||||
compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
|
||||
reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
|
||||
<0x0 0x7000e864 0x0 0x04>; /* Strapping options */
|
||||
};
|
||||
|
||||
pinmux: pinmux@0,70000868 {
|
||||
compatible = "nvidia,tegra124-pinmux";
|
||||
reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
|
||||
<0x0 0x70003000 0x0 0x434>, /* Mux registers */
|
||||
<0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
|
||||
};
|
||||
|
||||
/*
|
||||
* There are two serial driver i.e. 8250 based simple serial
|
||||
* driver and APB DMA based serial driver for higher baudrate
|
||||
* and performace. To enable the 8250 based driver, the compatible
|
||||
* is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
|
||||
* the APB DMA based serial driver, the comptible is
|
||||
* "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
|
||||
*/
|
||||
uarta: serial@0,70006000 {
|
||||
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x0 0x70006000 0x0 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_UARTA>;
|
||||
clock-names = "serial";
|
||||
resets = <&tegra_car 6>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 8>, <&apbdma 8>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uartb: serial@0,70006040 {
|
||||
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x0 0x70006040 0x0 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_UARTB>;
|
||||
clock-names = "serial";
|
||||
resets = <&tegra_car 7>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 9>, <&apbdma 9>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uartc: serial@0,70006200 {
|
||||
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x0 0x70006200 0x0 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_UARTC>;
|
||||
clock-names = "serial";
|
||||
resets = <&tegra_car 55>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 10>, <&apbdma 10>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uartd: serial@0,70006300 {
|
||||
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x0 0x70006300 0x0 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_UARTD>;
|
||||
clock-names = "serial";
|
||||
resets = <&tegra_car 65>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 19>, <&apbdma 19>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm: pwm@0,7000a000 {
|
||||
compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
|
||||
reg = <0x0 0x7000a000 0x0 0x100>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_PWM>;
|
||||
clock-names = "pwm";
|
||||
resets = <&tegra_car 17>;
|
||||
reset-names = "pwm";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@0,7000c000 {
|
||||
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
|
||||
reg = <0x0 0x7000c000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_I2C1>;
|
||||
clock-names = "div-clk";
|
||||
resets = <&tegra_car 12>;
|
||||
reset-names = "i2c";
|
||||
dmas = <&apbdma 21>, <&apbdma 21>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@0,7000c400 {
|
||||
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
|
||||
reg = <0x0 0x7000c400 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_I2C2>;
|
||||
clock-names = "div-clk";
|
||||
resets = <&tegra_car 54>;
|
||||
reset-names = "i2c";
|
||||
dmas = <&apbdma 22>, <&apbdma 22>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@0,7000c500 {
|
||||
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
|
||||
reg = <0x0 0x7000c500 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_I2C3>;
|
||||
clock-names = "div-clk";
|
||||
resets = <&tegra_car 67>;
|
||||
reset-names = "i2c";
|
||||
dmas = <&apbdma 23>, <&apbdma 23>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@0,7000c700 {
|
||||
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
|
||||
reg = <0x0 0x7000c700 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_I2C4>;
|
||||
clock-names = "div-clk";
|
||||
resets = <&tegra_car 103>;
|
||||
reset-names = "i2c";
|
||||
dmas = <&apbdma 26>, <&apbdma 26>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@0,7000d000 {
|
||||
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
|
||||
reg = <0x0 0x7000d000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_I2C5>;
|
||||
clock-names = "div-clk";
|
||||
resets = <&tegra_car 47>;
|
||||
reset-names = "i2c";
|
||||
dmas = <&apbdma 24>, <&apbdma 24>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@0,7000d100 {
|
||||
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
|
||||
reg = <0x0 0x7000d100 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_I2C6>;
|
||||
clock-names = "div-clk";
|
||||
resets = <&tegra_car 166>;
|
||||
reset-names = "i2c";
|
||||
dmas = <&apbdma 30>, <&apbdma 30>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@0,7000d400 {
|
||||
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
|
||||
reg = <0x0 0x7000d400 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_SBC1>;
|
||||
clock-names = "spi";
|
||||
resets = <&tegra_car 41>;
|
||||
reset-names = "spi";
|
||||
dmas = <&apbdma 15>, <&apbdma 15>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@0,7000d600 {
|
||||
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
|
||||
reg = <0x0 0x7000d600 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_SBC2>;
|
||||
clock-names = "spi";
|
||||
resets = <&tegra_car 44>;
|
||||
reset-names = "spi";
|
||||
dmas = <&apbdma 16>, <&apbdma 16>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@0,7000d800 {
|
||||
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
|
||||
reg = <0x0 0x7000d800 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_SBC3>;
|
||||
clock-names = "spi";
|
||||
resets = <&tegra_car 46>;
|
||||
reset-names = "spi";
|
||||
dmas = <&apbdma 17>, <&apbdma 17>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@0,7000da00 {
|
||||
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
|
||||
reg = <0x0 0x7000da00 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_SBC4>;
|
||||
clock-names = "spi";
|
||||
resets = <&tegra_car 68>;
|
||||
reset-names = "spi";
|
||||
dmas = <&apbdma 18>, <&apbdma 18>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@0,7000dc00 {
|
||||
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
|
||||
reg = <0x0 0x7000dc00 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_SBC5>;
|
||||
clock-names = "spi";
|
||||
resets = <&tegra_car 104>;
|
||||
reset-names = "spi";
|
||||
dmas = <&apbdma 27>, <&apbdma 27>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@0,7000de00 {
|
||||
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
|
||||
reg = <0x0 0x7000de00 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_SBC6>;
|
||||
clock-names = "spi";
|
||||
resets = <&tegra_car 105>;
|
||||
reset-names = "spi";
|
||||
dmas = <&apbdma 28>, <&apbdma 28>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc@0,7000e000 {
|
||||
compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
|
||||
reg = <0x0 0x7000e000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_RTC>;
|
||||
clock-names = "rtc";
|
||||
};
|
||||
|
||||
pmc@0,7000e400 {
|
||||
compatible = "nvidia,tegra124-pmc";
|
||||
reg = <0x0 0x7000e400 0x0 0x400>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
};
|
||||
|
||||
fuse@0,7000f800 {
|
||||
compatible = "nvidia,tegra124-efuse";
|
||||
reg = <0x0 0x7000f800 0x0 0x400>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_FUSE>;
|
||||
clock-names = "fuse";
|
||||
resets = <&tegra_car 39>;
|
||||
reset-names = "fuse";
|
||||
};
|
||||
|
||||
mc: memory-controller@0,70019000 {
|
||||
compatible = "nvidia,tegra132-mc";
|
||||
reg = <0x0 0x70019000 0x0 0x1000>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_MC>;
|
||||
clock-names = "mc";
|
||||
|
||||
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
emc: emc@0,7001b000 {
|
||||
compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc";
|
||||
reg = <0x0 0x7001b000 0x0 0x1000>;
|
||||
|
||||
nvidia,memory-controller = <&mc>;
|
||||
};
|
||||
|
||||
sata@0,70020000 {
|
||||
compatible = "nvidia,tegra124-ahci";
|
||||
reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
|
||||
<0x0 0x70020000 0x0 0x7000>; /* SATA */
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_SATA>,
|
||||
<&tegra_car TEGRA124_CLK_SATA_OOB>,
|
||||
<&tegra_car TEGRA124_CLK_CML1>,
|
||||
<&tegra_car TEGRA124_CLK_PLL_E>;
|
||||
clock-names = "sata", "sata-oob", "cml1", "pll_e";
|
||||
resets = <&tegra_car 124>,
|
||||
<&tegra_car 123>,
|
||||
<&tegra_car 129>;
|
||||
reset-names = "sata", "sata-oob", "sata-cold";
|
||||
phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
|
||||
phy-names = "sata-phy";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hda@0,70030000 {
|
||||
compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda",
|
||||
"nvidia,tegra30-hda";
|
||||
reg = <0x0 0x70030000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_HDA>,
|
||||
<&tegra_car TEGRA124_CLK_HDA2HDMI>,
|
||||
<&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
|
||||
clock-names = "hda", "hda2hdmi", "hda2codec_2x";
|
||||
resets = <&tegra_car 125>, /* hda */
|
||||
<&tegra_car 128>, /* hda2hdmi */
|
||||
<&tegra_car 111>; /* hda2codec_2x */
|
||||
reset-names = "hda", "hda2hdmi", "hda2codec_2x";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
padctl: padctl@0,7009f000 {
|
||||
compatible = "nvidia,tegra132-xusb-padctl",
|
||||
"nvidia,tegra124-xusb-padctl";
|
||||
reg = <0x0 0x7009f000 0x0 0x1000>;
|
||||
resets = <&tegra_car 142>;
|
||||
reset-names = "padctl";
|
||||
|
||||
#phy-cells = <1>;
|
||||
|
||||
phys {
|
||||
pcie-0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sata-0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb3-0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb3-1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
utmi-0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
utmi-1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
utmi-2 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@0,700b0000 {
|
||||
compatible = "nvidia,tegra124-sdhci";
|
||||
reg = <0x0 0x700b0000 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
|
||||
clock-names = "sdhci";
|
||||
resets = <&tegra_car 14>;
|
||||
reset-names = "sdhci";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci@0,700b0200 {
|
||||
compatible = "nvidia,tegra124-sdhci";
|
||||
reg = <0x0 0x700b0200 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
|
||||
clock-names = "sdhci";
|
||||
resets = <&tegra_car 9>;
|
||||
reset-names = "sdhci";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci@0,700b0400 {
|
||||
compatible = "nvidia,tegra124-sdhci";
|
||||
reg = <0x0 0x700b0400 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
|
||||
clock-names = "sdhci";
|
||||
resets = <&tegra_car 69>;
|
||||
reset-names = "sdhci";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci@0,700b0600 {
|
||||
compatible = "nvidia,tegra124-sdhci";
|
||||
reg = <0x0 0x700b0600 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
|
||||
clock-names = "sdhci";
|
||||
resets = <&tegra_car 15>;
|
||||
reset-names = "sdhci";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
soctherm: thermal-sensor@0,700e2000 {
|
||||
compatible = "nvidia,tegra124-soctherm";
|
||||
reg = <0x0 0x700e2000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
|
||||
<&tegra_car TEGRA124_CLK_SOC_THERM>;
|
||||
clock-names = "tsensor", "soctherm";
|
||||
resets = <&tegra_car 78>;
|
||||
reset-names = "soctherm";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
ahub@0,70300000 {
|
||||
compatible = "nvidia,tegra124-ahub";
|
||||
reg = <0x0 0x70300000 0x0 0x200>,
|
||||
<0x0 0x70300800 0x0 0x800>,
|
||||
<0x0 0x70300200 0x0 0x600>;
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
|
||||
<&tegra_car TEGRA124_CLK_APBIF>;
|
||||
clock-names = "d_audio", "apbif";
|
||||
resets = <&tegra_car 106>, /* d_audio */
|
||||
<&tegra_car 107>, /* apbif */
|
||||
<&tegra_car 30>, /* i2s0 */
|
||||
<&tegra_car 11>, /* i2s1 */
|
||||
<&tegra_car 18>, /* i2s2 */
|
||||
<&tegra_car 101>, /* i2s3 */
|
||||
<&tegra_car 102>, /* i2s4 */
|
||||
<&tegra_car 108>, /* dam0 */
|
||||
<&tegra_car 109>, /* dam1 */
|
||||
<&tegra_car 110>, /* dam2 */
|
||||
<&tegra_car 10>, /* spdif */
|
||||
<&tegra_car 153>, /* amx */
|
||||
<&tegra_car 185>, /* amx1 */
|
||||
<&tegra_car 154>, /* adx */
|
||||
<&tegra_car 180>, /* adx1 */
|
||||
<&tegra_car 186>, /* afc0 */
|
||||
<&tegra_car 187>, /* afc1 */
|
||||
<&tegra_car 188>, /* afc2 */
|
||||
<&tegra_car 189>, /* afc3 */
|
||||
<&tegra_car 190>, /* afc4 */
|
||||
<&tegra_car 191>; /* afc5 */
|
||||
reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
|
||||
"i2s3", "i2s4", "dam0", "dam1", "dam2",
|
||||
"spdif", "amx", "amx1", "adx", "adx1",
|
||||
"afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
|
||||
dmas = <&apbdma 1>, <&apbdma 1>,
|
||||
<&apbdma 2>, <&apbdma 2>,
|
||||
<&apbdma 3>, <&apbdma 3>,
|
||||
<&apbdma 4>, <&apbdma 4>,
|
||||
<&apbdma 6>, <&apbdma 6>,
|
||||
<&apbdma 7>, <&apbdma 7>,
|
||||
<&apbdma 12>, <&apbdma 12>,
|
||||
<&apbdma 13>, <&apbdma 13>,
|
||||
<&apbdma 14>, <&apbdma 14>,
|
||||
<&apbdma 29>, <&apbdma 29>;
|
||||
dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
|
||||
"rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
|
||||
"rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
|
||||
"rx9", "tx9";
|
||||
ranges;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
tegra_i2s0: i2s@0,70301000 {
|
||||
compatible = "nvidia,tegra124-i2s";
|
||||
reg = <0x0 0x70301000 0x0 0x100>;
|
||||
nvidia,ahub-cif-ids = <4 4>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_I2S0>;
|
||||
clock-names = "i2s";
|
||||
resets = <&tegra_car 30>;
|
||||
reset-names = "i2s";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tegra_i2s1: i2s@0,70301100 {
|
||||
compatible = "nvidia,tegra124-i2s";
|
||||
reg = <0x0 0x70301100 0x0 0x100>;
|
||||
nvidia,ahub-cif-ids = <5 5>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_I2S1>;
|
||||
clock-names = "i2s";
|
||||
resets = <&tegra_car 11>;
|
||||
reset-names = "i2s";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tegra_i2s2: i2s@0,70301200 {
|
||||
compatible = "nvidia,tegra124-i2s";
|
||||
reg = <0x0 0x70301200 0x0 0x100>;
|
||||
nvidia,ahub-cif-ids = <6 6>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_I2S2>;
|
||||
clock-names = "i2s";
|
||||
resets = <&tegra_car 18>;
|
||||
reset-names = "i2s";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tegra_i2s3: i2s@0,70301300 {
|
||||
compatible = "nvidia,tegra124-i2s";
|
||||
reg = <0x0 0x70301300 0x0 0x100>;
|
||||
nvidia,ahub-cif-ids = <7 7>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_I2S3>;
|
||||
clock-names = "i2s";
|
||||
resets = <&tegra_car 101>;
|
||||
reset-names = "i2s";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tegra_i2s4: i2s@0,70301400 {
|
||||
compatible = "nvidia,tegra124-i2s";
|
||||
reg = <0x0 0x70301400 0x0 0x100>;
|
||||
nvidia,ahub-cif-ids = <8 8>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_I2S4>;
|
||||
clock-names = "i2s";
|
||||
resets = <&tegra_car 102>;
|
||||
reset-names = "i2s";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
usb@0,7d000000 {
|
||||
compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
|
||||
reg = <0x0 0x7d000000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phy_type = "utmi";
|
||||
clocks = <&tegra_car TEGRA124_CLK_USBD>;
|
||||
clock-names = "usb";
|
||||
resets = <&tegra_car 22>;
|
||||
reset-names = "usb";
|
||||
nvidia,phy = <&phy1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
phy1: usb-phy@0,7d000000 {
|
||||
compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
|
||||
reg = <0x0 0x7d000000 0x0 0x4000>,
|
||||
<0x0 0x7d000000 0x0 0x4000>;
|
||||
phy_type = "utmi";
|
||||
clocks = <&tegra_car TEGRA124_CLK_USBD>,
|
||||
<&tegra_car TEGRA124_CLK_PLL_U>,
|
||||
<&tegra_car TEGRA124_CLK_USBD>;
|
||||
clock-names = "reg", "pll_u", "utmi-pads";
|
||||
resets = <&tegra_car 22>, <&tegra_car 22>;
|
||||
reset-names = "usb", "utmi-pads";
|
||||
nvidia,hssync-start-delay = <0>;
|
||||
nvidia,idle-wait-delay = <17>;
|
||||
nvidia,elastic-limit = <16>;
|
||||
nvidia,term-range-adj = <6>;
|
||||
nvidia,xcvr-setup = <9>;
|
||||
nvidia,xcvr-lsfslew = <0>;
|
||||
nvidia,xcvr-lsrslew = <3>;
|
||||
nvidia,hssquelch-level = <2>;
|
||||
nvidia,hsdiscon-level = <5>;
|
||||
nvidia,xcvr-hsslew = <12>;
|
||||
nvidia,has-utmi-pad-registers;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@0,7d004000 {
|
||||
compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
|
||||
reg = <0x0 0x7d004000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phy_type = "utmi";
|
||||
clocks = <&tegra_car TEGRA124_CLK_USB2>;
|
||||
clock-names = "usb";
|
||||
resets = <&tegra_car 58>;
|
||||
reset-names = "usb";
|
||||
nvidia,phy = <&phy2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
phy2: usb-phy@0,7d004000 {
|
||||
compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
|
||||
reg = <0x0 0x7d004000 0x0 0x4000>,
|
||||
<0x0 0x7d000000 0x0 0x4000>;
|
||||
phy_type = "utmi";
|
||||
clocks = <&tegra_car TEGRA124_CLK_USB2>,
|
||||
<&tegra_car TEGRA124_CLK_PLL_U>,
|
||||
<&tegra_car TEGRA124_CLK_USBD>;
|
||||
clock-names = "reg", "pll_u", "utmi-pads";
|
||||
resets = <&tegra_car 58>, <&tegra_car 22>;
|
||||
reset-names = "usb", "utmi-pads";
|
||||
nvidia,hssync-start-delay = <0>;
|
||||
nvidia,idle-wait-delay = <17>;
|
||||
nvidia,elastic-limit = <16>;
|
||||
nvidia,term-range-adj = <6>;
|
||||
nvidia,xcvr-setup = <9>;
|
||||
nvidia,xcvr-lsfslew = <0>;
|
||||
nvidia,xcvr-lsrslew = <3>;
|
||||
nvidia,hssquelch-level = <2>;
|
||||
nvidia,hsdiscon-level = <5>;
|
||||
nvidia,xcvr-hsslew = <12>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@0,7d008000 {
|
||||
compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
|
||||
reg = <0x0 0x7d008000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phy_type = "utmi";
|
||||
clocks = <&tegra_car TEGRA124_CLK_USB3>;
|
||||
clock-names = "usb";
|
||||
resets = <&tegra_car 59>;
|
||||
reset-names = "usb";
|
||||
nvidia,phy = <&phy3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
phy3: usb-phy@0,7d008000 {
|
||||
compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
|
||||
reg = <0x0 0x7d008000 0x0 0x4000>,
|
||||
<0x0 0x7d000000 0x0 0x4000>;
|
||||
phy_type = "utmi";
|
||||
clocks = <&tegra_car TEGRA124_CLK_USB3>,
|
||||
<&tegra_car TEGRA124_CLK_PLL_U>,
|
||||
<&tegra_car TEGRA124_CLK_USBD>;
|
||||
clock-names = "reg", "pll_u", "utmi-pads";
|
||||
resets = <&tegra_car 59>, <&tegra_car 22>;
|
||||
reset-names = "usb", "utmi-pads";
|
||||
nvidia,hssync-start-delay = <0>;
|
||||
nvidia,idle-wait-delay = <17>;
|
||||
nvidia,elastic-limit = <16>;
|
||||
nvidia,term-range-adj = <6>;
|
||||
nvidia,xcvr-setup = <9>;
|
||||
nvidia,xcvr-lsfslew = <0>;
|
||||
nvidia,xcvr-lsrslew = <3>;
|
||||
nvidia,hssquelch-level = <2>;
|
||||
nvidia,hsdiscon-level = <5>;
|
||||
nvidia,xcvr-hsslew = <12>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "nvidia,denver", "arm,armv8";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "nvidia,denver", "arm,armv8";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <GIC_PPI 13
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
interrupt-parent = <&gic>;
|
||||
};
|
||||
};
|
||||
45
arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
Normal file
45
arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
Normal file
@ -0,0 +1,45 @@
|
||||
#include "tegra210.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NVIDIA Jetson TX1";
|
||||
compatible = "nvidia,p2180", "nvidia,tegra210";
|
||||
|
||||
aliases {
|
||||
rtc1 = "/rtc@0,7000e000";
|
||||
serial0 = &uarta;
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0x1 0x0>;
|
||||
};
|
||||
|
||||
/* debug port */
|
||||
serial@0,70006000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pmc@0,7000e400 {
|
||||
nvidia,invert-interrupt;
|
||||
};
|
||||
|
||||
/* eMMC */
|
||||
sdhci@0,700b0600 {
|
||||
status = "okay";
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock@0 {
|
||||
compatible = "fixed-clock";
|
||||
reg = <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
};
|
||||
9
arch/arm64/boot/dts/nvidia/tegra210-p2371-0000.dts
Normal file
9
arch/arm64/boot/dts/nvidia/tegra210-p2371-0000.dts
Normal file
@ -0,0 +1,9 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include "tegra210-p2530.dtsi"
|
||||
#include "tegra210-p2595.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NVIDIA Tegra210 P2371 (P2530/P2595) reference design";
|
||||
compatible = "nvidia,p2371-0000", "nvidia,tegra210";
|
||||
};
|
||||
9
arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
Normal file
9
arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
Normal file
@ -0,0 +1,9 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include "tegra210-p2180.dtsi"
|
||||
#include "tegra210-p2597.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NVIDIA Jetson TX1 Developer Kit";
|
||||
compatible = "nvidia,p2371-2180", "nvidia,tegra210";
|
||||
};
|
||||
50
arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi
Normal file
50
arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi
Normal file
@ -0,0 +1,50 @@
|
||||
#include "tegra210.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NVIDIA Tegra210 P2530 main board";
|
||||
compatible = "nvidia,p2530", "nvidia,tegra210";
|
||||
|
||||
aliases {
|
||||
rtc1 = "/rtc@0,7000e000";
|
||||
serial0 = &uarta;
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0x0 0xc0000000>;
|
||||
};
|
||||
|
||||
/* debug port */
|
||||
serial@0,70006000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@0,7000d000 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
pmc@0,7000e400 {
|
||||
nvidia,invert-interrupt;
|
||||
};
|
||||
|
||||
/* eMMC */
|
||||
sdhci@0,700b0600 {
|
||||
status = "okay";
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock@0 {
|
||||
compatible = "fixed-clock";
|
||||
reg = <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
};
|
||||
1302
arch/arm64/boot/dts/nvidia/tegra210-p2571.dts
Normal file
1302
arch/arm64/boot/dts/nvidia/tegra210-p2571.dts
Normal file
File diff suppressed because it is too large
Load Diff
1272
arch/arm64/boot/dts/nvidia/tegra210-p2595.dtsi
Normal file
1272
arch/arm64/boot/dts/nvidia/tegra210-p2595.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
1270
arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
Normal file
1270
arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
805
arch/arm64/boot/dts/nvidia/tegra210.dtsi
Normal file
805
arch/arm64/boot/dts/nvidia/tegra210.dtsi
Normal file
@ -0,0 +1,805 @@
|
||||
#include <dt-bindings/clock/tegra210-car.h>
|
||||
#include <dt-bindings/gpio/tegra-gpio.h>
|
||||
#include <dt-bindings/memory/tegra210-mc.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
compatible = "nvidia,tegra210";
|
||||
interrupt-parent = <&lic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
host1x@0,50000000 {
|
||||
compatible = "nvidia,tegra210-host1x", "simple-bus";
|
||||
reg = <0x0 0x50000000 0x0 0x00034000>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
|
||||
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
|
||||
clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
|
||||
clock-names = "host1x";
|
||||
resets = <&tegra_car 28>;
|
||||
reset-names = "host1x";
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
|
||||
|
||||
dpaux1: dpaux@0,54040000 {
|
||||
compatible = "nvidia,tegra210-dpaux";
|
||||
reg = <0x0 0x54040000 0x0 0x00040000>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_DP>;
|
||||
clock-names = "dpaux", "parent";
|
||||
resets = <&tegra_car 207>;
|
||||
reset-names = "dpaux";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vi@0,54080000 {
|
||||
compatible = "nvidia,tegra210-vi";
|
||||
reg = <0x0 0x54080000 0x0 0x00040000>;
|
||||
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tsec@0,54100000 {
|
||||
compatible = "nvidia,tegra210-tsec";
|
||||
reg = <0x0 0x54100000 0x0 0x00040000>;
|
||||
};
|
||||
|
||||
dc@0,54200000 {
|
||||
compatible = "nvidia,tegra210-dc";
|
||||
reg = <0x0 0x54200000 0x0 0x00040000>;
|
||||
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_DISP1>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_P>;
|
||||
clock-names = "dc", "parent";
|
||||
resets = <&tegra_car 27>;
|
||||
reset-names = "dc";
|
||||
|
||||
iommus = <&mc TEGRA_SWGROUP_DC>;
|
||||
|
||||
nvidia,head = <0>;
|
||||
};
|
||||
|
||||
dc@0,54240000 {
|
||||
compatible = "nvidia,tegra210-dc";
|
||||
reg = <0x0 0x54240000 0x0 0x00040000>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_DISP2>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_P>;
|
||||
clock-names = "dc", "parent";
|
||||
resets = <&tegra_car 26>;
|
||||
reset-names = "dc";
|
||||
|
||||
iommus = <&mc TEGRA_SWGROUP_DCB>;
|
||||
|
||||
nvidia,head = <1>;
|
||||
};
|
||||
|
||||
dsi@0,54300000 {
|
||||
compatible = "nvidia,tegra210-dsi";
|
||||
reg = <0x0 0x54300000 0x0 0x00040000>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_DSIA>,
|
||||
<&tegra_car TEGRA210_CLK_DSIALP>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
|
||||
clock-names = "dsi", "lp", "parent";
|
||||
resets = <&tegra_car 48>;
|
||||
reset-names = "dsi";
|
||||
nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
|
||||
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
vic@0,54340000 {
|
||||
compatible = "nvidia,tegra210-vic";
|
||||
reg = <0x0 0x54340000 0x0 0x00040000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nvjpg@0,54380000 {
|
||||
compatible = "nvidia,tegra210-nvjpg";
|
||||
reg = <0x0 0x54380000 0x0 0x00040000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dsi@0,54400000 {
|
||||
compatible = "nvidia,tegra210-dsi";
|
||||
reg = <0x0 0x54400000 0x0 0x00040000>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_DSIB>,
|
||||
<&tegra_car TEGRA210_CLK_DSIBLP>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
|
||||
clock-names = "dsi", "lp", "parent";
|
||||
resets = <&tegra_car 82>;
|
||||
reset-names = "dsi";
|
||||
nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
|
||||
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
nvdec@0,54480000 {
|
||||
compatible = "nvidia,tegra210-nvdec";
|
||||
reg = <0x0 0x54480000 0x0 0x00040000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nvenc@0,544c0000 {
|
||||
compatible = "nvidia,tegra210-nvenc";
|
||||
reg = <0x0 0x544c0000 0x0 0x00040000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tsec@0,54500000 {
|
||||
compatible = "nvidia,tegra210-tsec";
|
||||
reg = <0x0 0x54500000 0x0 0x00040000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sor@0,54540000 {
|
||||
compatible = "nvidia,tegra210-sor";
|
||||
reg = <0x0 0x54540000 0x0 0x00040000>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SOR0>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_DP>,
|
||||
<&tegra_car TEGRA210_CLK_SOR_SAFE>;
|
||||
clock-names = "sor", "parent", "dp", "safe";
|
||||
resets = <&tegra_car 182>;
|
||||
reset-names = "sor";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sor@0,54580000 {
|
||||
compatible = "nvidia,tegra210-sor1";
|
||||
reg = <0x0 0x54580000 0x0 0x00040000>;
|
||||
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SOR1>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_DP>,
|
||||
<&tegra_car TEGRA210_CLK_SOR_SAFE>;
|
||||
clock-names = "sor", "parent", "dp", "safe";
|
||||
resets = <&tegra_car 183>;
|
||||
reset-names = "sor";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dpaux: dpaux@0,545c0000 {
|
||||
compatible = "nvidia,tegra124-dpaux";
|
||||
reg = <0x0 0x545c0000 0x0 0x00040000>;
|
||||
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_DP>;
|
||||
clock-names = "dpaux", "parent";
|
||||
resets = <&tegra_car 181>;
|
||||
reset-names = "dpaux";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
isp@0,54600000 {
|
||||
compatible = "nvidia,tegra210-isp";
|
||||
reg = <0x0 0x54600000 0x0 0x00040000>;
|
||||
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
isp@0,54680000 {
|
||||
compatible = "nvidia,tegra210-isp";
|
||||
reg = <0x0 0x54680000 0x0 0x00040000>;
|
||||
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@0,546c0000 {
|
||||
compatible = "nvidia,tegra210-i2c-vi";
|
||||
reg = <0x0 0x546c0000 0x0 0x00040000>;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@0,50041000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0x50041000 0x0 0x1000>,
|
||||
<0x0 0x50042000 0x0 0x2000>,
|
||||
<0x0 0x50044000 0x0 0x2000>,
|
||||
<0x0 0x50046000 0x0 0x2000>;
|
||||
interrupts = <GIC_PPI 9
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
interrupt-parent = <&gic>;
|
||||
};
|
||||
|
||||
gpu@0,57000000 {
|
||||
compatible = "nvidia,gm20b";
|
||||
reg = <0x0 0x57000000 0x0 0x01000000>,
|
||||
<0x0 0x58000000 0x0 0x01000000>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "stall", "nonstall";
|
||||
clocks = <&tegra_car TEGRA210_CLK_GPU>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_P_OUT5>;
|
||||
clock-names = "gpu", "pwr";
|
||||
resets = <&tegra_car 184>;
|
||||
reset-names = "gpu";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lic: interrupt-controller@0,60004000 {
|
||||
compatible = "nvidia,tegra210-ictlr";
|
||||
reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
|
||||
<0x0 0x60004100 0x0 0x40>, /* secondary controller */
|
||||
<0x0 0x60004200 0x0 0x40>, /* tertiary controller */
|
||||
<0x0 0x60004300 0x0 0x40>, /* quaternary controller */
|
||||
<0x0 0x60004400 0x0 0x40>, /* quinary controller */
|
||||
<0x0 0x60004500 0x0 0x40>; /* senary controller */
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-parent = <&gic>;
|
||||
};
|
||||
|
||||
timer@0,60005000 {
|
||||
compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer";
|
||||
reg = <0x0 0x60005000 0x0 0x400>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_TIMER>;
|
||||
clock-names = "timer";
|
||||
};
|
||||
|
||||
tegra_car: clock@0,60006000 {
|
||||
compatible = "nvidia,tegra210-car";
|
||||
reg = <0x0 0x60006000 0x0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
flow-controller@0,60007000 {
|
||||
compatible = "nvidia,tegra210-flowctrl";
|
||||
reg = <0x0 0x60007000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
gpio: gpio@0,6000d000 {
|
||||
compatible = "nvidia,tegra210-gpio", "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
|
||||
reg = <0x0 0x6000d000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
apbdma: dma@0,60020000 {
|
||||
compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
|
||||
reg = <0x0 0x60020000 0x0 0x1400>;
|
||||
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
|
||||
clock-names = "dma";
|
||||
resets = <&tegra_car 34>;
|
||||
reset-names = "dma";
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
apbmisc@0,70000800 {
|
||||
compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
|
||||
reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
|
||||
<0x0 0x7000e864 0x0 0x04>; /* Strapping options */
|
||||
};
|
||||
|
||||
pinmux: pinmux@0,700008d4 {
|
||||
compatible = "nvidia,tegra210-pinmux";
|
||||
reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
|
||||
<0x0 0x70003000 0x0 0x294>; /* Mux registers */
|
||||
};
|
||||
|
||||
/*
|
||||
* There are two serial driver i.e. 8250 based simple serial
|
||||
* driver and APB DMA based serial driver for higher baudrate
|
||||
* and performace. To enable the 8250 based driver, the compatible
|
||||
* is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
|
||||
* the APB DMA based serial driver, the comptible is
|
||||
* "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
|
||||
*/
|
||||
uarta: serial@0,70006000 {
|
||||
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x0 0x70006000 0x0 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_UARTA>;
|
||||
clock-names = "serial";
|
||||
resets = <&tegra_car 6>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 8>, <&apbdma 8>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uartb: serial@0,70006040 {
|
||||
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x0 0x70006040 0x0 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_UARTB>;
|
||||
clock-names = "serial";
|
||||
resets = <&tegra_car 7>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 9>, <&apbdma 9>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uartc: serial@0,70006200 {
|
||||
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x0 0x70006200 0x0 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_UARTC>;
|
||||
clock-names = "serial";
|
||||
resets = <&tegra_car 55>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 10>, <&apbdma 10>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uartd: serial@0,70006300 {
|
||||
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x0 0x70006300 0x0 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_UARTD>;
|
||||
clock-names = "serial";
|
||||
resets = <&tegra_car 65>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 19>, <&apbdma 19>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm: pwm@0,7000a000 {
|
||||
compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
|
||||
reg = <0x0 0x7000a000 0x0 0x100>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_PWM>;
|
||||
clock-names = "pwm";
|
||||
resets = <&tegra_car 17>;
|
||||
reset-names = "pwm";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@0,7000c000 {
|
||||
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
|
||||
reg = <0x0 0x7000c000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_I2C1>;
|
||||
clock-names = "div-clk";
|
||||
resets = <&tegra_car 12>;
|
||||
reset-names = "i2c";
|
||||
dmas = <&apbdma 21>, <&apbdma 21>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@0,7000c400 {
|
||||
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
|
||||
reg = <0x0 0x7000c400 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_I2C2>;
|
||||
clock-names = "div-clk";
|
||||
resets = <&tegra_car 54>;
|
||||
reset-names = "i2c";
|
||||
dmas = <&apbdma 22>, <&apbdma 22>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@0,7000c500 {
|
||||
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
|
||||
reg = <0x0 0x7000c500 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_I2C3>;
|
||||
clock-names = "div-clk";
|
||||
resets = <&tegra_car 67>;
|
||||
reset-names = "i2c";
|
||||
dmas = <&apbdma 23>, <&apbdma 23>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@0,7000c700 {
|
||||
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
|
||||
reg = <0x0 0x7000c700 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_I2C4>;
|
||||
clock-names = "div-clk";
|
||||
resets = <&tegra_car 103>;
|
||||
reset-names = "i2c";
|
||||
dmas = <&apbdma 26>, <&apbdma 26>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@0,7000d000 {
|
||||
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
|
||||
reg = <0x0 0x7000d000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_I2C5>;
|
||||
clock-names = "div-clk";
|
||||
resets = <&tegra_car 47>;
|
||||
reset-names = "i2c";
|
||||
dmas = <&apbdma 24>, <&apbdma 24>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@0,7000d100 {
|
||||
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
|
||||
reg = <0x0 0x7000d100 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_I2C6>;
|
||||
clock-names = "div-clk";
|
||||
resets = <&tegra_car 166>;
|
||||
reset-names = "i2c";
|
||||
dmas = <&apbdma 30>, <&apbdma 30>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@0,7000d400 {
|
||||
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
|
||||
reg = <0x0 0x7000d400 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SBC1>;
|
||||
clock-names = "spi";
|
||||
resets = <&tegra_car 41>;
|
||||
reset-names = "spi";
|
||||
dmas = <&apbdma 15>, <&apbdma 15>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@0,7000d600 {
|
||||
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
|
||||
reg = <0x0 0x7000d600 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SBC2>;
|
||||
clock-names = "spi";
|
||||
resets = <&tegra_car 44>;
|
||||
reset-names = "spi";
|
||||
dmas = <&apbdma 16>, <&apbdma 16>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@0,7000d800 {
|
||||
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
|
||||
reg = <0x0 0x7000d800 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SBC3>;
|
||||
clock-names = "spi";
|
||||
resets = <&tegra_car 46>;
|
||||
reset-names = "spi";
|
||||
dmas = <&apbdma 17>, <&apbdma 17>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@0,7000da00 {
|
||||
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
|
||||
reg = <0x0 0x7000da00 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SBC4>;
|
||||
clock-names = "spi";
|
||||
resets = <&tegra_car 68>;
|
||||
reset-names = "spi";
|
||||
dmas = <&apbdma 18>, <&apbdma 18>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc@0,7000e000 {
|
||||
compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
|
||||
reg = <0x0 0x7000e000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_RTC>;
|
||||
clock-names = "rtc";
|
||||
};
|
||||
|
||||
pmc: pmc@0,7000e400 {
|
||||
compatible = "nvidia,tegra210-pmc";
|
||||
reg = <0x0 0x7000e400 0x0 0x400>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
fuse@0,7000f800 {
|
||||
compatible = "nvidia,tegra210-efuse";
|
||||
reg = <0x0 0x7000f800 0x0 0x400>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_FUSE>;
|
||||
clock-names = "fuse";
|
||||
resets = <&tegra_car 39>;
|
||||
reset-names = "fuse";
|
||||
};
|
||||
|
||||
mc: memory-controller@0,70019000 {
|
||||
compatible = "nvidia,tegra210-mc";
|
||||
reg = <0x0 0x70019000 0x0 0x1000>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_MC>;
|
||||
clock-names = "mc";
|
||||
|
||||
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
hda@0,70030000 {
|
||||
compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
|
||||
reg = <0x0 0x70030000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_HDA>,
|
||||
<&tegra_car TEGRA210_CLK_HDA2HDMI>,
|
||||
<&tegra_car TEGRA210_CLK_HDA2CODEC_2X>;
|
||||
clock-names = "hda", "hda2hdmi", "hda2codec_2x";
|
||||
resets = <&tegra_car 125>, /* hda */
|
||||
<&tegra_car 128>, /* hda2hdmi */
|
||||
<&tegra_car 111>; /* hda2codec_2x */
|
||||
reset-names = "hda", "hda2hdmi", "hda2codec_2x";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci@0,700b0000 {
|
||||
compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
|
||||
reg = <0x0 0x700b0000 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
|
||||
clock-names = "sdhci";
|
||||
resets = <&tegra_car 14>;
|
||||
reset-names = "sdhci";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci@0,700b0200 {
|
||||
compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
|
||||
reg = <0x0 0x700b0200 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
|
||||
clock-names = "sdhci";
|
||||
resets = <&tegra_car 9>;
|
||||
reset-names = "sdhci";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci@0,700b0400 {
|
||||
compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
|
||||
reg = <0x0 0x700b0400 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
|
||||
clock-names = "sdhci";
|
||||
resets = <&tegra_car 69>;
|
||||
reset-names = "sdhci";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci@0,700b0600 {
|
||||
compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
|
||||
reg = <0x0 0x700b0600 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
|
||||
clock-names = "sdhci";
|
||||
resets = <&tegra_car 15>;
|
||||
reset-names = "sdhci";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mipi: mipi@0,700e3000 {
|
||||
compatible = "nvidia,tegra210-mipi";
|
||||
reg = <0x0 0x700e3000 0x0 0x100>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
|
||||
clock-names = "mipi-cal";
|
||||
#nvidia,mipi-calibrate-cells = <1>;
|
||||
};
|
||||
|
||||
spi@0,70410000 {
|
||||
compatible = "nvidia,tegra210-qspi";
|
||||
reg = <0x0 0x70410000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_QSPI>;
|
||||
clock-names = "qspi";
|
||||
resets = <&tegra_car 211>;
|
||||
reset-names = "qspi";
|
||||
dmas = <&apbdma 5>, <&apbdma 5>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@0,7d000000 {
|
||||
compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
|
||||
reg = <0x0 0x7d000000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phy_type = "utmi";
|
||||
clocks = <&tegra_car TEGRA210_CLK_USBD>;
|
||||
clock-names = "usb";
|
||||
resets = <&tegra_car 22>;
|
||||
reset-names = "usb";
|
||||
nvidia,phy = <&phy1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
phy1: usb-phy@0,7d000000 {
|
||||
compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
|
||||
reg = <0x0 0x7d000000 0x0 0x4000>,
|
||||
<0x0 0x7d000000 0x0 0x4000>;
|
||||
phy_type = "utmi";
|
||||
clocks = <&tegra_car TEGRA210_CLK_USBD>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_U>,
|
||||
<&tegra_car TEGRA210_CLK_USBD>;
|
||||
clock-names = "reg", "pll_u", "utmi-pads";
|
||||
resets = <&tegra_car 22>, <&tegra_car 22>;
|
||||
reset-names = "usb", "utmi-pads";
|
||||
nvidia,hssync-start-delay = <0>;
|
||||
nvidia,idle-wait-delay = <17>;
|
||||
nvidia,elastic-limit = <16>;
|
||||
nvidia,term-range-adj = <6>;
|
||||
nvidia,xcvr-setup = <9>;
|
||||
nvidia,xcvr-lsfslew = <0>;
|
||||
nvidia,xcvr-lsrslew = <3>;
|
||||
nvidia,hssquelch-level = <2>;
|
||||
nvidia,hsdiscon-level = <5>;
|
||||
nvidia,xcvr-hsslew = <12>;
|
||||
nvidia,has-utmi-pad-registers;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@0,7d004000 {
|
||||
compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
|
||||
reg = <0x0 0x7d004000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phy_type = "utmi";
|
||||
clocks = <&tegra_car TEGRA210_CLK_USB2>;
|
||||
clock-names = "usb";
|
||||
resets = <&tegra_car 58>;
|
||||
reset-names = "usb";
|
||||
nvidia,phy = <&phy2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
phy2: usb-phy@0,7d004000 {
|
||||
compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
|
||||
reg = <0x0 0x7d004000 0x0 0x4000>,
|
||||
<0x0 0x7d000000 0x0 0x4000>;
|
||||
phy_type = "utmi";
|
||||
clocks = <&tegra_car TEGRA210_CLK_USB2>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_U>,
|
||||
<&tegra_car TEGRA210_CLK_USBD>;
|
||||
clock-names = "reg", "pll_u", "utmi-pads";
|
||||
resets = <&tegra_car 58>, <&tegra_car 22>;
|
||||
reset-names = "usb", "utmi-pads";
|
||||
nvidia,hssync-start-delay = <0>;
|
||||
nvidia,idle-wait-delay = <17>;
|
||||
nvidia,elastic-limit = <16>;
|
||||
nvidia,term-range-adj = <6>;
|
||||
nvidia,xcvr-setup = <9>;
|
||||
nvidia,xcvr-lsfslew = <0>;
|
||||
nvidia,xcvr-lsrslew = <3>;
|
||||
nvidia,hssquelch-level = <2>;
|
||||
nvidia,hsdiscon-level = <5>;
|
||||
nvidia,xcvr-hsslew = <12>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
interrupt-parent = <&gic>;
|
||||
};
|
||||
};
|
||||
@ -4,7 +4,7 @@ config ARM_AMBA
|
||||
if ARM_AMBA
|
||||
|
||||
config TEGRA_AHB
|
||||
bool "Enable AHB driver for NVIDIA Tegra SoCs"
|
||||
bool
|
||||
default y if ARCH_TEGRA
|
||||
help
|
||||
Adds AHB configuration functionality for NVIDIA Tegra SoCs,
|
||||
|
||||
@ -7,6 +7,7 @@ source "drivers/soc/mediatek/Kconfig"
|
||||
source "drivers/soc/qcom/Kconfig"
|
||||
source "drivers/soc/rockchip/Kconfig"
|
||||
source "drivers/soc/sunxi/Kconfig"
|
||||
source "drivers/soc/tegra/Kconfig"
|
||||
source "drivers/soc/ti/Kconfig"
|
||||
source "drivers/soc/versatile/Kconfig"
|
||||
|
||||
|
||||
83
drivers/soc/tegra/Kconfig
Normal file
83
drivers/soc/tegra/Kconfig
Normal file
@ -0,0 +1,83 @@
|
||||
if ARCH_TEGRA
|
||||
|
||||
# 32-bit ARM SoCs
|
||||
if ARM
|
||||
|
||||
config ARCH_TEGRA_2x_SOC
|
||||
bool "Enable support for Tegra20 family"
|
||||
select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
|
||||
select ARM_ERRATA_720789
|
||||
select ARM_ERRATA_754327 if SMP
|
||||
select ARM_ERRATA_764369 if SMP
|
||||
select PINCTRL_TEGRA20
|
||||
select PL310_ERRATA_727915 if CACHE_L2X0
|
||||
select PL310_ERRATA_769419 if CACHE_L2X0
|
||||
select TEGRA_TIMER
|
||||
help
|
||||
Support for NVIDIA Tegra AP20 and T20 processors, based on the
|
||||
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
|
||||
|
||||
config ARCH_TEGRA_3x_SOC
|
||||
bool "Enable support for Tegra30 family"
|
||||
select ARM_ERRATA_754322
|
||||
select ARM_ERRATA_764369 if SMP
|
||||
select PINCTRL_TEGRA30
|
||||
select PL310_ERRATA_769419 if CACHE_L2X0
|
||||
select TEGRA_TIMER
|
||||
help
|
||||
Support for NVIDIA Tegra T30 processor family, based on the
|
||||
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
|
||||
|
||||
config ARCH_TEGRA_114_SOC
|
||||
bool "Enable support for Tegra114 family"
|
||||
select ARM_ERRATA_798181 if SMP
|
||||
select ARM_L1_CACHE_SHIFT_6
|
||||
select HAVE_ARM_ARCH_TIMER
|
||||
select PINCTRL_TEGRA114
|
||||
select TEGRA_TIMER
|
||||
help
|
||||
Support for NVIDIA Tegra T114 processor family, based on the
|
||||
ARM CortexA15MP CPU
|
||||
|
||||
config ARCH_TEGRA_124_SOC
|
||||
bool "Enable support for Tegra124 family"
|
||||
select ARM_L1_CACHE_SHIFT_6
|
||||
select HAVE_ARM_ARCH_TIMER
|
||||
select PINCTRL_TEGRA124
|
||||
select TEGRA_TIMER
|
||||
help
|
||||
Support for NVIDIA Tegra T124 processor family, based on the
|
||||
ARM CortexA15MP CPU
|
||||
|
||||
endif
|
||||
|
||||
# 64-bit ARM SoCs
|
||||
if ARM64
|
||||
|
||||
config ARCH_TEGRA_132_SOC
|
||||
bool "NVIDIA Tegra132 SoC"
|
||||
select PINCTRL_TEGRA124
|
||||
help
|
||||
Enable support for NVIDIA Tegra132 SoC, based on the Denver
|
||||
ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
|
||||
but contains an NVIDIA Denver CPU complex in place of
|
||||
Tegra124's "4+1" Cortex-A15 CPU complex.
|
||||
|
||||
config ARCH_TEGRA_210_SOC
|
||||
bool "NVIDIA Tegra210 SoC"
|
||||
select PINCTRL_TEGRA210
|
||||
help
|
||||
Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1,
|
||||
the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53
|
||||
cores in a switched configuration. It features a GPU of the Maxwell
|
||||
architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1
|
||||
and providing 256 CUDA cores. It supports hardware-accelerated en-
|
||||
and decoding of various video standards including H.265, H.264 and
|
||||
VP8 at 4K resolution and up to 60 fps.
|
||||
|
||||
Besides the multimedia features it also comes with a variety of I/O
|
||||
controllers, such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to
|
||||
name only a few.
|
||||
|
||||
endif
|
||||
endif
|
||||
@ -229,6 +229,8 @@ config USB_EHCI_TEGRA
|
||||
depends on ARCH_TEGRA
|
||||
select USB_EHCI_ROOT_HUB_TT
|
||||
select USB_PHY
|
||||
select USB_ULPI
|
||||
select USB_ULPI_VIEWPORT
|
||||
help
|
||||
This driver enables support for the internal USB Host Controllers
|
||||
found in NVIDIA Tegra SoCs. The controllers are EHCI compliant.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user