From 795d5fd4b8b06944976c95e8592e17e2d415aa81 Mon Sep 17 00:00:00 2001 From: Dmitry Artamonow Date: Tue, 6 Mar 2012 12:45:43 +0400 Subject: [PATCH] arm/tegra: add timeout to PCIe PLL lock detection loop Tegra PCIe driver waits for PLL to lock using busy loop. If PLL fails to lock for some reason, this leads to silent lockup while booting (as PCIe code is not modular). Fix by adding timeout, so if PLL doesn't lock in a couple of seconds, just PCIe driver fails and machine continues to boot. Signed-off-by: Dmitry Artamonow Acked-by: Stephen Warren Signed-off-by: Olof Johansson --- arch/arm/mach-tegra/pcie.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c index af8b63435727..0a1dec694394 100644 --- a/arch/arm/mach-tegra/pcie.c +++ b/arch/arm/mach-tegra/pcie.c @@ -585,10 +585,10 @@ static void tegra_pcie_setup_translations(void) afi_writel(0, AFI_MSI_BAR_SZ); } -static void tegra_pcie_enable_controller(void) +static int tegra_pcie_enable_controller(void) { u32 val, reg; - int i; + int i, timeout; /* Enable slot clock and pulse the reset signals */ for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) { @@ -639,8 +639,14 @@ static void tegra_pcie_enable_controller(void) pads_writel(0xfa5cfa5c, 0xc8); /* Wait for the PLL to lock */ + timeout = 2000; do { val = pads_readl(PADS_PLL_CTL); + mdelay(1); + if (--timeout == 0) { + pr_err("Tegra PCIe error: timeout waiting for PLL\n"); + return -EBUSY; + } } while (!(val & PADS_PLL_CTL_LOCKDET)); /* turn off IDDQ override */ @@ -921,7 +927,9 @@ int __init tegra_pcie_init(bool init_port0, bool init_port1) if (err) return err; - tegra_pcie_enable_controller(); + err = tegra_pcie_enable_controller(); + if (err) + return err; /* setup the AFI address translations */ tegra_pcie_setup_translations();