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RISC-V Devicetrees for v6.7

Browse Source 
StarFive:
 Things are a bit slower for StarFive this window, there's only the
 addition of audio related DT nodes to speak of here.
 
 Generic:
 The SiFive, StarFive and Microchip devicetrees have had my replacement
 ISA extension detection properties added. Unfortunately, the old
 "riscv,isa" property never defined exactly what the extensions it
 contained meant, and people were want to fill it in incorrectly (and
 call upstream kernel devs idiots for not doing the same). The new
 properties have explicit definitions and hopefully will stand up better
 to some of the variation from RVI.
 
 Sophgo:
 Two new SoCs, one is probably the first of several with up/down tuned
 variants, that have a pair of T-Head c906 cores and appear aimed at the
 IP camera, smart <insert whatever> etc markets. They are intended to run
 in AMP mode, with an RTOS on the less powerful core. The other is far
 more interesting to kernel developers however, the 64-core SG2042, with
 more recent c920 cores from T-Head at 2 GHz. For both, support is at a
 very basic stage - some of the same developers are working on them as
 other T-Head powered SoCs, but hopefully things will move beyond a basic
 console boot. The goal is for Chen Wang to take over maintaining the
 Sophgo support once they have some more experience with the process.
 
 Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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Merge tag 'riscv-dt-for-v6.7' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt

RISC-V Devicetrees for v6.7

StarFive:
Things are a bit slower for StarFive this window, there's only the
addition of audio related DT nodes to speak of here.

Generic:
The SiFive, StarFive and Microchip devicetrees have had my replacement
ISA extension detection properties added. Unfortunately, the old
"riscv,isa" property never defined exactly what the extensions it
contained meant, and people were want to fill it in incorrectly (and
call upstream kernel devs idiots for not doing the same). The new
properties have explicit definitions and hopefully will stand up better
to some of the variation from RVI.

Sophgo:
Two new SoCs, one is probably the first of several with up/down tuned
variants, that have a pair of T-Head c906 cores and appear aimed at the
IP camera, smart <insert whatever> etc markets. They are intended to run
in AMP mode, with an RTOS on the less powerful core. The other is far
more interesting to kernel developers however, the 64-core SG2042, with
more recent c920 cores from T-Head at 2 GHz. For both, support is at a
very basic stage - some of the same developers are working on them as
other T-Head powered SoCs, but hopefully things will move beyond a basic
console boot. The goal is for Chen Wang to take over maintaining the
Sophgo support once they have some more experience with the process.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

* tag 'riscv-dt-for-v6.7' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: (22 commits)
  riscv: dts: starfive: convert isa detection to new properties
  riscv: dts: sifive: convert isa detection to new properties
  riscv: dts: microchip: convert isa detection to new properties
  riscv: dts: sophgo: add Milk-V Duo board device tree
  riscv: dts: sophgo: add initial CV1800B SoC device tree
  dt-bindings: riscv: Add Milk-V Duo board compatibles
  dt-bindings: timer: Add SOPHGO CV1800B clint
  dt-bindings: interrupt-controller: Add SOPHGO CV1800B plic
  riscv: defconfig: enable SOPHGO SoC
  riscv: dts: sophgo: add Milk-V Pioneer board device tree
  riscv: dts: add initial Sophgo SG2042 SoC device tree
  dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi
  dt-bindings: timer: Add Sophgo sg2042 CLINT timer
  dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC
  dt-bindings: riscv: Add T-HEAD C920 compatibles
  dt-bindings: riscv: add sophgo sg2042 bindings
  dt-bindings: vendor-prefixes: add milkv/sophgo
  riscv: Add SOPHGO SOC family Kconfig support
  riscv: dts: starfive: add assigned-clock* to limit frquency
  riscv: dts: starfive: Add JH7110 PWM-DAC support
  ...

Link: https://lore.kernel.org/r/20231016-filing-payroll-7aca51b8f1a3@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-10-18 16:03:47 +02:00
commit 79384a0475
24 changed files with 2906 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
View File

@ -65,6 +65,8 @@ properties:
- items:
- enum:
- allwinner,sun20i-d1-plic
- sophgo,cv1800b-plic
- sophgo,sg2042-plic
- thead,th1520-plic
- const: thead,c900-plic
- items:

43
Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml Normal file
View File

@ -0,0 +1,43 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-mswi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Sophgo sg2042 CLINT Machine-level Software Interrupt Device
maintainers:
- Inochi Amaoto <inochiama@outlook.com>
properties:
compatible:
items:
- enum:
- sophgo,sg2042-aclint-mswi
- const: thead,c900-aclint-mswi
reg:
maxItems: 1
interrupts-extended:
minItems: 1
maxItems: 4095
additionalProperties: false
required:
- compatible
- reg
- interrupts-extended
examples:
- |
interrupt-controller@94000000 {
compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
interrupts-extended = <&cpu1intc 3>,
<&cpu2intc 3>,
<&cpu3intc 3>,
<&cpu4intc 3>;
reg = <0x94000000 0x00010000>;
};
...

1
Documentation/devicetree/bindings/riscv/cpus.yaml
View File

@ -47,6 +47,7 @@ properties:
- sifive,u74-mc
- thead,c906
- thead,c910
- thead,c920
- const: riscv
- items:
- enum:

32
Documentation/devicetree/bindings/riscv/sophgo.yaml Normal file
View File

@ -0,0 +1,32 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/riscv/sophgo.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Sophgo SoC-based boards
maintainers:
- Chao Wei <chao.wei@sophgo.com>
- Chen Wang <unicorn_wang@outlook.com>
description:
Sophgo SoC-based boards
properties:
$nodename:
const: '/'
compatible:
oneOf:
- items:
- enum:
- milkv,duo
- const: sophgo,cv1800b
- items:
- enum:
- milkv,pioneer
- const: sophgo,sg2042
additionalProperties: true
...

1
Documentation/devicetree/bindings/timer/sifive,clint.yaml
View File

@ -37,6 +37,7 @@ properties:
- items:
- enum:
- allwinner,sun20i-d1-clint
- sophgo,cv1800b-clint
- thead,th1520-clint
- const: thead,c900-clint
- items:

43
Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml Normal file
View File

@ -0,0 +1,43 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/thead,c900-aclint-mtimer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Sophgo CLINT Timer
maintainers:
- Inochi Amaoto <inochiama@outlook.com>
properties:
compatible:
items:
- enum:
- sophgo,sg2042-aclint-mtimer
- const: thead,c900-aclint-mtimer
reg:
maxItems: 1
interrupts-extended:
minItems: 1
maxItems: 4095
additionalProperties: false
required:
- compatible
- reg
- interrupts-extended
examples:
- |
timer@ac000000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
interrupts-extended = <&cpu1intc 7>,
<&cpu2intc 7>,
<&cpu3intc 7>,
<&cpu4intc 7>;
reg = <0xac000000 0x00010000>;
};
...

4
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@ -877,6 +877,8 @@ patternProperties:
description: MikroElektronika d.o.o.
"^mikrotik,.*":
description: MikroTik
"^milkv,.*":
description: MilkV Technology Co., Ltd
"^miniand,.*":
description: Miniand Tech
"^minix,.*":
@ -1287,6 +1289,8 @@ patternProperties:
description: Solomon Systech Limited
"^sony,.*":
description: Sony Corporation
"^sophgo,.*":
description: Sophgo Technology Inc.
"^sourceparts,.*":
description: Source Parts Inc.
"^spansion,.*":

7
MAINTAINERS
View File

@ -20063,6 +20063,13 @@ F: drivers/char/sonypi.c
F: drivers/platform/x86/sony-laptop.c
F: include/linux/sony-laptop.h
SOPHGO DEVICETREES
M: Chao Wei <chao.wei@sophgo.com>
M: Chen Wang <unicorn_wang@outlook.com>
S: Maintained
F: arch/riscv/boot/dts/sophgo/
F: Documentation/devicetree/bindings/riscv/sophgo.yaml
SOUND
M: Jaroslav Kysela <perex@perex.cz>
M: Takashi Iwai <tiwai@suse.com>

5
arch/riscv/Kconfig.socs
View File

@ -22,6 +22,11 @@ config SOC_SIFIVE
help
This enables support for SiFive SoC platform hardware.
config ARCH_SOPHGO
bool "Sophgo SoCs"
help
This enables support for Sophgo SoC platform hardware.
config ARCH_STARFIVE
def_bool SOC_STARFIVE

1
arch/riscv/boot/dts/Makefile
View File

@ -4,6 +4,7 @@ subdir-y += canaan
subdir-y += microchip
subdir-y += renesas
subdir-y += sifive
subdir-y += sophgo
subdir-y += starfive
subdir-y += thead

15
arch/riscv/boot/dts/microchip/mpfs.dtsi
View File

@ -22,6 +22,9 @@
i-cache-size = <16384>;
reg = <0>;
riscv,isa = "rv64imac";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
"zihpm";
clocks = <&clkcfg CLK_CPU>;
status = "disabled";
@ -48,6 +51,9 @@
mmu-type = "riscv,sv39";
reg = <1>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
next-level-cache = <&cctrllr>;
@ -76,6 +82,9 @@
mmu-type = "riscv,sv39";
reg = <2>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
next-level-cache = <&cctrllr>;
@ -104,6 +113,9 @@
mmu-type = "riscv,sv39";
reg = <3>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
next-level-cache = <&cctrllr>;
@ -132,6 +144,9 @@
mmu-type = "riscv,sv39";
reg = <4>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
next-level-cache = <&cctrllr>;

15
arch/riscv/boot/dts/sifive/fu540-c000.dtsi
View File

@ -30,6 +30,9 @@
i-cache-size = <16384>;
reg = <0>;
riscv,isa = "rv64imac";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
"zihpm";
status = "disabled";
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
@ -53,6 +56,9 @@
mmu-type = "riscv,sv39";
reg = <1>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
tlb-split;
next-level-cache = <&l2cache>;
cpu1_intc: interrupt-controller {
@ -77,6 +83,9 @@
mmu-type = "riscv,sv39";
reg = <2>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
tlb-split;
next-level-cache = <&l2cache>;
cpu2_intc: interrupt-controller {
@ -101,6 +110,9 @@
mmu-type = "riscv,sv39";
reg = <3>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
tlb-split;
next-level-cache = <&l2cache>;
cpu3_intc: interrupt-controller {
@ -125,6 +137,9 @@
mmu-type = "riscv,sv39";
reg = <4>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
tlb-split;
next-level-cache = <&l2cache>;
cpu4_intc: interrupt-controller {

15
arch/riscv/boot/dts/sifive/fu740-c000.dtsi
View File

@ -31,6 +31,9 @@
next-level-cache = <&ccache>;
reg = <0x0>;
riscv,isa = "rv64imac";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
"zihpm";
status = "disabled";
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
@ -55,6 +58,9 @@
next-level-cache = <&ccache>;
reg = <0x1>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
tlb-split;
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
@ -79,6 +85,9 @@
next-level-cache = <&ccache>;
reg = <0x2>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
tlb-split;
cpu2_intc: interrupt-controller {
#interrupt-cells = <1>;
@ -103,6 +112,9 @@
next-level-cache = <&ccache>;
reg = <0x3>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
tlb-split;
cpu3_intc: interrupt-controller {
#interrupt-cells = <1>;
@ -127,6 +139,9 @@
next-level-cache = <&ccache>;
reg = <0x4>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
tlb-split;
cpu4_intc: interrupt-controller {
#interrupt-cells = <1>;

3
arch/riscv/boot/dts/sophgo/Makefile Normal file
View File

@ -0,0 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb

38
arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts Normal file
View File

@ -0,0 +1,38 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
*/
/dts-v1/;
#include "cv1800b.dtsi"
/ {
model = "Milk-V Duo";
compatible = "milkv,duo", "sophgo,cv1800b";
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x3f40000>;
};
};
&osc {
clock-frequency = <25000000>;
};
&uart0 {
status = "okay";
};

123
arch/riscv/boot/dts/sophgo/cv1800b.dtsi Normal file
View File

@ -0,0 +1,123 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
*/
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "sophgo,cv1800b";
#address-cells = <1>;
#size-cells = <1>;
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <25000000>;
cpu0: cpu@0 {
compatible = "thead,c906", "riscv";
device_type = "cpu";
reg = <0>;
d-cache-block-size = <64>;
d-cache-sets = <512>;
d-cache-size = <65536>;
i-cache-block-size = <64>;
i-cache-sets = <128>;
i-cache-size = <32768>;
mmu-type = "riscv,sv39";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
};
osc: oscillator {
compatible = "fixed-clock";
clock-output-names = "osc_25m";
#clock-cells = <0>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
#address-cells = <1>;
#size-cells = <1>;
dma-noncoherent;
ranges;
uart0: serial@4140000 {
compatible = "snps,dw-apb-uart";
reg = <0x04140000 0x100>;
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart1: serial@4150000 {
compatible = "snps,dw-apb-uart";
reg = <0x04150000 0x100>;
interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart2: serial@4160000 {
compatible = "snps,dw-apb-uart";
reg = <0x04160000 0x100>;
interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart3: serial@4170000 {
compatible = "snps,dw-apb-uart";
reg = <0x04170000 0x100>;
interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart4: serial@41c0000 {
compatible = "snps,dw-apb-uart";
reg = <0x041c0000 0x100>;
interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
plic: interrupt-controller@70000000 {
compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
reg = <0x70000000 0x4000000>;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
riscv,ndev = <101>;
};
clint: timer@74000000 {
compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
reg = <0x74000000 0x10000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
};
};
};

2000
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi Normal file
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File diff suppressed because it is too large Load Diff

19
arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts Normal file
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@ -0,0 +1,19 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
*/
#include "sg2042.dtsi"
/ {
model = "Milk-V Pioneer";
compatible = "milkv,pioneer", "sophgo,sg2042";
chosen {
stdout-path = "serial0";
};
};
&uart0 {
status = "okay";
};

325
arch/riscv/boot/dts/sophgo/sg2042.dtsi Normal file
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@ -0,0 +1,325 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
*/
/dts-v1/;
#include <dt-bindings/interrupt-controller/irq.h>
#include "sg2042-cpus.dtsi"
/ {
compatible = "sophgo,sg2042";
#address-cells = <2>;
#size-cells = <2>;
dma-noncoherent;
aliases {
serial0 = &uart0;
};
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
clint_mswi: interrupt-controller@7094000000 {
compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
interrupts-extended = <&cpu0_intc 3>,
<&cpu1_intc 3>,
<&cpu2_intc 3>,
<&cpu3_intc 3>,
<&cpu4_intc 3>,
<&cpu5_intc 3>,
<&cpu6_intc 3>,
<&cpu7_intc 3>,
<&cpu8_intc 3>,
<&cpu9_intc 3>,
<&cpu10_intc 3>,
<&cpu11_intc 3>,
<&cpu12_intc 3>,
<&cpu13_intc 3>,
<&cpu14_intc 3>,
<&cpu15_intc 3>,
<&cpu16_intc 3>,
<&cpu17_intc 3>,
<&cpu18_intc 3>,
<&cpu19_intc 3>,
<&cpu20_intc 3>,
<&cpu21_intc 3>,
<&cpu22_intc 3>,
<&cpu23_intc 3>,
<&cpu24_intc 3>,
<&cpu25_intc 3>,
<&cpu26_intc 3>,
<&cpu27_intc 3>,
<&cpu28_intc 3>,
<&cpu29_intc 3>,
<&cpu30_intc 3>,
<&cpu31_intc 3>,
<&cpu32_intc 3>,
<&cpu33_intc 3>,
<&cpu34_intc 3>,
<&cpu35_intc 3>,
<&cpu36_intc 3>,
<&cpu37_intc 3>,
<&cpu38_intc 3>,
<&cpu39_intc 3>,
<&cpu40_intc 3>,
<&cpu41_intc 3>,
<&cpu42_intc 3>,
<&cpu43_intc 3>,
<&cpu44_intc 3>,
<&cpu45_intc 3>,
<&cpu46_intc 3>,
<&cpu47_intc 3>,
<&cpu48_intc 3>,
<&cpu49_intc 3>,
<&cpu50_intc 3>,
<&cpu51_intc 3>,
<&cpu52_intc 3>,
<&cpu53_intc 3>,
<&cpu54_intc 3>,
<&cpu55_intc 3>,
<&cpu56_intc 3>,
<&cpu57_intc 3>,
<&cpu58_intc 3>,
<&cpu59_intc 3>,
<&cpu60_intc 3>,
<&cpu61_intc 3>,
<&cpu62_intc 3>,
<&cpu63_intc 3>;
};
clint_mtimer0: timer@70ac000000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac000000 0x00000000 0x00007ff8>;
interrupts-extended = <&cpu0_intc 7>,
<&cpu1_intc 7>,
<&cpu2_intc 7>,
<&cpu3_intc 7>;
};
clint_mtimer1: timer@70ac010000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac010000 0x00000000 0x00007ff8>;
interrupts-extended = <&cpu4_intc 7>,
<&cpu5_intc 7>,
<&cpu6_intc 7>,
<&cpu7_intc 7>;
};
clint_mtimer2: timer@70ac020000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac020000 0x00000000 0x00007ff8>;
interrupts-extended = <&cpu8_intc 7>,
<&cpu9_intc 7>,
<&cpu10_intc 7>,
<&cpu11_intc 7>;
};
clint_mtimer3: timer@70ac030000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac030000 0x00000000 0x00007ff8>;
interrupts-extended = <&cpu12_intc 7>,
<&cpu13_intc 7>,
<&cpu14_intc 7>,
<&cpu15_intc 7>;
};
clint_mtimer4: timer@70ac040000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac040000 0x00000000 0x00007ff8>;
interrupts-extended = <&cpu16_intc 7>,
<&cpu17_intc 7>,
<&cpu18_intc 7>,
<&cpu19_intc 7>;
};
clint_mtimer5: timer@70ac050000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac050000 0x00000000 0x00007ff8>;
interrupts-extended = <&cpu20_intc 7>,
<&cpu21_intc 7>,
<&cpu22_intc 7>,
<&cpu23_intc 7>;
};
clint_mtimer6: timer@70ac060000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac060000 0x00000000 0x00007ff8>;
interrupts-extended = <&cpu24_intc 7>,
<&cpu25_intc 7>,
<&cpu26_intc 7>,
<&cpu27_intc 7>;
};
clint_mtimer7: timer@70ac070000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac070000 0x00000000 0x00007ff8>;
interrupts-extended = <&cpu28_intc 7>,
<&cpu29_intc 7>,
<&cpu30_intc 7>,
<&cpu31_intc 7>;
};
clint_mtimer8: timer@70ac080000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac080000 0x00000000 0x00007ff8>;
interrupts-extended = <&cpu32_intc 7>,
<&cpu33_intc 7>,
<&cpu34_intc 7>,
<&cpu35_intc 7>;
};
clint_mtimer9: timer@70ac090000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac090000 0x00000000 0x00007ff8>;
interrupts-extended = <&cpu36_intc 7>,
<&cpu37_intc 7>,
<&cpu38_intc 7>,
<&cpu39_intc 7>;
};
clint_mtimer10: timer@70ac0a0000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac0a0000 0x00000000 0x00007ff8>;
interrupts-extended = <&cpu40_intc 7>,
<&cpu41_intc 7>,
<&cpu42_intc 7>,
<&cpu43_intc 7>;
};
clint_mtimer11: timer@70ac0b0000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac0b0000 0x00000000 0x00007ff8>;
interrupts-extended = <&cpu44_intc 7>,
<&cpu45_intc 7>,
<&cpu46_intc 7>,
<&cpu47_intc 7>;
};
clint_mtimer12: timer@70ac0c0000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac0c0000 0x00000000 0x00007ff8>;
interrupts-extended = <&cpu48_intc 7>,
<&cpu49_intc 7>,
<&cpu50_intc 7>,
<&cpu51_intc 7>;
};
clint_mtimer13: timer@70ac0d0000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac0d0000 0x00000000 0x00007ff8>;
interrupts-extended = <&cpu52_intc 7>,
<&cpu53_intc 7>,
<&cpu54_intc 7>,
<&cpu55_intc 7>;
};
clint_mtimer14: timer@70ac0e0000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac0e0000 0x00000000 0x00007ff8>;
interrupts-extended = <&cpu56_intc 7>,
<&cpu57_intc 7>,
<&cpu58_intc 7>,
<&cpu59_intc 7>;
};
clint_mtimer15: timer@70ac0f0000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac0f0000 0x00000000 0x00007ff8>;
interrupts-extended = <&cpu60_intc 7>,
<&cpu61_intc 7>,
<&cpu62_intc 7>,
<&cpu63_intc 7>;
};
intc: interrupt-controller@7090000000 {
compatible = "sophgo,sg2042-plic", "thead,c900-plic";
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x00000070 0x90000000 0x00000000 0x04000000>;
interrupt-controller;
interrupts-extended =
<&cpu0_intc 11>, <&cpu0_intc 9>,
<&cpu1_intc 11>, <&cpu1_intc 9>,
<&cpu2_intc 11>, <&cpu2_intc 9>,
<&cpu3_intc 11>, <&cpu3_intc 9>,
<&cpu4_intc 11>, <&cpu4_intc 9>,
<&cpu5_intc 11>, <&cpu5_intc 9>,
<&cpu6_intc 11>, <&cpu6_intc 9>,
<&cpu7_intc 11>, <&cpu7_intc 9>,
<&cpu8_intc 11>, <&cpu8_intc 9>,
<&cpu9_intc 11>, <&cpu9_intc 9>,
<&cpu10_intc 11>, <&cpu10_intc 9>,
<&cpu11_intc 11>, <&cpu11_intc 9>,
<&cpu12_intc 11>, <&cpu12_intc 9>,
<&cpu13_intc 11>, <&cpu13_intc 9>,
<&cpu14_intc 11>, <&cpu14_intc 9>,
<&cpu15_intc 11>, <&cpu15_intc 9>,
<&cpu16_intc 11>, <&cpu16_intc 9>,
<&cpu17_intc 11>, <&cpu17_intc 9>,
<&cpu18_intc 11>, <&cpu18_intc 9>,
<&cpu19_intc 11>, <&cpu19_intc 9>,
<&cpu20_intc 11>, <&cpu20_intc 9>,
<&cpu21_intc 11>, <&cpu21_intc 9>,
<&cpu22_intc 11>, <&cpu22_intc 9>,
<&cpu23_intc 11>, <&cpu23_intc 9>,
<&cpu24_intc 11>, <&cpu24_intc 9>,
<&cpu25_intc 11>, <&cpu25_intc 9>,
<&cpu26_intc 11>, <&cpu26_intc 9>,
<&cpu27_intc 11>, <&cpu27_intc 9>,
<&cpu28_intc 11>, <&cpu28_intc 9>,
<&cpu29_intc 11>, <&cpu29_intc 9>,
<&cpu30_intc 11>, <&cpu30_intc 9>,
<&cpu31_intc 11>, <&cpu31_intc 9>,
<&cpu32_intc 11>, <&cpu32_intc 9>,
<&cpu33_intc 11>, <&cpu33_intc 9>,
<&cpu34_intc 11>, <&cpu34_intc 9>,
<&cpu35_intc 11>, <&cpu35_intc 9>,
<&cpu36_intc 11>, <&cpu36_intc 9>,
<&cpu37_intc 11>, <&cpu37_intc 9>,
<&cpu38_intc 11>, <&cpu38_intc 9>,
<&cpu39_intc 11>, <&cpu39_intc 9>,
<&cpu40_intc 11>, <&cpu40_intc 9>,
<&cpu41_intc 11>, <&cpu41_intc 9>,
<&cpu42_intc 11>, <&cpu42_intc 9>,
<&cpu43_intc 11>, <&cpu43_intc 9>,
<&cpu44_intc 11>, <&cpu44_intc 9>,
<&cpu45_intc 11>, <&cpu45_intc 9>,
<&cpu46_intc 11>, <&cpu46_intc 9>,
<&cpu47_intc 11>, <&cpu47_intc 9>,
<&cpu48_intc 11>, <&cpu48_intc 9>,
<&cpu49_intc 11>, <&cpu49_intc 9>,
<&cpu50_intc 11>, <&cpu50_intc 9>,
<&cpu51_intc 11>, <&cpu51_intc 9>,
<&cpu52_intc 11>, <&cpu52_intc 9>,
<&cpu53_intc 11>, <&cpu53_intc 9>,
<&cpu54_intc 11>, <&cpu54_intc 9>,
<&cpu55_intc 11>, <&cpu55_intc 9>,
<&cpu56_intc 11>, <&cpu56_intc 9>,
<&cpu57_intc 11>, <&cpu57_intc 9>,
<&cpu58_intc 11>, <&cpu58_intc 9>,
<&cpu59_intc 11>, <&cpu59_intc 9>,
<&cpu60_intc 11>, <&cpu60_intc 9>,
<&cpu61_intc 11>, <&cpu61_intc 9>,
<&cpu62_intc 11>, <&cpu62_intc 9>,
<&cpu63_intc 11>, <&cpu63_intc 9>;
riscv,ndev = <224>;
};
uart0: serial@7040000000 {
compatible = "snps,dw-apb-uart";
reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
interrupt-parent = <&intc>;
interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <500000000>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
};
};

6
arch/riscv/boot/dts/starfive/jh7100.dtsi
View File

@ -33,6 +33,9 @@
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
tlb-split;
cpu0_intc: interrupt-controller {
@ -58,6 +61,9 @@
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
tlb-split;
cpu1_intc: interrupt-controller {

4
arch/riscv/boot/dts/starfive/jh7110-pinfunc.h
View File

@ -240,8 +240,8 @@
#define GPI_SYS_MCLK_EXT 30
#define GPI_SYS_I2SRX_BCLK 31
#define GPI_SYS_I2SRX_LRCK 32
#define GPI_SYS_I2STX0_BCLK 33
#define GPI_SYS_I2STX0_LRCK 34
#define GPI_SYS_I2STX1_BCLK 33
#define GPI_SYS_I2STX1_LRCK 34
#define GPI_SYS_TDM_CLK 35
#define GPI_SYS_TDM_RXD 36
#define GPI_SYS_TDM_SYNC 37

111
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
View File

@ -40,6 +40,33 @@
gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
priority = <224>;
};
pwmdac_codec: pwmdac-codec {
compatible = "linux,spdif-dit";
#sound-dai-cells = <0>;
};
sound-pwmdac {
compatible = "simple-audio-card";
simple-audio-card,name = "StarFive-PWMDAC-Sound-Card";
#address-cells = <1>;
#size-cells = <0>;
simple-audio-card,dai-link@0 {
reg = <0>;
format = "left_j";
bitclock-master = <&sndcpu0>;
frame-master = <&sndcpu0>;
sndcpu0: cpu {
sound-dai = <&pwmdac>;
};
codec {
sound-dai = <&pwmdac_codec>;
};
};
};
};
&dvp_clk {
@ -203,8 +230,28 @@
status = "okay";
};
&i2srx {
pinctrl-names = "default";
pinctrl-0 = <&i2srx_pins>;
status = "okay";
};
&i2stx0 {
pinctrl-names = "default";
pinctrl-0 = <&mclk_ext_pins>;
status = "okay";
};
&i2stx1 {
pinctrl-names = "default";
pinctrl-0 = <&i2stx1_pins>;
status = "okay";
};
&mmc0 {
max-frequency = <100000000>;
assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
assigned-clock-rates = <50000000>;
bus-width = <8>;
cap-mmc-highspeed;
mmc-ddr-1_8v;
@ -221,6 +268,8 @@
&mmc1 {
max-frequency = <100000000>;
assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
assigned-clock-rates = <50000000>;
bus-width = <4>;
no-sdio;
no-mmc;
@ -232,6 +281,12 @@
status = "okay";
};
&pwmdac {
pinctrl-names = "default";
pinctrl-0 = <&pwmdac_pins>;
status = "okay";
};
&qspi {
#address-cells = <1>;
#size-cells = <0>;
@ -337,6 +392,46 @@
};
};
i2srx_pins: i2srx-0 {
clk-sd-pins {
pinmux = <GPIOMUX(38, GPOUT_LOW,
GPOEN_DISABLE,
GPI_SYS_I2SRX_BCLK)>,
<GPIOMUX(63, GPOUT_LOW,
GPOEN_DISABLE,
GPI_SYS_I2SRX_LRCK)>,
<GPIOMUX(38, GPOUT_LOW,
GPOEN_DISABLE,
GPI_SYS_I2STX1_BCLK)>,
<GPIOMUX(63, GPOUT_LOW,
GPOEN_DISABLE,
GPI_SYS_I2STX1_LRCK)>,
<GPIOMUX(61, GPOUT_LOW,
GPOEN_DISABLE,
GPI_SYS_I2SRX_SDIN0)>;
input-enable;
};
};
i2stx1_pins: i2stx1-0 {
sd-pins {
pinmux = <GPIOMUX(44, GPOUT_SYS_I2STX1_SDO0,
GPOEN_ENABLE,
GPI_NONE)>;
bias-disable;
input-disable;
};
};
mclk_ext_pins: mclk-ext-0 {
mclk-ext-pins {
pinmux = <GPIOMUX(4, GPOUT_LOW,
GPOEN_DISABLE,
GPI_SYS_MCLK_EXT)>;
input-enable;
};
};
mmc0_pins: mmc0-0 {
rst-pins {
pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
@ -402,6 +497,22 @@
};
};
pwmdac_pins: pwmdac-0 {
pwmdac-pins {
pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT,
GPOEN_ENABLE,
GPI_NONE)>,
<GPIOMUX(34, GPOUT_SYS_PWMDAC_RIGHT,
GPOEN_ENABLE,
GPI_NONE)>;
bias-disable;
drive-strength = <2>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};
spi0_pins: spi0-0 {
mosi-pins {
pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,

93
arch/riscv/boot/dts/starfive/jh7110.dtsi
View File

@ -28,6 +28,9 @@
i-cache-size = <16384>;
next-level-cache = <&ccache>;
riscv,isa = "rv64imac_zba_zbb";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "c", "zba", "zbb", "zicntr", "zicsr",
"zifencei", "zihpm";
status = "disabled";
cpu0_intc: interrupt-controller {
@ -54,6 +57,9 @@
mmu-type = "riscv,sv39";
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
"zicsr", "zifencei", "zihpm";
tlb-split;
operating-points-v2 = <&cpu_opp>;
clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
@ -84,6 +90,9 @@
mmu-type = "riscv,sv39";
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
"zicsr", "zifencei", "zihpm";
tlb-split;
operating-points-v2 = <&cpu_opp>;
clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
@ -114,6 +123,9 @@
mmu-type = "riscv,sv39";
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
"zicsr", "zifencei", "zihpm";
tlb-split;
operating-points-v2 = <&cpu_opp>;
clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
@ -144,6 +156,9 @@
mmu-type = "riscv,sv39";
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
"zicsr", "zifencei", "zihpm";
tlb-split;
operating-points-v2 = <&cpu_opp>;
clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
@ -512,6 +527,43 @@
status = "disabled";
};
i2srx: i2s@100e0000 {
compatible = "starfive,jh7110-i2srx";
reg = <0x0 0x100e0000 0x0 0x1000>;
clocks = <&syscrg JH7110_SYSCLK_I2SRX_BCLK_MST>,
<&syscrg JH7110_SYSCLK_I2SRX_APB>,
<&syscrg JH7110_SYSCLK_MCLK>,
<&syscrg JH7110_SYSCLK_MCLK_INNER>,
<&mclk_ext>,
<&syscrg JH7110_SYSCLK_I2SRX_BCLK>,
<&syscrg JH7110_SYSCLK_I2SRX_LRCK>,
<&i2srx_bclk_ext>,
<&i2srx_lrck_ext>;
clock-names = "i2sclk", "apb", "mclk",
"mclk_inner", "mclk_ext", "bclk",
"lrck", "bclk_ext", "lrck_ext";
resets = <&syscrg JH7110_SYSRST_I2SRX_APB>,
<&syscrg JH7110_SYSRST_I2SRX_BCLK>;
dmas = <0>, <&dma 24>;
dma-names = "tx", "rx";
starfive,syscon = <&sys_syscon 0x18 0x2>;
#sound-dai-cells = <0>;
status = "disabled";
};
pwmdac: pwmdac@100b0000 {
compatible = "starfive,jh7110-pwmdac";
reg = <0x0 0x100b0000 0x0 0x1000>;
clocks = <&syscrg JH7110_SYSCLK_PWMDAC_APB>,
<&syscrg JH7110_SYSCLK_PWMDAC_CORE>;
clock-names = "apb", "core";
resets = <&syscrg JH7110_SYSRST_PWMDAC_APB>;
dmas = <&dma 22>;
dma-names = "tx";
#sound-dai-cells = <0>;
status = "disabled";
};
usb0: usb@10100000 {
compatible = "starfive,jh7110-usb";
ranges = <0x0 0x0 0x10100000 0x100000>;
@ -736,6 +788,47 @@
status = "disabled";
};
i2stx0: i2s@120b0000 {
compatible = "starfive,jh7110-i2stx0";
reg = <0x0 0x120b0000 0x0 0x1000>;
clocks = <&syscrg JH7110_SYSCLK_I2STX0_BCLK_MST>,
<&syscrg JH7110_SYSCLK_I2STX0_APB>,
<&syscrg JH7110_SYSCLK_MCLK>,
<&syscrg JH7110_SYSCLK_MCLK_INNER>,
<&mclk_ext>;
clock-names = "i2sclk", "apb", "mclk",
"mclk_inner","mclk_ext";
resets = <&syscrg JH7110_SYSRST_I2STX0_APB>,
<&syscrg JH7110_SYSRST_I2STX0_BCLK>;
dmas = <&dma 47>;
dma-names = "tx";
#sound-dai-cells = <0>;
status = "disabled";
};
i2stx1: i2s@120c0000 {
compatible = "starfive,jh7110-i2stx1";
reg = <0x0 0x120c0000 0x0 0x1000>;
clocks = <&syscrg JH7110_SYSCLK_I2STX1_BCLK_MST>,
<&syscrg JH7110_SYSCLK_I2STX1_APB>,
<&syscrg JH7110_SYSCLK_MCLK>,
<&syscrg JH7110_SYSCLK_MCLK_INNER>,
<&mclk_ext>,
<&syscrg JH7110_SYSCLK_I2STX1_BCLK>,
<&syscrg JH7110_SYSCLK_I2STX1_LRCK>,
<&i2stx_bclk_ext>,
<&i2stx_lrck_ext>;
clock-names = "i2sclk", "apb", "mclk",
"mclk_inner", "mclk_ext", "bclk",
"lrck", "bclk_ext", "lrck_ext";
resets = <&syscrg JH7110_SYSRST_I2STX1_APB>,
<&syscrg JH7110_SYSRST_I2STX1_BCLK>;
dmas = <&dma 48>;
dma-names = "tx";
#sound-dai-cells = <0>;
status = "disabled";
};
sfctemp: temperature-sensor@120e0000 {
compatible = "starfive,jh7110-temp";
reg = <0x0 0x120e0000 0x0 0x10000>;

3
arch/riscv/configs/defconfig
View File

@ -27,10 +27,11 @@ CONFIG_EXPERT=y
CONFIG_PROFILING=y
CONFIG_SOC_MICROCHIP_POLARFIRE=y
CONFIG_ARCH_RENESAS=y
CONFIG_ARCH_THEAD=y
CONFIG_SOC_SIFIVE=y
CONFIG_ARCH_SOPHGO=y
CONFIG_SOC_STARFIVE=y
CONFIG_ARCH_SUNXI=y
CONFIG_ARCH_THEAD=y
CONFIG_SOC_VIRT=y
CONFIG_SMP=y
CONFIG_HOTPLUG_CPU=y