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Merge branch 'pci/controller/cadence'
- Add j721e DT and driver support for 'num-lanes' for devices that support x1, x2, or x4 Links (Matt Ranostay) - Add j721e DT compatible strings and driver support for j784s4 (Matt Ranostay) - Make TI J721E Kconfig depend on ARCH_K3 since the hardware is specific to those TI SoC parts (Peter Robinson) * pci/controller/cadence: PCI: j721e: Make TI J721E depend on ARCH_K3 PCI: j721e: Add TI J784S4 PCIe configuration PCI: j721e: Add PCIe 4x lane selection support PCI: j721e: Add per platform maximum lane settings dt-bindings: PCI: ti,j721e-pci-*: Add j784s4-pci-* compatible strings dt-bindings: PCI: ti,j721e-pci-*: Add checks for num-lanes
This commit is contained in:
Bjorn Helgaas
commit
78fe51fcb4
@ -10,13 +10,11 @@ title: TI J721E PCI EP (PCIe Wrapper)
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maintainers:
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- Kishon Vijay Abraham I <kishon@ti.com>
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allOf:
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- $ref: cdns-pcie-ep.yaml#
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properties:
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compatible:
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oneOf:
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- const: ti,j721e-pcie-ep
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- const: ti,j784s4-pcie-ep
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- description: PCIe EP controller in AM64
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items:
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- const: ti,am64-pcie-ep
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@ -65,6 +63,41 @@ properties:
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items:
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- const: link_state
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allOf:
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- $ref: cdns-pcie-ep.yaml#
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- if:
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properties:
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compatible:
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enum:
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- ti,am64-pcie-ep
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then:
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properties:
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num-lanes:
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const: 1
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- if:
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properties:
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compatible:
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enum:
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- ti,j7200-pcie-ep
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- ti,j721e-pcie-ep
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then:
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properties:
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num-lanes:
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minimum: 1
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maximum: 2
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- if:
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properties:
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compatible:
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enum:
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- ti,j784s4-pcie-ep
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then:
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properties:
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num-lanes:
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minimum: 1
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maximum: 4
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required:
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- compatible
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- reg
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@ -10,13 +10,11 @@ title: TI J721E PCI Host (PCIe Wrapper)
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maintainers:
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- Kishon Vijay Abraham I <kishon@ti.com>
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allOf:
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- $ref: cdns-pcie-host.yaml#
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properties:
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compatible:
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oneOf:
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- const: ti,j721e-pcie-host
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- const: ti,j784s4-pcie-host
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- description: PCIe controller in AM64
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items:
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- const: ti,am64-pcie-host
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@ -94,6 +92,41 @@ properties:
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interrupts:
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maxItems: 1
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allOf:
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- $ref: cdns-pcie-host.yaml#
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- if:
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properties:
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compatible:
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enum:
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- ti,am64-pcie-host
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then:
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properties:
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num-lanes:
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const: 1
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- if:
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properties:
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compatible:
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enum:
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- ti,j7200-pcie-host
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- ti,j721e-pcie-host
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then:
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properties:
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num-lanes:
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minimum: 1
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maximum: 2
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- if:
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properties:
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compatible:
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enum:
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- ti,j784s4-pcie-host
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then:
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properties:
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num-lanes:
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minimum: 1
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maximum: 4
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required:
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- compatible
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- reg
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@ -47,6 +47,7 @@ config PCI_J721E
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config PCI_J721E_HOST
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bool "TI J721E PCIe controller (host mode)"
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depends on ARCH_K3 || COMPILE_TEST
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depends on OF
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select PCIE_CADENCE_HOST
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select PCI_J721E
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@ -57,6 +58,7 @@ config PCI_J721E_HOST
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config PCI_J721E_EP
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bool "TI J721E PCIe controller (endpoint mode)"
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depends on ARCH_K3 || COMPILE_TEST
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depends on OF
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depends on PCI_ENDPOINT
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select PCIE_CADENCE_EP
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@ -42,18 +42,16 @@ enum link_status {
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};
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#define J721E_MODE_RC BIT(7)
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#define LANE_COUNT_MASK BIT(8)
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#define LANE_COUNT(n) ((n) << 8)
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#define GENERATION_SEL_MASK GENMASK(1, 0)
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#define MAX_LANES 2
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struct j721e_pcie {
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struct cdns_pcie *cdns_pcie;
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struct clk *refclk;
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u32 mode;
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u32 num_lanes;
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u32 max_lanes;
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void __iomem *user_cfg_base;
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void __iomem *intd_cfg_base;
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u32 linkdown_irq_regfield;
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@ -71,6 +69,7 @@ struct j721e_pcie_data {
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unsigned int quirk_disable_flr:1;
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u32 linkdown_irq_regfield;
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unsigned int byte_access_allowed:1;
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unsigned int max_lanes;
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};
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static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
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@ -206,11 +205,15 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
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{
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struct device *dev = pcie->cdns_pcie->dev;
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u32 lanes = pcie->num_lanes;
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u32 mask = BIT(8);
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u32 val = 0;
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int ret;
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if (pcie->max_lanes == 4)
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mask = GENMASK(9, 8);
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val = LANE_COUNT(lanes - 1);
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ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val);
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ret = regmap_update_bits(syscon, offset, mask, val);
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if (ret)
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dev_err(dev, "failed to set link count\n");
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@ -290,11 +293,13 @@ static const struct j721e_pcie_data j721e_pcie_rc_data = {
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.quirk_retrain_flag = true,
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.byte_access_allowed = false,
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.linkdown_irq_regfield = LINK_DOWN,
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.max_lanes = 2,
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};
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static const struct j721e_pcie_data j721e_pcie_ep_data = {
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.mode = PCI_MODE_EP,
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.linkdown_irq_regfield = LINK_DOWN,
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.max_lanes = 2,
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};
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static const struct j721e_pcie_data j7200_pcie_rc_data = {
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@ -302,23 +307,41 @@ static const struct j721e_pcie_data j7200_pcie_rc_data = {
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.quirk_detect_quiet_flag = true,
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.linkdown_irq_regfield = J7200_LINK_DOWN,
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.byte_access_allowed = true,
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.max_lanes = 2,
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};
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static const struct j721e_pcie_data j7200_pcie_ep_data = {
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.mode = PCI_MODE_EP,
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.quirk_detect_quiet_flag = true,
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.quirk_disable_flr = true,
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.max_lanes = 2,
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};
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static const struct j721e_pcie_data am64_pcie_rc_data = {
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.mode = PCI_MODE_RC,
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.linkdown_irq_regfield = J7200_LINK_DOWN,
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.byte_access_allowed = true,
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.max_lanes = 1,
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};
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static const struct j721e_pcie_data am64_pcie_ep_data = {
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.mode = PCI_MODE_EP,
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.linkdown_irq_regfield = J7200_LINK_DOWN,
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.max_lanes = 1,
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};
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static const struct j721e_pcie_data j784s4_pcie_rc_data = {
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.mode = PCI_MODE_RC,
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.quirk_retrain_flag = true,
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.byte_access_allowed = false,
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.linkdown_irq_regfield = LINK_DOWN,
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.max_lanes = 4,
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};
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static const struct j721e_pcie_data j784s4_pcie_ep_data = {
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.mode = PCI_MODE_EP,
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.linkdown_irq_regfield = LINK_DOWN,
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.max_lanes = 4,
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};
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static const struct of_device_id of_j721e_pcie_match[] = {
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@ -346,6 +369,14 @@ static const struct of_device_id of_j721e_pcie_match[] = {
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.compatible = "ti,am64-pcie-ep",
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.data = &am64_pcie_ep_data,
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},
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{
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.compatible = "ti,j784s4-pcie-host",
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.data = &j784s4_pcie_rc_data,
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},
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{
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.compatible = "ti,j784s4-pcie-ep",
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.data = &j784s4_pcie_ep_data,
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},
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{},
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};
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@ -432,9 +463,13 @@ static int j721e_pcie_probe(struct platform_device *pdev)
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pcie->user_cfg_base = base;
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ret = of_property_read_u32(node, "num-lanes", &num_lanes);
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if (ret || num_lanes > MAX_LANES)
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if (ret || num_lanes > data->max_lanes) {
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dev_warn(dev, "num-lanes property not provided or invalid, setting num-lanes to 1\n");
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num_lanes = 1;
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}
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pcie->num_lanes = num_lanes;
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pcie->max_lanes = data->max_lanes;
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if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
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return -EINVAL;
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