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A collection of clk driver fixes and one core clk API fix
- Fix stm32 clk data to avoid a crash early on - Fix a randconfig build error in HiSilicon clk driver - Avoid an oops at boot on Qualcomm MSM8936 SoCs due to an improper consolidation of structs - Fix imbalanced disabling of the unused MMC clock on Tegra210 Jetson Nano - Plug a memory leak in devm_clk_bulk_get_all() unwind path -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmEI+6gRHHNib3lkQGtl cm5lbC5vcmcACgkQrQKIl8bklSVFpw//VmoawOGyRfva5tPojVF9rJMIympxdMHa jsGcCqDFCH9MBIEszD8oBnocI+J4ejlwVSMRadav2vv8+HcXI2E3GgkYae1J4J/y dYfyeQNL/VQbObkgXnh+dsCqw84FvuB+LVgLTWZ386BkFPc9brbszf5Jumsy7mQ5 KWvo9eEjlJkbYDCJj3z7I5xSr4ATaFgWTf4UW6pCuTuD4nUY7b4MaOA3rcMHBN/y bdX3YxfkRkMflHofi63p/P39eHNXbdOFzTxgEK+sYHIu6NxWDBw9Blm7yOER+pIT voryNw29P8bbe6Fx2eRMXV3LDRLhvIuTE7TzsRMswbydscCdJX/CNrdR572NH684 aL+S/ykcTj15wMfxieIEm2Zq6wDjT6IkRr3NIzbD/BpUKN5JcG9keKoxL3uGYkZd 52mrrBhHPQBRr62aafUThQf/mdCmeFOAPIABAQXyI5xJfwcE5e292npMqQzrcQZz NgP77d8NI4GQXlJLI/Yc6tR9NC9tY56igU4VG3AAOeUhK/bqLyDJyNeBB+1V63qA IN/bvfWb89b3Gnsah1zZQZXJPw8Z1xjrQBb1Nj1Ouw5jBlnCn74E/9jTsLc4543b 5P8TW2hnqbf9bFeZhK6yWjY2o+S5ynC7mVS3eos+HUX5F8/TY27bidot3tOv70il f6LiX1IRb54= =5bwG -----END PGP SIGNATURE----- Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk fixes from Stephen Boyd: "A collection of clk driver fixes and one core clk API fix: - Fix stm32 clk data to avoid a crash early on - Fix a randconfig build error in HiSilicon clk driver - Avoid an oops at boot on Qualcomm MSM8936 SoCs due to an improper consolidation of structs - Fix imbalanced disabling of the unused MMC clock on Tegra210 Jetson Nano - Plug a memory leak in devm_clk_bulk_get_all() unwind path" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: fix leak on devm_clk_bulk_get_all() unwind clk: tegra: Implement disable_unused() of tegra_clk_sdmmc_mux_ops clk: qcom: smd-rpm: Fix MSM8936 RPM_SMD_PCNOC_A_CLK clk: hisilicon: hi3559a: select RESET_HISI clk: stm32f4: fix post divisor setup for I2S/SAI PLLs
This commit is contained in:
commit
785ee98349
@ -92,13 +92,20 @@ int __must_check devm_clk_bulk_get_optional(struct device *dev, int num_clks,
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}
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EXPORT_SYMBOL_GPL(devm_clk_bulk_get_optional);
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static void devm_clk_bulk_release_all(struct device *dev, void *res)
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{
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struct clk_bulk_devres *devres = res;
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clk_bulk_put_all(devres->num_clks, devres->clks);
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}
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int __must_check devm_clk_bulk_get_all(struct device *dev,
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struct clk_bulk_data **clks)
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{
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struct clk_bulk_devres *devres;
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int ret;
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devres = devres_alloc(devm_clk_bulk_release,
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devres = devres_alloc(devm_clk_bulk_release_all,
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sizeof(*devres), GFP_KERNEL);
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if (!devres)
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return -ENOMEM;
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@ -526,7 +526,7 @@ struct stm32f4_pll {
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struct stm32f4_pll_post_div_data {
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int idx;
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u8 pll_num;
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int pll_idx;
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const char *name;
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const char *parent;
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u8 flag;
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@ -557,13 +557,13 @@ static const struct clk_div_table post_divr_table[] = {
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#define MAX_POST_DIV 3
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static const struct stm32f4_pll_post_div_data post_div_data[MAX_POST_DIV] = {
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{ CLK_I2SQ_PDIV, PLL_I2S, "plli2s-q-div", "plli2s-q",
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{ CLK_I2SQ_PDIV, PLL_VCO_I2S, "plli2s-q-div", "plli2s-q",
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CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 0, 5, 0, NULL},
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{ CLK_SAIQ_PDIV, PLL_SAI, "pllsai-q-div", "pllsai-q",
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{ CLK_SAIQ_PDIV, PLL_VCO_SAI, "pllsai-q-div", "pllsai-q",
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CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 8, 5, 0, NULL },
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{ NO_IDX, PLL_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT,
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{ NO_IDX, PLL_VCO_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT,
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STM32F4_RCC_DCKCFGR, 16, 2, 0, post_divr_table },
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};
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@ -1774,7 +1774,7 @@ static void __init stm32f4_rcc_init(struct device_node *np)
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post_div->width,
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post_div->flag_div,
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post_div->div_table,
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clks[post_div->pll_num],
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clks[post_div->pll_idx],
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&stm32f4_clk_lock);
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if (post_div->idx != NO_IDX)
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@ -18,6 +18,7 @@ config COMMON_CLK_HI3519
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config COMMON_CLK_HI3559A
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bool "Hi3559A Clock Driver"
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depends on ARCH_HISI || COMPILE_TEST
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select RESET_HISI
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default ARCH_HISI
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help
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Build the clock driver for hi3559a.
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@ -467,7 +467,7 @@ DEFINE_CLK_SMD_RPM(msm8936, sysmmnoc_clk, sysmmnoc_a_clk, QCOM_SMD_RPM_BUS_CLK,
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static struct clk_smd_rpm *msm8936_clks[] = {
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[RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
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[RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_clk,
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[RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk,
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[RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
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[RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
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[RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
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@ -194,6 +194,15 @@ static void clk_sdmmc_mux_disable(struct clk_hw *hw)
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gate_ops->disable(gate_hw);
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}
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static void clk_sdmmc_mux_disable_unused(struct clk_hw *hw)
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{
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struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
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const struct clk_ops *gate_ops = sdmmc_mux->gate_ops;
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struct clk_hw *gate_hw = &sdmmc_mux->gate.hw;
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gate_ops->disable_unused(gate_hw);
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}
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static void clk_sdmmc_mux_restore_context(struct clk_hw *hw)
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{
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struct clk_hw *parent = clk_hw_get_parent(hw);
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@ -218,6 +227,7 @@ static const struct clk_ops tegra_clk_sdmmc_mux_ops = {
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.is_enabled = clk_sdmmc_mux_is_enabled,
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.enable = clk_sdmmc_mux_enable,
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.disable = clk_sdmmc_mux_disable,
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.disable_unused = clk_sdmmc_mux_disable_unused,
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.restore_context = clk_sdmmc_mux_restore_context,
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};
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