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Merge patch series "riscv: enable lockless lockref implementation"
Jisheng Zhang <jszhang@kernel.org> says: This series selects ARCH_USE_CMPXCHG_LOCKREF to enable the cmpxchg-based lockless lockref implementation for riscv. Then, implement arch_cmpxchg64_{relaxed|acquire|release}. After patch1: Using Linus' test case[1] on TH1520 platform, I see a 11.2% improvement. On JH7110 platform, I see 12.0% improvement. After patch2: on both TH1520 and JH7110 platforms, I didn't see obvious performance improvement with Linus' test case [1]. IMHO, this may be related with the fence and lr.d/sc.d hw implementations. In theory, lr/sc without fence could give performance improvement over lr/sc plus fence, so add the code here to leave performance improvement room on newer HW platforms. * b4-shazam-merge: riscv: cmpxchg: implement arch_cmpxchg64_{relaxed|acquire|release} riscv: select ARCH_USE_CMPXCHG_LOCKREF Link: http://marc.info/?l=linux-fsdevel&m=137782380714721&w=4 [1] Link: https://lore.kernel.org/r/20240325111038.1700-1-jszhang@kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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commit
7845f52256
@ -57,6 +57,7 @@ config RISCV
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select ARCH_SUPPORTS_PAGE_TABLE_CHECK if MMU
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select ARCH_SUPPORTS_PER_VMA_LOCK if MMU
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select ARCH_SUPPORTS_SHADOW_CALL_STACK if HAVE_SHADOW_CALL_STACK
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select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
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select ARCH_USE_MEMTEST
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select ARCH_USE_QUEUED_RWLOCKS
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select ARCH_USES_CFI_TRAPS if CFI_CLANG
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@ -203,4 +203,22 @@
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arch_cmpxchg_relaxed((ptr), (o), (n)); \
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})
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#define arch_cmpxchg64_relaxed(ptr, o, n) \
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({ \
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BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
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arch_cmpxchg_relaxed((ptr), (o), (n)); \
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})
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#define arch_cmpxchg64_acquire(ptr, o, n) \
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({ \
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BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
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arch_cmpxchg_acquire((ptr), (o), (n)); \
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})
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#define arch_cmpxchg64_release(ptr, o, n) \
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({ \
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BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
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arch_cmpxchg_release((ptr), (o), (n)); \
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})
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#endif /* _ASM_RISCV_CMPXCHG_H */
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