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RDMA/hns: Simplify the function config_eqc()
Use "hr_reg_write" replace "roce_set_filed". Link: https://lore.kernel.org/r/1617354454-47840-9-git-send-email-liweihang@huawei.com Signed-off-by: Yixing Liu <liuyixing1@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
This commit is contained in:
Yixing Liu
Jason Gunthorpe
parent
495c24808c
commit
782832f254
@ -6088,6 +6088,16 @@ static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
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hns_roce_mtr_destroy(hr_dev, &eq->mtr);
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}
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static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
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{
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eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG;
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eq->cons_index = 0;
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eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0;
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eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0;
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eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED;
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eq->shift = ilog2((unsigned int)eq->entries);
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}
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static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq,
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void *mb_buf)
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{
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@ -6099,13 +6109,7 @@ static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq,
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eqc = mb_buf;
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memset(eqc, 0, sizeof(struct hns_roce_eq_context));
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/* init eqc */
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eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG;
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eq->cons_index = 0;
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eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0;
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eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0;
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eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED;
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eq->shift = ilog2((unsigned int)eq->entries);
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init_eq_config(hr_dev, eq);
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/* if not multi-hop, eqe buffer only use one trunk */
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count = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, MTT_MIN_COUNT,
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@ -6115,102 +6119,34 @@ static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq,
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return -ENOBUFS;
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}
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/* set eqc state */
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roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQ_ST_M, HNS_ROCE_EQC_EQ_ST_S,
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HNS_ROCE_V2_EQ_STATE_VALID);
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hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID);
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hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num);
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hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore);
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hr_reg_write(eqc, EQC_COALESCE, eq->coalesce);
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hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st);
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hr_reg_write(eqc, EQC_EQN, eq->eqn);
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hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT);
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hr_reg_write(eqc, EQC_EQE_BA_PG_SZ,
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to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift));
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hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ,
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to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift));
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hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX);
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hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt);
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/* set eqe hop num */
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roce_set_field(eqc->byte_4, HNS_ROCE_EQC_HOP_NUM_M,
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HNS_ROCE_EQC_HOP_NUM_S, eq->hop_num);
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/* set eqc over_ignore */
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roce_set_field(eqc->byte_4, HNS_ROCE_EQC_OVER_IGNORE_M,
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HNS_ROCE_EQC_OVER_IGNORE_S, eq->over_ignore);
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/* set eqc coalesce */
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roce_set_field(eqc->byte_4, HNS_ROCE_EQC_COALESCE_M,
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HNS_ROCE_EQC_COALESCE_S, eq->coalesce);
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/* set eqc arm_state */
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roce_set_field(eqc->byte_4, HNS_ROCE_EQC_ARM_ST_M,
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HNS_ROCE_EQC_ARM_ST_S, eq->arm_st);
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/* set eqn */
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roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQN_M, HNS_ROCE_EQC_EQN_S,
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eq->eqn);
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/* set eqe_cnt */
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roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQE_CNT_M,
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HNS_ROCE_EQC_EQE_CNT_S, HNS_ROCE_EQ_INIT_EQE_CNT);
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/* set eqe_ba_pg_sz */
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roce_set_field(eqc->byte_8, HNS_ROCE_EQC_BA_PG_SZ_M,
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HNS_ROCE_EQC_BA_PG_SZ_S,
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to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift));
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/* set eqe_buf_pg_sz */
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roce_set_field(eqc->byte_8, HNS_ROCE_EQC_BUF_PG_SZ_M,
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HNS_ROCE_EQC_BUF_PG_SZ_S,
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to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift));
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/* set eq_producer_idx */
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roce_set_field(eqc->byte_8, HNS_ROCE_EQC_PROD_INDX_M,
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HNS_ROCE_EQC_PROD_INDX_S, HNS_ROCE_EQ_INIT_PROD_IDX);
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/* set eq_max_cnt */
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roce_set_field(eqc->byte_12, HNS_ROCE_EQC_MAX_CNT_M,
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HNS_ROCE_EQC_MAX_CNT_S, eq->eq_max_cnt);
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/* set eq_period */
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roce_set_field(eqc->byte_12, HNS_ROCE_EQC_PERIOD_M,
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HNS_ROCE_EQC_PERIOD_S, eq->eq_period);
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/* set eqe_report_timer */
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roce_set_field(eqc->eqe_report_timer, HNS_ROCE_EQC_REPORT_TIMER_M,
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HNS_ROCE_EQC_REPORT_TIMER_S,
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HNS_ROCE_EQ_INIT_REPORT_TIMER);
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/* set bt_ba [34:3] */
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roce_set_field(eqc->eqe_ba0, HNS_ROCE_EQC_EQE_BA_L_M,
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HNS_ROCE_EQC_EQE_BA_L_S, bt_ba >> 3);
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/* set bt_ba [64:35] */
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roce_set_field(eqc->eqe_ba1, HNS_ROCE_EQC_EQE_BA_H_M,
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HNS_ROCE_EQC_EQE_BA_H_S, bt_ba >> 35);
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/* set eq shift */
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roce_set_field(eqc->byte_28, HNS_ROCE_EQC_SHIFT_M, HNS_ROCE_EQC_SHIFT_S,
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eq->shift);
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/* set eq MSI_IDX */
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roce_set_field(eqc->byte_28, HNS_ROCE_EQC_MSI_INDX_M,
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HNS_ROCE_EQC_MSI_INDX_S, HNS_ROCE_EQ_INIT_MSI_IDX);
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/* set cur_eqe_ba [27:12] */
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roce_set_field(eqc->byte_28, HNS_ROCE_EQC_CUR_EQE_BA_L_M,
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HNS_ROCE_EQC_CUR_EQE_BA_L_S, eqe_ba[0] >> 12);
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/* set cur_eqe_ba [59:28] */
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roce_set_field(eqc->byte_32, HNS_ROCE_EQC_CUR_EQE_BA_M_M,
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HNS_ROCE_EQC_CUR_EQE_BA_M_S, eqe_ba[0] >> 28);
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/* set cur_eqe_ba [63:60] */
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roce_set_field(eqc->byte_36, HNS_ROCE_EQC_CUR_EQE_BA_H_M,
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HNS_ROCE_EQC_CUR_EQE_BA_H_S, eqe_ba[0] >> 60);
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/* set eq consumer idx */
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roce_set_field(eqc->byte_36, HNS_ROCE_EQC_CONS_INDX_M,
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HNS_ROCE_EQC_CONS_INDX_S, HNS_ROCE_EQ_INIT_CONS_IDX);
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roce_set_field(eqc->byte_40, HNS_ROCE_EQC_NXT_EQE_BA_L_M,
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HNS_ROCE_EQC_NXT_EQE_BA_L_S, eqe_ba[1] >> 12);
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roce_set_field(eqc->byte_44, HNS_ROCE_EQC_NXT_EQE_BA_H_M,
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HNS_ROCE_EQC_NXT_EQE_BA_H_S, eqe_ba[1] >> 44);
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roce_set_field(eqc->byte_44, HNS_ROCE_EQC_EQE_SIZE_M,
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HNS_ROCE_EQC_EQE_SIZE_S,
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eq->eqe_size == HNS_ROCE_V3_EQE_SIZE ? 1 : 0);
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hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period);
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hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER);
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hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3);
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hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35);
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hr_reg_write(eqc, EQC_SHIFT, eq->shift);
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hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX);
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hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12);
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hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28);
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hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60);
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hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX);
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hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12);
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hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44);
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hr_reg_write(eqc, EQC_EQE_SIZE,
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!!(eq->eqe_size == HNS_ROCE_V3_EQE_SIZE));
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return 0;
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}
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@ -1990,88 +1990,32 @@ struct hns_roce_dip {
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#define HNS_ROCE_V2_VF_ABN_INT_CFG_M GENMASK(2, 0)
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#define HNS_ROCE_V2_VF_EVENT_INT_EN_M GENMASK(0, 0)
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/* WORD0 */
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#define HNS_ROCE_EQC_EQ_ST_S 0
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#define HNS_ROCE_EQC_EQ_ST_M GENMASK(1, 0)
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#define EQC_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_eq_context, h, l)
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#define HNS_ROCE_EQC_HOP_NUM_S 2
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#define HNS_ROCE_EQC_HOP_NUM_M GENMASK(3, 2)
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#define HNS_ROCE_EQC_OVER_IGNORE_S 4
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#define HNS_ROCE_EQC_OVER_IGNORE_M GENMASK(4, 4)
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#define HNS_ROCE_EQC_COALESCE_S 5
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#define HNS_ROCE_EQC_COALESCE_M GENMASK(5, 5)
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#define HNS_ROCE_EQC_ARM_ST_S 6
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#define HNS_ROCE_EQC_ARM_ST_M GENMASK(7, 6)
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#define HNS_ROCE_EQC_EQN_S 8
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#define HNS_ROCE_EQC_EQN_M GENMASK(15, 8)
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#define HNS_ROCE_EQC_EQE_CNT_S 16
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#define HNS_ROCE_EQC_EQE_CNT_M GENMASK(31, 16)
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/* WORD1 */
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#define HNS_ROCE_EQC_BA_PG_SZ_S 0
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#define HNS_ROCE_EQC_BA_PG_SZ_M GENMASK(3, 0)
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#define HNS_ROCE_EQC_BUF_PG_SZ_S 4
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#define HNS_ROCE_EQC_BUF_PG_SZ_M GENMASK(7, 4)
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#define HNS_ROCE_EQC_PROD_INDX_S 8
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#define HNS_ROCE_EQC_PROD_INDX_M GENMASK(31, 8)
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/* WORD2 */
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#define HNS_ROCE_EQC_MAX_CNT_S 0
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#define HNS_ROCE_EQC_MAX_CNT_M GENMASK(15, 0)
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#define HNS_ROCE_EQC_PERIOD_S 16
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#define HNS_ROCE_EQC_PERIOD_M GENMASK(31, 16)
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/* WORD3 */
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#define HNS_ROCE_EQC_REPORT_TIMER_S 0
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#define HNS_ROCE_EQC_REPORT_TIMER_M GENMASK(31, 0)
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/* WORD4 */
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#define HNS_ROCE_EQC_EQE_BA_L_S 0
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#define HNS_ROCE_EQC_EQE_BA_L_M GENMASK(31, 0)
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/* WORD5 */
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#define HNS_ROCE_EQC_EQE_BA_H_S 0
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#define HNS_ROCE_EQC_EQE_BA_H_M GENMASK(28, 0)
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/* WORD6 */
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#define HNS_ROCE_EQC_SHIFT_S 0
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#define HNS_ROCE_EQC_SHIFT_M GENMASK(7, 0)
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#define HNS_ROCE_EQC_MSI_INDX_S 8
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#define HNS_ROCE_EQC_MSI_INDX_M GENMASK(15, 8)
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#define HNS_ROCE_EQC_CUR_EQE_BA_L_S 16
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#define HNS_ROCE_EQC_CUR_EQE_BA_L_M GENMASK(31, 16)
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/* WORD7 */
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#define HNS_ROCE_EQC_CUR_EQE_BA_M_S 0
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#define HNS_ROCE_EQC_CUR_EQE_BA_M_M GENMASK(31, 0)
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/* WORD8 */
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#define HNS_ROCE_EQC_CUR_EQE_BA_H_S 0
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#define HNS_ROCE_EQC_CUR_EQE_BA_H_M GENMASK(3, 0)
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#define HNS_ROCE_EQC_CONS_INDX_S 8
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#define HNS_ROCE_EQC_CONS_INDX_M GENMASK(31, 8)
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/* WORD9 */
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#define HNS_ROCE_EQC_NXT_EQE_BA_L_S 0
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#define HNS_ROCE_EQC_NXT_EQE_BA_L_M GENMASK(31, 0)
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/* WORD10 */
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#define HNS_ROCE_EQC_NXT_EQE_BA_H_S 0
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#define HNS_ROCE_EQC_NXT_EQE_BA_H_M GENMASK(19, 0)
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#define HNS_ROCE_EQC_EQE_SIZE_S 20
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#define HNS_ROCE_EQC_EQE_SIZE_M GENMASK(21, 20)
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#define EQC_EQ_ST EQC_FIELD_LOC(1, 0)
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#define EQC_EQE_HOP_NUM EQC_FIELD_LOC(3, 2)
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#define EQC_OVER_IGNORE EQC_FIELD_LOC(4, 4)
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#define EQC_COALESCE EQC_FIELD_LOC(5, 5)
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#define EQC_ARM_ST EQC_FIELD_LOC(7, 6)
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#define EQC_EQN EQC_FIELD_LOC(15, 8)
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#define EQC_EQE_CNT EQC_FIELD_LOC(31, 16)
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#define EQC_EQE_BA_PG_SZ EQC_FIELD_LOC(35, 32)
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#define EQC_EQE_BUF_PG_SZ EQC_FIELD_LOC(39, 36)
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#define EQC_EQ_PROD_INDX EQC_FIELD_LOC(63, 40)
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#define EQC_EQ_MAX_CNT EQC_FIELD_LOC(79, 64)
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#define EQC_EQ_PERIOD EQC_FIELD_LOC(95, 80)
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#define EQC_EQE_REPORT_TIMER EQC_FIELD_LOC(127, 96)
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#define EQC_EQE_BA_L EQC_FIELD_LOC(159, 128)
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#define EQC_EQE_BA_H EQC_FIELD_LOC(188, 160)
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#define EQC_SHIFT EQC_FIELD_LOC(199, 192)
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#define EQC_MSI_INDX EQC_FIELD_LOC(207, 200)
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#define EQC_CUR_EQE_BA_L EQC_FIELD_LOC(223, 208)
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#define EQC_CUR_EQE_BA_M EQC_FIELD_LOC(255, 224)
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#define EQC_CUR_EQE_BA_H EQC_FIELD_LOC(259, 256)
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#define EQC_EQ_CONS_INDX EQC_FIELD_LOC(287, 264)
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#define EQC_NEX_EQE_BA_L EQC_FIELD_LOC(319, 288)
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#define EQC_NEX_EQE_BA_H EQC_FIELD_LOC(339, 320)
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#define EQC_EQE_SIZE EQC_FIELD_LOC(341, 340)
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#define HNS_ROCE_V2_CEQE_COMP_CQN_S 0
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#define HNS_ROCE_V2_CEQE_COMP_CQN_M GENMASK(23, 0)
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