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drm/i915/execlists: Pack the count into the low bits of the port.request
add/remove: 1/1 grow/shrink: 5/4 up/down: 391/-578 (-187) function old new delta execlists_submit_ports 262 471 +209 port_assign.isra - 136 +136 capture 6344 6359 +15 reset_common_ring 438 452 +14 execlists_submit_request 228 238 +10 gen8_init_common_ring 334 341 +7 intel_engine_is_idle 106 105 -1 i915_engine_info 2314 2290 -24 __i915_gem_set_wedged_BKL 485 411 -74 intel_lrc_irq_handler 1789 1604 -185 execlists_update_context 294 - -294 The most important change there is the improve to the intel_lrc_irq_handler and excclist_submit_ports (net improvement since execlists_update_context is now inlined). v2: Use the port_api() for guc as well (even though currently we do not pack any counters in there, yet) and hide all port->request_count inside the helpers. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170517121007.27224-5-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson
parent
0ce8178808
commit
77f0d0e925
@ -3353,6 +3353,7 @@ static int i915_engine_info(struct seq_file *m, void *unused)
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if (i915.enable_execlists) {
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u32 ptr, read, write;
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struct rb_node *rb;
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unsigned int idx;
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seq_printf(m, "\tExeclist status: 0x%08x %08x\n",
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I915_READ(RING_EXECLIST_STATUS_LO(engine)),
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@ -3370,8 +3371,7 @@ static int i915_engine_info(struct seq_file *m, void *unused)
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if (read > write)
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write += GEN8_CSB_ENTRIES;
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while (read < write) {
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unsigned int idx = ++read % GEN8_CSB_ENTRIES;
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idx = ++read % GEN8_CSB_ENTRIES;
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seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
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idx,
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I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
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@ -3379,21 +3379,19 @@ static int i915_engine_info(struct seq_file *m, void *unused)
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}
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rcu_read_lock();
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rq = READ_ONCE(engine->execlist_port[0].request);
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if (rq) {
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seq_printf(m, "\t\tELSP[0] count=%d, ",
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engine->execlist_port[0].count);
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print_request(m, rq, "rq: ");
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} else {
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seq_printf(m, "\t\tELSP[0] idle\n");
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}
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rq = READ_ONCE(engine->execlist_port[1].request);
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if (rq) {
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seq_printf(m, "\t\tELSP[1] count=%d, ",
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engine->execlist_port[1].count);
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print_request(m, rq, "rq: ");
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} else {
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seq_printf(m, "\t\tELSP[1] idle\n");
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for (idx = 0; idx < ARRAY_SIZE(engine->execlist_port); idx++) {
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unsigned int count;
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rq = port_unpack(&engine->execlist_port[idx],
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&count);
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if (rq) {
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seq_printf(m, "\t\tELSP[%d] count=%d, ",
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idx, count);
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print_request(m, rq, "rq: ");
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} else {
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seq_printf(m, "\t\tELSP[%d] idle\n",
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idx);
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}
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}
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rcu_read_unlock();
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@ -3019,12 +3019,14 @@ static void engine_set_wedged(struct intel_engine_cs *engine)
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*/
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if (i915.enable_execlists) {
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struct execlist_port *port = engine->execlist_port;
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unsigned long flags;
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unsigned int n;
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spin_lock_irqsave(&engine->timeline->lock, flags);
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i915_gem_request_put(engine->execlist_port[0].request);
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i915_gem_request_put(engine->execlist_port[1].request);
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for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++)
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i915_gem_request_put(port_request(&port[n]));
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memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
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engine->execlist_queue = RB_ROOT;
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engine->execlist_first = NULL;
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@ -1324,12 +1324,17 @@ static void engine_record_requests(struct intel_engine_cs *engine,
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static void error_record_engine_execlists(struct intel_engine_cs *engine,
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struct drm_i915_error_engine *ee)
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{
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const struct execlist_port *port = engine->execlist_port;
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unsigned int n;
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for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++)
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if (engine->execlist_port[n].request)
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record_request(engine->execlist_port[n].request,
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&ee->execlist[n]);
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for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) {
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struct drm_i915_gem_request *rq = port_request(&port[n]);
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if (!rq)
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break;
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record_request(rq, &ee->execlist[n]);
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}
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}
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static void record_context(struct drm_i915_error_context *e,
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@ -653,10 +653,22 @@ static void nested_enable_signaling(struct drm_i915_gem_request *rq)
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spin_unlock(&rq->lock);
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}
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static void port_assign(struct execlist_port *port,
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struct drm_i915_gem_request *rq)
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{
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GEM_BUG_ON(rq == port_request(port));
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if (port_isset(port))
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i915_gem_request_put(port_request(port));
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port_set(port, i915_gem_request_get(rq));
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nested_enable_signaling(rq);
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}
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static bool i915_guc_dequeue(struct intel_engine_cs *engine)
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{
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struct execlist_port *port = engine->execlist_port;
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struct drm_i915_gem_request *last = port[0].request;
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struct drm_i915_gem_request *last = port_request(port);
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struct rb_node *rb;
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bool submit = false;
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@ -670,8 +682,7 @@ static bool i915_guc_dequeue(struct intel_engine_cs *engine)
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if (port != engine->execlist_port)
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break;
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i915_gem_request_assign(&port->request, last);
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nested_enable_signaling(last);
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port_assign(port, last);
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port++;
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}
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@ -681,13 +692,12 @@ static bool i915_guc_dequeue(struct intel_engine_cs *engine)
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rq->priotree.priority = INT_MAX;
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i915_guc_submit(rq);
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trace_i915_gem_request_in(rq, port - engine->execlist_port);
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trace_i915_gem_request_in(rq, port_index(port, engine));
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last = rq;
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submit = true;
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}
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if (submit) {
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i915_gem_request_assign(&port->request, last);
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nested_enable_signaling(last);
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port_assign(port, last);
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engine->execlist_first = rb;
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}
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spin_unlock_irq(&engine->timeline->lock);
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@ -703,17 +713,19 @@ static void i915_guc_irq_handler(unsigned long data)
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bool submit;
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do {
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rq = port[0].request;
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rq = port_request(&port[0]);
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while (rq && i915_gem_request_completed(rq)) {
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trace_i915_gem_request_out(rq);
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i915_gem_request_put(rq);
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port[0].request = port[1].request;
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port[1].request = NULL;
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rq = port[0].request;
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port[0] = port[1];
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memset(&port[1], 0, sizeof(port[1]));
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rq = port_request(&port[0]);
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}
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submit = false;
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if (!port[1].request)
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if (!port_count(&port[1]))
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submit = i915_guc_dequeue(engine);
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} while (submit);
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}
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@ -1233,7 +1233,7 @@ bool intel_engine_is_idle(struct intel_engine_cs *engine)
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return false;
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/* Both ports drained, no more ELSP submission? */
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if (engine->execlist_port[0].request)
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if (port_request(&engine->execlist_port[0]))
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return false;
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/* Ring stopped? */
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@ -337,39 +337,32 @@ static u64 execlists_update_context(struct drm_i915_gem_request *rq)
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static void execlists_submit_ports(struct intel_engine_cs *engine)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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struct execlist_port *port = engine->execlist_port;
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u32 __iomem *elsp =
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dev_priv->regs + i915_mmio_reg_offset(RING_ELSP(engine));
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u64 desc[2];
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engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine));
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unsigned int n;
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GEM_BUG_ON(port[0].count > 1);
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if (!port[0].count)
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execlists_context_status_change(port[0].request,
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INTEL_CONTEXT_SCHEDULE_IN);
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desc[0] = execlists_update_context(port[0].request);
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GEM_DEBUG_EXEC(port[0].context_id = upper_32_bits(desc[0]));
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port[0].count++;
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for (n = ARRAY_SIZE(engine->execlist_port); n--; ) {
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struct drm_i915_gem_request *rq;
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unsigned int count;
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u64 desc;
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if (port[1].request) {
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GEM_BUG_ON(port[1].count);
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execlists_context_status_change(port[1].request,
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INTEL_CONTEXT_SCHEDULE_IN);
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desc[1] = execlists_update_context(port[1].request);
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GEM_DEBUG_EXEC(port[1].context_id = upper_32_bits(desc[1]));
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port[1].count = 1;
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} else {
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desc[1] = 0;
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rq = port_unpack(&port[n], &count);
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if (rq) {
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GEM_BUG_ON(count > !n);
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if (!count++)
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execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
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port_set(&port[n], port_pack(rq, count));
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desc = execlists_update_context(rq);
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GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc));
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} else {
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GEM_BUG_ON(!n);
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desc = 0;
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}
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writel(upper_32_bits(desc), elsp);
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writel(lower_32_bits(desc), elsp);
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}
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GEM_BUG_ON(desc[0] == desc[1]);
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/* You must always write both descriptors in the order below. */
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writel(upper_32_bits(desc[1]), elsp);
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writel(lower_32_bits(desc[1]), elsp);
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writel(upper_32_bits(desc[0]), elsp);
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/* The context is automatically loaded after the following */
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writel(lower_32_bits(desc[0]), elsp);
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}
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static bool ctx_single_port_submission(const struct i915_gem_context *ctx)
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@ -390,6 +383,17 @@ static bool can_merge_ctx(const struct i915_gem_context *prev,
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return true;
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}
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static void port_assign(struct execlist_port *port,
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struct drm_i915_gem_request *rq)
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{
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GEM_BUG_ON(rq == port_request(port));
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if (port_isset(port))
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i915_gem_request_put(port_request(port));
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port_set(port, port_pack(i915_gem_request_get(rq), port_count(port)));
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}
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static void execlists_dequeue(struct intel_engine_cs *engine)
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{
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struct drm_i915_gem_request *last;
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@ -397,7 +401,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
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struct rb_node *rb;
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bool submit = false;
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last = port->request;
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last = port_request(port);
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if (last)
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/* WaIdleLiteRestore:bdw,skl
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* Apply the wa NOOPs to prevent ring:HEAD == req:TAIL
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@ -407,7 +411,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
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*/
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last->tail = last->wa_tail;
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GEM_BUG_ON(port[1].request);
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GEM_BUG_ON(port_isset(&port[1]));
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/* Hardware submission is through 2 ports. Conceptually each port
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* has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
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@ -464,7 +468,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
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GEM_BUG_ON(last->ctx == cursor->ctx);
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i915_gem_request_assign(&port->request, last);
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if (submit)
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port_assign(port, last);
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port++;
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}
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@ -474,12 +479,12 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
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cursor->priotree.priority = INT_MAX;
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__i915_gem_request_submit(cursor);
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trace_i915_gem_request_in(cursor, port - engine->execlist_port);
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trace_i915_gem_request_in(cursor, port_index(port, engine));
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last = cursor;
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submit = true;
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}
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if (submit) {
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i915_gem_request_assign(&port->request, last);
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port_assign(port, last);
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engine->execlist_first = rb;
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}
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spin_unlock_irq(&engine->timeline->lock);
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@ -488,16 +493,11 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
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execlists_submit_ports(engine);
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}
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static bool execlists_elsp_idle(struct intel_engine_cs *engine)
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{
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return !engine->execlist_port[0].request;
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}
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static bool execlists_elsp_ready(const struct intel_engine_cs *engine)
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{
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const struct execlist_port *port = engine->execlist_port;
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return port[0].count + port[1].count < 2;
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return port_count(&port[0]) + port_count(&port[1]) < 2;
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}
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/*
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@ -547,7 +547,9 @@ static void intel_lrc_irq_handler(unsigned long data)
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tail = GEN8_CSB_WRITE_PTR(head);
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head = GEN8_CSB_READ_PTR(head);
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while (head != tail) {
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struct drm_i915_gem_request *rq;
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unsigned int status;
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unsigned int count;
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if (++head == GEN8_CSB_ENTRIES)
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head = 0;
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@ -575,22 +577,26 @@ static void intel_lrc_irq_handler(unsigned long data)
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/* Check the context/desc id for this event matches */
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GEM_DEBUG_BUG_ON(readl(buf + 2 * head + 1) !=
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port[0].context_id);
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port->context_id);
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GEM_BUG_ON(port[0].count == 0);
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if (--port[0].count == 0) {
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rq = port_unpack(port, &count);
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GEM_BUG_ON(count == 0);
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if (--count == 0) {
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GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED);
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GEM_BUG_ON(!i915_gem_request_completed(port[0].request));
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execlists_context_status_change(port[0].request,
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INTEL_CONTEXT_SCHEDULE_OUT);
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GEM_BUG_ON(!i915_gem_request_completed(rq));
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execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT);
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trace_i915_gem_request_out(rq);
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i915_gem_request_put(rq);
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trace_i915_gem_request_out(port[0].request);
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i915_gem_request_put(port[0].request);
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port[0] = port[1];
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memset(&port[1], 0, sizeof(port[1]));
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} else {
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port_set(port, port_pack(rq, count));
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}
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GEM_BUG_ON(port[0].count == 0 &&
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/* After the final element, the hw should be idle */
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GEM_BUG_ON(port_count(port) == 0 &&
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!(status & GEN8_CTX_STATUS_ACTIVE_IDLE));
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}
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@ -1147,6 +1153,7 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
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struct drm_i915_private *dev_priv = engine->i915;
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struct execlist_port *port = engine->execlist_port;
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unsigned int n;
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bool submit;
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int ret;
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ret = intel_mocs_init_engine(engine);
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@ -1168,19 +1175,21 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
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/* After a GPU reset, we may have requests to replay */
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clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
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submit = false;
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for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) {
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if (!port[n].request)
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if (!port_isset(&port[n]))
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break;
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DRM_DEBUG_DRIVER("Restarting %s:%d from 0x%x\n",
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engine->name, n,
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port[n].request->global_seqno);
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port_request(&port[n])->global_seqno);
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/* Discard the current inflight count */
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port[n].count = 0;
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port_set(&port[n], port_request(&port[n]));
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submit = true;
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}
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if (!i915.enable_guc_submission && !execlists_elsp_idle(engine))
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if (submit && !i915.enable_guc_submission)
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execlists_submit_ports(engine);
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return 0;
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@ -1258,13 +1267,13 @@ static void reset_common_ring(struct intel_engine_cs *engine,
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intel_ring_update_space(request->ring);
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/* Catch up with any missed context-switch interrupts */
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if (request->ctx != port[0].request->ctx) {
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i915_gem_request_put(port[0].request);
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if (request->ctx != port_request(port)->ctx) {
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||||
i915_gem_request_put(port_request(port));
|
||||
port[0] = port[1];
|
||||
memset(&port[1], 0, sizeof(port[1]));
|
||||
}
|
||||
|
||||
GEM_BUG_ON(request->ctx != port[0].request->ctx);
|
||||
GEM_BUG_ON(request->ctx != port_request(port)->ctx);
|
||||
|
||||
/* Reset WaIdleLiteRestore:bdw,skl as well */
|
||||
request->tail =
|
||||
|
||||
@ -368,8 +368,15 @@ struct intel_engine_cs {
|
||||
/* Execlists */
|
||||
struct tasklet_struct irq_tasklet;
|
||||
struct execlist_port {
|
||||
struct drm_i915_gem_request *request;
|
||||
unsigned int count;
|
||||
struct drm_i915_gem_request *request_count;
|
||||
#define EXECLIST_COUNT_BITS 2
|
||||
#define port_request(p) ptr_mask_bits((p)->request_count, EXECLIST_COUNT_BITS)
|
||||
#define port_count(p) ptr_unmask_bits((p)->request_count, EXECLIST_COUNT_BITS)
|
||||
#define port_pack(rq, count) ptr_pack_bits(rq, count, EXECLIST_COUNT_BITS)
|
||||
#define port_unpack(p, count) ptr_unpack_bits((p)->request_count, count, EXECLIST_COUNT_BITS)
|
||||
#define port_set(p, packed) ((p)->request_count = (packed))
|
||||
#define port_isset(p) ((p)->request_count)
|
||||
#define port_index(p, e) ((p) - (e)->execlist_port)
|
||||
GEM_DEBUG_DECL(u32 context_id);
|
||||
} execlist_port[2];
|
||||
struct rb_root execlist_queue;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user